CONFIDENTIAL

UTM
UNIVERSITI TEKNOLOGI MALAYSIA

FINAL EXAMINATION SEMESTER II

SESSION 2010/2011
COURSE CODE

SEL 4743

COURSE NAME

BASIC DIGITAL VLSI

LECTURERS

PROF. DR. MOHAMED KHALIL BIN

MOHD HANI
DR. SHAIKH NASIR BIN SHAIKH HUSIN
MR. ZULKIFLI BIN MD YUSOF

PROGRAMME

SEC / SEL / SEW / SET

SECTION

01-02

TIME

2 HOURS 30 MINUTES

DATE

14 MAY 2011

INSTRUCTION TO CANDIDATE

ANSWER FOUR (4) QUESTIONS ONLY.

THIS EXAMINATION BOOKLET CONSISTS OF 6 PAGES INCLUDING THE FRONT COVER

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2
FORMULAE & PARAMETERS:
Supply voltage: Vdd = 2.5 V
Drain current:

'

T _|Kj-|Frl)Fmi,-5FL,](i+UV

Vmin =

DS |

min( |Vgs| - |Vt|, |Vds| |Vdsat| )

V t = V to + y

Standard transistor parameters:

Vto (V) Y Cv )
0.43
NMOS
0.4
PMOS
-0.4
-0.4

<Pf(V) Vdsat (V)

-0.3
0.63
0.3
-1

k' (|iA/V")
115
-30

MV'1)
0.06
-0.1

Question 1
(a)

Calculate the current for a pMOS transistor for the cases in Table 1.

(i)
(ii)
(iii)
(iv)

(b)

W/L
1.35 nm/0.3 |im
1.35 fim/0.3 n.m
1.35 nm/0.3
4.5 pm/1.5 fim

Table 1
VGS (V)
-1
-1
-1.5
-1.6

VDS (V)
-0.5
-0.8
-1.4
-1.5

[12 marks]

VBS (V)
0
1
0
0

Both transistors in Fig. 1 have identical size. Determine the voltage for Vx. Ignore
body effect in your calculation.
[13 marks]
VDD = 2.5 V

Fig. 1

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Question 2
(a)

Refer to the circuit in Fig. 2.

(i) Write the Boolean equation for output Y.

[5 marks]

(ii) Minimize the Boolean equation such that it can be implemented using eight
transistors only.
[4 marks]
(iii) Draw a new schematic circuit based on your minimized Boolean equation.
[6 marks]

A HI

hc[ hcJ

HI
HI

b hiz

a nr

Fig. 2

(b)

(i) Draw a pseudo-nMOS circuit for 2-input NAND gate.

[3 marks]

(ii) Choose the size of the nMOS transistors for your circuit to ensure the output low
value Vql is below 0.2 V. Given (W/L)p = 0.9 nm/0.6 ^m.
[7 marks]

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Question 3
(a)

Refer to the circuit in Fig. 3(a).

(i) The size of Ml transistor is W/L = 2.7 fim/0.3 (im. Size the other seven transistors
such that the tpHL and tpLH of the gate is equivalent to an inverter with (W/L)p = 0.9
Hm/0.3 urn and (W/L)n = 0.45 |j.m/0.3 urn.
[8 marks]
(ii) Draw a stick diagram corresponding to the circuit. Use the convention shown in
Fig. 3(b).You should use a single active strip for both PMOS and NMOS
transistors, and you must minimize the output capacitance.
[7 marks]

x
Fig. 3(a)

(b)

active
poly
metal 1
contact cut

Fig. 3(b)

Fig. 3(c) shows a layout for the pull-down network of a CMOS circuit.
(i) Draw the corresponding transistor schematic for the layout.

[6 marks]

(ii) State the size (W and L) of all transistors in unit of L In Fig. 3(c), 1 grid = 1 L
You can label the size next to each transistor in your schematic for part (b)(i)
above.
[4 marks]

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ndiff

pdiff

poly

metal 1
I active
I contact

vss

bar

bar

AC

bar

Fig. 3(c)

Question 4
A chain of four inverters is shown in Fig. 4. The second and fourth inverters drive an external
load, as indicated. Assume each inverter has a symmetrical VTC, and C int = C g (Y = 1).
Equivalent input capacitance of unit-sized inverter is C.
In

Out

s, = l

s2 = ? Jj4

C S', = 4

X
T

C = 16 C

Fig. 4

(a)

Obtain the optimal sizing factors S2 and S4 for minimum propagation delay.
[10 marks]

(b)

Determine the minimum delay (in terms of t p o ) for the inverter chain.

[5 marks]

(c)

If the 4C load does not exist, and only the output load remains, determine the lowest
possible delay attainable, using unlimited number of inverters.
[10 marks]

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Question 5
(a)

A logic gate network is shown in Fig. 5(a). The input inverter size is (W/L)p = 4 7J2 X
and (W/L)n = 3 )J2 X. The input capacitance Cin = 6 fF, while the output capacitance
Cl = 256 fF. Use logical effort approach to optimize the sizes (in X unit) of inverter sO
and NAND gate si to minimize delay for the logic network. Assume C int = C g(y = 1).
The logical effort g for the NAND gate is 4/3.
[10 marks]

Fig. 5(a)

(b)

A similar logic gate network is shown in Fig. 5(b). The only difference is the input
inverter gO now drives three similarly sized inverters sOa - sOc. Determine the new
sizing for the inverters and NAND gate to achieve minimum delay.
[15 marks]

Fig. 5(b)