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The ideal ADC quantizes its input with the practical result of adding noise to the
input signal. This noise is called as the quantization noise. Quantization noise is
the effective noise added to a signal after passing through an ADC. This chapter
discusses how to determine the actual signal to noise ratio (SNR) of a data
conversion system and topologies for improving the data conversion systems
SNR
SNR ideal =
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Taking z transforms
the circuitry, the rate at which these samples are generated is lowered.
new = 2B =
This reduction in sampling frequency is called decimation or down
sampling.
In the time domain the input and output of the decimating filter is
The decimation filter will take K samples add them and the result in divided by K.
Taking the z transform of Eq.
Fig.
shows one circuit to implement the above Eq. and is called the
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Latches L1 are used to accumulate the K samples and Latches L2 are used to dump
the sum, hence the name accumulate and dump. First the set of latches L1 are reset.
The sampling clock is used to clock L1 K times until the sum of K inputs is
accumulated. The accumulated sum is dumped into L2. At the same time L1 starts
the process of accumulating the next set of K samples. To find the frequency
response of the circuit Z is set to
=
The frequency response of the accumulate and dump for K=2 and K=4 are shown
in Fig. These are called sinc filters for obvious reasons.
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Averaging filter :
To implement averaging filter on the chip, the transfer function is split into
the numerator and denominator.
This implies there are L differentiators and L integrators. Fig. shows the
block diagram of a digital integrator and digital differentiator.
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analog out
DAC
RCF
clk
The input signal to the interpolator is digital. This input band limited to B is
connected to a set of latches clocked at 2B. The output of these latches is
connected to the digital filter which is clocked at 8B. The signal is then given to
the second stage interpolator. The amplitude of the spectrum reduces after passing
through the second stage interpolator. The word size and world rate increases. The
reconstruction filter RCF attenuates the unwanted spectral contents.
Summary :
This chapter characterized a system using ADCs and DACs in terms of the
signal to noise ratio (SNR). The data converter performance can be measured by
ENOB, spurious free dynamic range and signal to noise plus distortion ratio. The
effect of clock jitter was presented. Clock jitter is the variation in the period of the
clock signal around the ideal value. To reduce the quantization noise voltage
averaging is used.
Not only averaging but decimation is employed in decimating filter. To
implement averaging filters on the chip, the transfer function is split into L
differentiators and L integrators.
From the magnitude and frequency response of the differentiators or comb
filters it was observed that by cancelling zeros on the unit circle yielded different
types of filters. A digital resonator was employed to cancel zeros. The
interpolation filter was used to up sample the input signals.
The interpolation and decimation fitters are used in DACs and ADCs. One
application of this is in the digital audio field where different frequencies are
required for broad casting, for compact discs and audio tapes. Both up sampling
and down sampling are employed.
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