LCD Profilo Telra PT1000

26-32 LCD-TV
PT1000
26'' - 32 '' LCD-TV PT1000 Service Manual

__________________________________________________________________________________________________________________
CONTENTS
1.
2.
3.
4.
5.
6.
7.
8.
Assembling/Disassembling Procedure
Safety Instructions and Warnings
Specifications
Block Diagrams and Connections
Menu Structure
Circuit Diagrams and Printed Circuit Board Layouts
Troubleshooting
Data Sheets
.................... 04
.................... 09
.................... 12
.................... 17
.................... 30
.................... 34
.................... 52
TECH2949PS40A(D)
.................... 53
CAT24WC01/02/04/08/16
1K/2K/8K/16K-Bit Serial EEPROM
.................... 55
74HC4066; 74HCT4066
Quad bilateral switches
.................... 56
CD4069UBC
Inverter Circuits
.................... 58
EDD1232AAFA (4M wordsx32 bits)

128M bits DDR SDRAM
.................... 59
EN29LV040
4 Megabit (512k x 8-bit) Uniform Sector,
CMOS 3.0 Volt-only Flash Memory
.................... 61
FDC6326L
Integrated Load Switch
.................... 63
IL1117A-x
1.0A Low Dropout Positive Voltage Regulator
..................... 64
MST6181LDA
SXGA/WXGA LCD Multi-Function Monitor
Controller with Dual LVDS transmitter
Preliminary Data Sheet Version 0.2
..................... 66
MTV512M
8051 Embedded Monitor Controller with
64K Flash ROM
..................... 76
RC1117
1A Adjustable/Fixed Low Dropout
Linear Regulator
..................... 79
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2
26'' - 32'' LCD-TV PT1000 Service Manual

_________________________________________________________________________________________________________
TPA3004D2
12-W STEREO CLASS-D AUDIO POWER
AMPLIFER WITH DC VOLUME CONTROL
.................... 81
TPA6110A2
150-m W STEREO AUDIO POWER
AMPLIFIER
.................... 85
TW9906
3x10-bit Multi-Standard Comb Filter Video
decoder with YcbCr Component Input
.................... 87
VCT 49xyl, VCT 48xyl
.................... 89
WM8725
99dB Stereo DAC
....................101
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3

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1. Assembling/ Disassembling Procedure

Please follow the assembly instructions explained below;
NOTE: Make sure that the power cord is disconnected from the outlet.
Pay special attention not to break or damage the parts.
When removing each board, remove the connectors as required.
Taking notes of the connecting points (connector numbers) makes service
procedure manageable.
Make sure that there is no bent or stain on the connectors before inserting, and
firmly insert the connectors.
Be sure that all cables are free. If necessary fix the cables firmly to avoid any kind
of squeezing while placing the boards back.
If possible before starting every each stage of disassembly take a photo.
Keep all screws and other components in safety place.
Do not store components in a moist , dusty and dirty place.
Disassambly ordering:
1-) Remove Back Cover
2-) Remove Stand Group
3-) Remove DVD Holder and DVD (or wireless holder and PCB)
4-) Remove Switch Box
5-) Remove Power Board and Main Board
6-) Remove Board Base Metal (or plastic)
7-) Remove Power Cable
8-) Remove LCD Panel keepers (plastics or metals)
9-) Remove LCD panel
10-) Remove all cables and connectors from Side AV.
11-) Remove Side AV holder and PCB
12-) Remove Multibutton holder and PCB from Cabinet
13-) Remove Multibutton PCB and Multibuttons from Multibutton_Holder
14-) Remove Tweeters and Speakers from Cabinet
15-) Remove Standby&Infrared PCB from its holder
16-) Remove Acrylic standby button, and LED holder from Cabinet.
17-) Remove Eject button and PCB
Assembly ordering:
The assembly ordering is exactly reverse of disassembly ordering. In any doubt, look
photos, which you have taken before, and check, exploded view.
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4
NO.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
39.
40.
41.
42.
43.
44.
45.
46.
DESCRIPTION
FRONT CABINET
LCD PANEL
LCD PANEL HOLDER
LCD PANEL HOLDER SCREW
MULTIBUTTON
MULTIBUTTON PCB
MULTIBUTTON PCB SCREW
SIDE AV HOLDER
SIDE AV HOLDER SCREW
SIDE AV PCB
SIDE AV PCB SCREW
REFLECTOR
INFRA LED PCB
INFRA LED PCB SCREW
SPEAKER
SPEAKER SCREW
EJECT BUTTON
EJECT BUTTON PCB
EJECT BUTTON PCB SCREW
STAND HOLDER SHEET
STAND HOLDER SHEET SCREW
COVER PART
COVER PART SCREW
MMC CARD HOLDER
MMC CARD HOLDER SCREW
MMC CARD PCB
MMC CARD PCB SCREW
MAIN BOARD HOLDER
MAIN BOARD HOLDER SCREW
MAIN BOARD AVISOL
MAIN BOARD SCREW
POWER BOARD HOLDER
POWER BOARD HOLDER SCREW
POWER BOARD
DVD LOADER HOLDER
DVD LOADER HOLDER SCREW
DVD LOADER
VESA STANDARD SHEET
VESA STANDARD SHEET SCREW
PLASTIC STAND
PLASTIC STAND SHEET
PLASTIC STAND SHEET SCREW
PLASTIC STAND BOTTOM SHEET
PLASTIC STAND BOTTOM SHEET SCREW
BACKCOVER DVD
BACKCOVER DVD SCREW
EXPLODED WIEW PART LIST
NO.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
37.
38.
DESCRIPTION
FRONT CABINET
FRAME CMO/FRAME OTHER
PANEL CMO/SM/AUO/LG
BOARD HOLDER (METAL)
PANEL HOLDER (TOP-BOTTOM)
PANEL HOLDER (SIDE)
EJECT PCB
EJECT BUTTON
VESA METAL 200X200
BACK COVER
PHILIPS SPEAKER
SPEAKER RUBBER
SIDE AV
MULTIBUTTON
MULTIBUTTON PCB
CONTROL PCB
CMO PANEL FIXING (LEFT)
CMO PANEL FIXING (RIGHT)
CASON SLOT DVD
DVD HOLDER
POWER BOARD
AVISOL MAIN BOARD
CABLE STOPPER
MAINS CORD
PANEL HOLDER (LEFT)
PANEL HOLDER (RIGHT)
BOTTOM COVER
HOLDER FIXING METAL
STAND
HOLDER METAL
STAND SHIELD
FOOT RUBBERS
LABEL
ON-OFF SWITCH
LG FIXING (BOTTOM)
LG FIXING (TOP)
LG HOLDER (BOTTOM)
LG HOLDER (TOP)
EXPLODED WIEW PART

LIST
DESCRIPTION
FRONT CABINET V01 INSERT

LCD PANEL (LG / AUO / SAMSUNG)
BACK COVER (DVD INSERT)
PANEL COVER METAL
POWER BOARD
EJECT BUTTON HOLDER
EJECT BUTTON
EJECT PCB
DVD LOADER
PANEL FIXING PLASTICS
DVD HOLDER
MAIN BOARD
SWITCH COVER
AV PCB(20" COLORFUL)
I/O SWITCH
MULTI BUTTON
MULTI BUTTON PCB
AV PCB / MULTI BUTTON PCB HOLDER
SPEAKER VIBRATION RUBBER
SPEAKER VIBRATION PLASTIC
SPEAKER
STAND-BY PCB
MCR HOLDER
MCR PCB
REFLECTOR
STAND-BY REFLECTOR
STAND-BY BUTTON
METAL FOOD
FRONT SHUTTER
PLASTIC STAND
STAND SHIELD
NO.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.

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NO.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13 .
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
DESCRIPTION
FRONT CABINET V02 INSERT
LCD PANEL (LG / AUO / SAMSUNG)
BACK COVER V02 (DVD INSERT)
PANEL COVER METAL
POWER BOARD
EJECT BUTTON HOLDER
EJECT BUTTON
EJECT PCB
DVD LOADER
PANEL FIXING PLASTICS
DVD HOLDER
MAIN BOARD
SWITCH COVER
AV PCB(20" COLORFUL)
I/O SWITCH
MULTI BUTTON V02
MULTI BUTTON PCB V02
SIDEAV PCB HOLDER V02
SPEAKER VIBRATION RUBBER
SPEAKER VIBRATION PLASTIC
SPEAKER
STAND-BY PCB V02
MCR HOLDER
MCR PCB
REFLECTOR V02
STAND-BY REFLECTOR V02
MENU BUTTON
METAL FOOD V02
FRONT SHUTTER V02
PLASTIC STAND V02
STAND SHIELD V02

__________________________________________________________________________________________________________________
__________________________________________________________

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2. SAFETY INSTRUCTIONS AND PRECAUTIONS

1. Use only the original spare parts with the same specifications for replacement.
2. Only the original fuse value should be used.
3. Safety components should be replaced by components identical to the original
ones.
4. Main leads and connecting leads should be checked for external damage before
connection. Insulation must be checked.
5. Parts contributing to the safety of the product must not be damaged or obviously
unsuitable. This is valid especially for insulators and insulating parts.
6. Thermally loaded solder pads are to be sucked off and re-soldered.
7. Ensure that the ventilation slots are not obstructed.
8. Servicing should not be attempted by anyone who is not thoroughly familiar with
precautions necessary when working on high voltage equipment. Perfectly
discharge the high potential of the picture tube before handling it. The picture
tube is highly evacuated and if broken. Glass fragments will be violently expelled.
Always discharge the picture tube anode to the receiver chassis to keep of the
shock hazard before removing the anode cap.
9. Keep wire away from the high voltage or high temperature components.
10. When replacing a wattage resistor, keep the resistor 10mm away from the circuit
board.
HANDLING THE MOS CHIP COMPONENTS

MOS circuit requires special attention with regard to static charges. Static charges
may occur with any highly insulated plastics and can be transferred to persons
wearing clothes and shoes made of synthetic materials. Protective circuits on the
inputs and outputs of MOS circuits give protection to a limited extend only due to
time of reaction.
Please observe the following instructions to protect the components against ESD.
1. Keep MOS components in conductive package until they are used. Most
components must never be stored in styropor materials or plastic magazines.
2. Personnel must not touch the MOS components to avoid electrostatic
discharging.
3. Hold the component by the body touching the terminals.
4. Use only grounded instruments for testing and processing purposes.
5. Remove or connect MOS Ics when operating voltage is disconnected.
6. Personnel in charge must make sure that they are connected with the same
potential as the mass of the set by a wristband with resistance.
2.1. Precautions
Please pay attention to the followings when you use this TFT LCD module.
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9

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2.1.1. Mounting Precautions

(1) You must mount a module using holes arranged in four corners or four sides.
(2) You should consider the mounting structure so that uneven force (ex. Twisted
stress) is not applied to the module. And the case on which a module is
mounted should have sufficient strength so that external force is not
transmitted directly to the module.
(3) Please attach the surface transparent protective plate to the surface in order
to protect the polarizer. Transparent protective plate should have sufficient
strength in order to the resist external force.
(4) You should adopt radiation structure to satisfy the temperature
specification.
(5) Acetic acid type and chlorine type materials for the cover case are not
desirable because the former generates corrosive gas of attacking the
polarizer at high temperature and the latter causes circuit break by electrochemical reaction.
(6) Do not touch, push or rub the exposed polarizer with glass, tweezers or
anything harder than HB pencil lead. And please do not rub with dust clothes
with chemical treatment. Do not touch the surface of polarizer for bare hand
or greasy cloth. (Some cosmetics are detrimental to the polarizer.)
(7) When the surface becomes dusty, please wipe gently with absorbent cotton or
other soft materials like chamois soaks with petroleum benzine. Normalhexane is recommended for cleaning the adhesives used to attach front / rear
polarizers. Do not use acetone, toluene and alcohol because they cause
chemical damage to the polarizer.
(8) Wipe off saliva or water drops as soon as possible. Their long time contact
with polarizer causes deformations and color fading.
(9) Do not open the case because inside circuits do not have sufficient strength.
2.1.2 Operating Precautions
(1) The spike noise causes the mis-operation of circuits. It should be lower than
following voltage: V=200mV(Over and under shoot voltage)
(2) Response time depends on the temperature. (In lower temperature, it becomes
longer.)
(3) Brightness depends on the temperature. (In lower temperature, it becomes
lower.) And in lower temperature, response time (required time that brightness is
stable after turned on) becomes longer.
(4) Be careful for condensation at sudden temperature change. Condensation makes
damage to polarizer or electrical contacted parts. And after fading condensation,
smear or spot will occur.
(5) When fixed patterns are displayed for a long time, remnant image is likely
to occur.
(6) Module has high frequency circuits. Sufficient suppression to the electromagnetic
interference shall be done by system manufacturers. Grounding and shielding
methods may be important to minimize the interference.
(7) Please do not give any mechanical and/or acoustical impact to LCM. Otherwise,
LCM cant be operated its full characteristics perfectly.
(8)A screw, which is fastened up the steels, should be a machine screw. (if not, it
__________________________________________________________________________
10

__________________________________________________________________________________________________________________
causes metallic foreign material and deal LCM a fatal blow)

(9) Please do not set LCD on its edge.
2.1.3. Electrostatic Discharge Control
Since a module is composed of electronic circuits, it is not strong to electrostatic
discharge. Make certain that treatment persons are connected to ground through
wrist band etc. And dont touch interface pin directly.
2.1.4. Precautions for Strong Light Exposure

Strong light exposure causes degradation of polarizer and color filter.
2.1.5. Storage
When storing modules as spares for a long time, the following precautions are
necessary.
(1) Store them in a dark place. Do not expose the module to sunlight or fluorescent
light. Keep the temperature between 5C and 35C at normal humidity.
(2) The polarizer surface should not come in contact with any other object. It is
recommended that they be stored in the container in which they were shipped.
2.1.6. Handling Precautions for Protection Film

(1) The protection film is attached to the bezel with a small masking tape. When the
protection film is peeled off, static electricity is generated between the film
and polarizer. This should be peeled off slowly and carefully by people who
are electrically grounded and with well ion-blown equipment or in such a
condition, etc.
(2) When the module with protection film attached is stored for a long time,
sometimes there remains a very small amount of glue still on the bezel after
the protection film is peeled off.
(3) You can remove the glue easily. When the glue remains on the bezel surface or
its vestige is recognized, please wipe them off with absorbent cotton waste or
other soft material like chamois soaked with normal-hexane.
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11

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3.Specifications
3.1 Technical Specifications
Panel
26"
16:9
1366 x 768
284.16 x 213.12
500 cd/m2
600:1 / 800:1
H/V: 140/115
8ms(GtG)
Aspect Ratio
Resolution (*)
Active Area(mm) (*)
Brightness (typ) (*)
Contrast Ratio (typ) (*)
Viewing Angle (H/V degree) (typ) (*)
Response Time (typ) (*)
32"
16:9
1366x768
500 / 550 cd/m2
800:1 / 1000:1 /1200:1
8ms(GtG)
Picture
-z
z
z
z
z
z
z
z
z
z
z
Cool1/2, Warm1/2, Normal
Standart-Dynamic-Soft-User
16:9, 14:9, Cinema, 4:3, Auto
Full HD(1080p) support

INVATEK Engine
3D DNR (Digital Noise Reduction)
3D MADI (Motion Adaptive De-Interlacer)
Digital Comb Filter
DLTI/DCTI
DLC (Dynamic Luminance Control)
3/2 - 2/2 motion pull down
STC (Skin Tone Control)
BWS (Black & White Stretch)
PMR(Picture Mode Recognition)
Freeze
Color Temperature Selection
Pre-set Picture Modes
Picture Formats
Tuning
PLL
z
z
z
z
z
99
z
z
Tuner
TV-Standards PAL BG / DK / I ; SECAM BG/ DK / LL'
NTSC 4.43MHz / 3.58MHz Playback
Auto Programming
ATS Euro Plus Tuning System
Fine-tuning
Program storage capacity
VHF / UHF
Ch. coverage CATV / Hyperband (S1-S41)
Teletext
Flof teletext
Teletext capability in OSD Languages
T.Text Page Memory
General Features
HD Ready
Bitmap GUI (Graphic OSD)
OSD Menu in multi languages
On/Off Timer
Auto shut-off
Program Lock
Program naming
PIP Options
PIP via PC/Component/HDMI(or DVI)
PIP via AV
PIP double tuner
PAP available w/ PIP double tuner
PIP(Analog/ Digital) optional for IDTV
PIP size/Position Adjustment
z
z
250 pages
z
z
z
z
z
z
z
available with PIP double tuner
available with PIP double tuner
{
{
{
{
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12

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Sound
z
z
z
flat, speech, music, movie, user
z
z
z
2 x 8W (<10%THD)
A2 + Nicam stereo
Auto Volume Level
Sound Effect(Spatial Effect)
Pre-set sound modes
Balance
Treble
Bass
Audio output power (rms)
Connections
Side Connections
Video CVBS In, Audio L/R In
Headphone Output
Rear Connections
Antenna input ( 75 ohm IEC )
1st Scart (RGB, CVBS In/Out, Audio L/R)
2nd Scart (CVBS In/Out, , Audio L/R)
Video CVBS Out, Audio L/R Out (AV-OUT)
YPbPr Video In, Audio L/R In
COMPONENT (YPbPr) Modes
S-Video In, Audio L/R In(Cinch)
VGA Analog PC Input (D-Sub 15P )
HDMI(w/ HDCP)
2nd HDMI(w/ HDCP) w/ full hd chassis
HDMI / PC Audio In
CI Slot (available w/ IDTV)
z
z
z
z
z
z
z
480i : 59.94/60Hz, 480P : 59.94/60Hz 576i : 50Hz,
576P : 50Hz 720P : 59.94/60Hz, 1080i : 50/59.94/60Hz
z
z
z
-z
{
Accessories
TM3602 / TM64 DVD-TV / TM4901IDTV
Remote Control Unit
z : standard { : optional
* These specifications are dependent on the panel brand/ver. & panel manufacturer's changes.
Specifications are subject to change without notice.
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13

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3.2Electrical Specifications
Electrical Specifications
No.
Description
Item
Remarks
Min
Typ
Max
For Audio
For Standby
For Logic
11.4
12.0
12.6
4.8
5.0
5.2
4.8
5.0
5.2
For Tuner
32.5
33.0
33.5
DPMS
Sync (V/H)
VIDEO
Power (V/A)
LED
Stand By, Sleep & Suspend

Mode
Off/On &
On/Off
Off
3W
DARK RED
POWER OFF
3W
RED
Power Supply
1
Power Consumption normal

operation
Stand-by Power Consumption
Power
Audio
AMP
Speaker
10Wrms + 10Wrms ( 10%)
Volume: Adjust
Max
12Wrms + 12Wrms
Volume: Max
Response Frequency
100Hz ~ 10KHz
T.H.D
10%
Input
0.700Vrms
S/N
40dB
Type
External
Impedance
System
Typical
System
PAL/SECAM
Tuning
Frequency Synthesizer System
TV
Channel
1) VHF LOW: 46.25~127.25MHz

HIGH: 133.25~361.25
2) UHF 367.25~863.75MHz
Video Level
0.70.15
V p-p
Sync Level
0.2860.075
V p-p
Color Burst
0.2140.072
V p-p
0.70.1
V rms
75
Termination
75
Termination
75
Termination
PC Input
0.50.05
V rms
NTSC
0.40.05
V rms
PAL
43
dB
AV
Audio Level
Video Cross-Talk
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14

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3.3 Supported Resolutions

PC Mode
Frequency
CLOCK
M
Item
Pol
[kHz]/[Hz]
[MHz]
1
H(Pixels)
V(Lines)
+
-
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
25.175
28.321
25.175
31.5
36.0
V(Lines)
40.0
H(Pixels)
49.5
V(Lines)
H(Pixels)
V(Lines)
56.25
H(Pixels)
9
+/V(Lines)
10
11
12
13
14
15
16
H(Pixels)
+/-
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
H(Pixels)
V(Lines)
57.283
65.0
78.75
94.5
74.5
84.75
108.0
135.00
Display
(A)
Front
Porch(B)
Sync.
(D)
Back
Porch(F)
31.469
HTotal
(E)
800
640
16
96
48
70.8
449
350
37
60
31.468
900
720
18
108
54
70.8
449
400
12
35
31.469
800
640
16
96
48
59.94
525
480
10
33
37.5
840
640
16
64
120
75
500
480
16
43.269
832
640
56
56
80
85.0
509
480
25
37.879
1056
800
40
128
88
60.317
628
600
23
46.875
1056
800
16
80
160
75.0
625
600
21
53.674
1048
800
32
64
152
85.061
631
600
27
49.725
1152
832
32
64
224
74.55
667
624
39
48.363
1344
1024
24
136
160
60.0
806
768
29
60.123
1312
1024
16
96
176
75.029
800
768
28
68.68
1376
1024
48
96
208
85.00
808
768
36
44.772
1664
1280
64
128
192
59.855
748
720
20
47.72
1776
1360
72
136
208
59.799
798
768
22
63.981
1688
1280
48
112
248
60.02
1066
1024
38
79.98
1688
1280
16
144
248
75.02
1066
1024
38
Res.
640
x
350
720
X
400
640
x
480
640
x
480
640
x
480
800
x
600
800
x
600
800
x
600
832
x
624
1024
x
768
1024
x
768
1024
x
768
1280
x
720
1360
x
768
1280
x
1024
1280
x
1024
DTV Mode (Component Video Input: Y/Pb/Pr)

- 50Hz: 576i, 576p, 720p, 1080i
- 60Hz: 480i, 480p, 720p, 1080i
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15

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16
17
YpPbPr INPUT
HDMi INPUT
PC/DVI AUDIO
PC INPUT
AV OUT
S-VIDEO
S-VIDEO AUDIO
SCARTS
PIP TUNER
MAIN TUNER
AUDIO
DECODER
YPbPR AUDIO INPUT
DVI-D (Single Link) INPUT
HDMi AUDIO INPUT
PC AUDIO INPUT
VGA INPUT
AV CVBS OUT
AV AUDIO OUT
S-VIDEO Y/C IN
S-VIDEO AUDIO IN
SCART RGB/FB
SCART AUDIO INPUT
SCART AUDIO OUT
WM8725
PLL TUNER
SCART CVBS INPUT
PLL TUNER
SIDE AV CVBS INPUT
FRONT AV HEADPHONE
SIDE AV AUDIO INPUT
AUDIO S/W
74HC4052
PIP CVBS
IF1
VCTi
HP AMP
TPA6110
.VIDEO
DECODER
TW9906
ITU656
ITU656
SRAM
(4M)
. MICOM
. VIDEO DECODER.
. AUDIO DECODER
. TXT DECODER
. IF DEM
FLASH
(512K)
MAIN SPEAKER L/R
MULTIBUTTON
AUDIO
AMP
TPA3004
LED/INFRA
.OSD
DEINTERLACE.
PIP
MST6***
SCALER
IP PORT
EXT CTRL.
MTV512
SUB MICOM
AM0005 BLOCK DIAGRAM
DDR RAM
LCD

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7805
7808
+12V
+12V
18
AC INPUT
POWER BOARD
+5V_OFF
+33V
+3.3V_SCALER
+3.3V_VID
+2.5V_SCALER
+2.5V_VID
+1.8V_SCALER
+1.8V_VCTi
+8V
+5V_TUNER
+12V
RC1117_3.
+5V_OFF
4069
RC1117_2.
+5V_OFF
+8V
RC1117_1.
+5V_OFF
+5VS
RC1117_3.
+5VS
+3.3V_MICOM
POWER BLOCK DIAGRAM
+5VS
+33V
4066
SWITCH
+5VS
24LC32
EEPROM
+3.3V_VID
24LC32
EEPROM
+3.3V_VID
24LC02
DDC IC
+5V
TUNER
0A2
TPA611
AMP
H.P
+5V_OFF
TPA3004
AUDIO AMP
+12V
4052
SWITCH
+8V
EN29LV040
FLASH
+3.3V_VID
K6R4008V1
DRAM
+3.3V_VID
DDR RAM
+2.5V_SCALER
WM872
AUDIO
I2S
+5V_TUNER
MTV512
MCU
SUB
+5VS
+8V
+1.8V_VCTi
+5V_TUNER
+2.5V_VID
TW9906
PIP VIDEO DECODER
+3.3V_VID
MST6181LDA
+1.8V_SCALER
+2.5V_SCALER
SCALER
+3.3V_SCALER
VCTi
/TXT PROCESSOR
MICOM
VIDEO/AUDIO/MAIN
+3.3V_VID

__________________________________________________________________________________________________________________
__________________________________________________________________________

__________________________________________________________________________________________________________________
5
5
7:
079
I2C BLOCK DIAGRAM
5
5
5
5
781(5
6&/B9
((3520
6'$B9
5
96&/
96'$
5
781(5
0&8
5
5
__________________________________________________________________________
19

__________________________________________________________________________________________________________________
1) J916: For IR, LED - Wafer

Pin No.
Symbol
Description
I/O
LED-WARNING
LED-RED
LED drive for RED Color
GND
Ground
IR-RCVR
IR Receive Signal
5V
5V Power for IR Receiver
Remarks
2) J917: For Local Key - Wafer

Pin No.
Symbol
Description
I/O
KEY-AD1
Local Key Value Detection
GND
Ground
Remarks
3) J909: For Debugging - Wafer

Pin No.
Symbol
Description
I/O
VCT_RXD
Receiver Line
VCT_TXD
Transmitter Line
GND
Ground
3.3V_VID
3.3V Power for Debugging Tool
Remarks
4) J912: For Debugging - Wafer

Pin No.
Symbol
Description
I/O
Remarks
VCT_SDA
Data Line
DPMS AMBER
VCT_SCL
Clock Line
GND
Ground
5) J915: For HDCP Writing - Wafer

Pin No.
Symbol
Description
I/O
GND
Ground
EEPROM_SCL
Clock Line
EEPROM_SDA
Data Line
Remarks
DPMS AMBER
__________________________________________________________________________
20

__________________________________________________________________________________________________________________
6) J924: For DVD interface, Wafer

Pin No.
Symbol
Description
I/O
DVD_AR
Right Sound Signal of DVD/DVB
GND
Ground
DVD_AL
4,5
NC
No Connection
GND
Ground
NC
No Connection
GND
Ground
DVD_Y
Luma signal of DVD/DVB
10
GND
Ground
11
DVD_C
Chroma signal of DVD/DVB
12
GND
Ground
Left Sound signal of DVD/DVB
Remarks
7) J925: For DVD/DVB Power Supply, Wafer

Pin No.
Symbol
Description
5V-DVD
5V Power for DVD/DVB
2,3
GND
Ground
12V-DVD
12V Power for DVD
I/O
Remarks
8) J926: For DVB Upgrade Interface, Wafer

Pin No.
Symbol
Description
I/O
GND
Ground
TXD_DVB
Transmitter Line
RXD_DVB
Receiver Line
GND
Ground
Remarks
9) J927: For IR, Interface (DVB), Wafer

Pin No.
Symbol
Description
I/O
TV_MENU
TV OSD MENU Detect Signal
DVB OSD MENU Detect Signal
DVB_MENU
GPIO
No Connection
DVB_ON
DVB PWR ON Status
GND
Ground
IR_RCVR
IR Receive Signal
Remarks
__________________________________________________________________________
21

__________________________________________________________________________________________________________________
10) J919: For Headphone Drive, Wafer

Pin No.
Symbol
Description
I/O
HP-R
Right Sound signal for Headphone
GND
Ground
HP-L
Left Sound signal for Headphone
HP-SENSE
Remarks
11) J920: For LCD Speaker Output, Wafer

Pin No.
1
Symbol
LOUT+
LOUT-
ROUT-
ROUT+
Speaker
Signal
Speaker
Signal
Speaker
Signal
Speaker
Signal
Description
Left Positive Class-D Output
I/O
Remarks
O
Left Negative Class-D Output
O
Right Negative Class-D Output
O
Right Positive Class-D Output
O
12) J922: For PDP Speaker Output, Wafer

Pin No.
Symbol
LOUT+
LOUT-
GND
ROUT-
ROUT+
Description
Speaker Left Positive Class-D Output
Signal
Speaker Left Negative Class-D Output
Signal
Ground
Speaker Right Negative Class-D Output
Signal
Speaker Right Positive Class-D Output
Signal
I/O
Remarks
O
O
O
O
13) J502: For LCD Side AV, Wafer

Pin No.
Symbol
Description
I/O
VCR_ARIN_R
Side Right Sound Signal
GND
Ground
VCR_ALIN_L
Side Left Sound signal
GND
Ground
VCR_IN
Side CVBS Signal Input
HP-R
Right Sound signal for Headphone
GND
Ground
HP-L
Left Sound signal for Headphone
Remarks
__________________________________________________________________________
22

__________________________________________________________________________________________________________________
14) J923: For PDP Side AV, Wafer

Pin No.
Symbol
Description
NC
No Connection
GND
Ground
VCR_ALIN_L
Side Left Sound signal
GND
Ground
VCR_ARIN_R
Side Right Sound Signal
GND
Ground
NC
No Connection
GND
Ground
VCR_IN
Side CVBS Signal Input
10
GND
Ground
I/O
Remarks
15) J701: For Logic Power Supply LCD, Wafer

Pin No.
Symbol
Description
I/O
Remarks
P_CTRL1
SMPS Power On Control Signal
3.3V(High) :On
2,3
GND
Ground
5V_OFF_CD
5V Logic Power Supply
5V_DVD_CD
5V DVD Power Supply
5VS
5V Standby Power Supply
7,8
GND
Ground
12V_CD
12V Power Supply
Max 3.0A
10
12V_DVD_CD
12V DVD Power Supply
Max 1.0A
11
INV_DIM
Inverter Dimming Control Signal
Max 1.0A
12
INV_CTRL
Inverter ON/OFF Control Signal
16) J702: For Logic Power Supply SDI PDP, Wafer

Pin No.
Symbol
Description
I/O
Remarks
1,3,4
GND
Ground
NC
No Connection
12V_DVD_SS
Max 1.0A
12V_AMP_SS
12V Audio Amp. Power Supply
GND
Ground
12V_SS
12V Power Supply
GND
Ground
10
5V_DVD_SS
5V DVD Power Supply
Max 3.0A
__________________________________________________________________________
23

__________________________________________________________________________________________________________________
17) J921: For Logic Power Supply SDI PDP, Wafer

Pin No.
Symbol
Description
THD_SS
VS On Control Signal
5VS
GND
Ground
P_CRTL_SS
NC
No Connection
6,7
GND
Ground
8,9
3.3V_OFF_SS
3.3V Logic Power Supply
10
GND
Ground
11
5V_OFF_SS
I/O
Remarks
3.3V(High) :On
18) J704: For Logic Power Supply LG PDP, Wafer

Pin No.
Symbol
Description
I/O
1,2
NC
No Connection
3,4
GND
Ground
12V_LG
12V Power Supply
12V_DVD_LG
7,8,9
GND
Ground
10,11
5V_OFF_LG
12
5V_DVD_LG
5V DVD Power Supply
Remarks

Pin No.
Symbol
Description
1,2
GND
Ground
3,4
24V_LG
24V Power Supply
I/O
Remarks

Pin No.
Symbol
Description
I/O
NC
No Connection
5V_D
5V Detection
SW_PANEL_P
VS On Control Signal
GND
Ground
5VS
P_CRTL
ACD
AC Detection
Remarks
3.3V(High) :On
__________________________________________________________________________
24

__________________________________________________________________________________________________________________
21) J913: For LCD VDD Selection LCD, Wafer

Pin No.
Symbol
Description
I/O
12V_CD
12V Power Supply
LCD_VDD
5V_OFF
Selected LCD_VDD Power Supply

5V Power Supply
Remarks
O
I
22) J102: LVDS Interface for LCD - PDP - DLP, Wafer

Pin No
Symbol
PDP_DLP_SCL
RA-
LVDS A Channel Negative Signal
GND
Ground
RA+
LVDS A Channel Positive Signal
5,6
GND
Ground
PDP_DLP_SDA
PDP_DLP Data Line
PDP_DLP_SCL
PDP_DLP Clock Line
RB-
LVDS B Channel Negative Signal
GND
Ground
10
RB+
LVDS B Channel Positive Signal
11
LVDS_OPTION
12,13
GND
Ground
14
RC-
LVDS C Channel Negative Signal
15
GND
Ground
16
RC+
LVDS C Channel Positive Signal
17,18,19
GND
Ground
20
RCLK-
21
LVDS_MAP_SEL
22
RCLK+
23
LCD_VDD
24
GND
25
LCD_VDD
26
RD-
27
LCD_VDD
28
RD+
29
LCD_VDD
30
GND
Function
Remark
PDP_DLP Clock Line

350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
LVDS Option selection
LVDS Clock Channel Negative Signal
350mVpp
5%
350mVpp
5%
350mVpp
5%
LVDS Map Selection

LVDS Clock Channel Positive Signal
350mVpp
5%
LCD Power or Ground

Ground
LCD Power or Ground
LVDS D Channel Negative Signal
350mVpp
5%
LCD Power or Ground

LVDS D Channel Positive Signal
350mVpp
5%
LCD Power or Ground

Ground
__________________________________________________________________________
25

__________________________________________________________________________________________________________________
23) J21: LVDS Interface for LCD-PDP-DLP, Wafer

Pin No
Symbol
1,2
GND
PDP_DLP_SCL
PDP_DLP Clock Line
PDP_DLP_SDA
PDP_DLP Data Line
GND
Ground
RD+
LVDS D Channel Positive Signal
RD-
LVDS D Channel Negative Signal
GND
Ground
RCLK+
LVDS Clock Channel Positive Signal
10
RCLK-
LVDS Clock Channel Negative Signal
11
GND
Ground
12
RC+
LVDS C Channel Positive Signal
13
RC-
LVDS C Channel Negative Signal
14
GND
Ground
15
RB+
LVDS B Channel Positive Signal
16
RB-
LVDS B Channel Negative Signal
17
GND
Ground
18
RA+
LVDS A Channel Positive Signal
19
RA-
LVDS A Channel Negative Signal
20
GND
Ground
21
INV_CTRL
22
LVDS_MAP_SEL
Function
Remark
Ground
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
350mVpp
5%
Inverter Brightness Control

LVDS Map Selection
23, 24
25, 26
GND
Ground
27,28
29, 30
VDD
LCD Power
__________________________________________________________________________
26

__________________________________________________________________________________________________________________
24) J905: Full SCART
Pin No.
Symbol
Description
I/O
SCART_ROUT
SCART Audio Right Output
SCART_ARIN_R1
SCART Audio Right Signal Input
SCART_LOUT
SCART Audio Left Output
4,5
GND
Ground
SCART_ALIN_L1
SCART Audio Left Signal Input
SCART_VBIN1
SCART Blue Video Signal Input
SCART_AVSW1
ID detection Signal
GND
Ground
10
NC
No Connection
11
SCART_VGIN1
SCART Green Video Signal Input
12
NC
No Connection
13
GND
Ground
14
NC
No Connection
15
SCART_VRIN1
SCART Red Video Signal Input
16
SCART_FBLNK1
SCART R/G/B Video FB Signal Input
Remarks
I
I
17,18
GND
Ground
19
SCART_VOUT1
TV Video Signal Output
20
SCART_VIN1
SCART CVBS Signal Input
__________________________________________________________________________
27

__________________________________________________________________________________________________________________
25) J907: Half SCART
Pin No.
1
Symbol
Description
I/O
SCART_ROUT2
Selected Audio Right Output
SCART_ARIN_R2
SCART Audio Right Signal Input
SCART_LOUT2
Selected Audio Left Output
GND
Ground
SCART_ALIN_L2
SCART Audio Left Signal Input
NC
No Connection
SCART2_AVSW2
ID detection Signal
GND
Ground
TXD_DVB
DVB Upgrade Line
NC
No Connection
RXD_DVB
DVB Upgrade Line
GND
Ground
SCART_CIN2
SCART Chroma Signal Input
NC
No Connection
GND
Ground
SCART_VOUT2
Selected Video Signal Output
Remarks
2
3
4,5
6
7
8
9
10
11
12
13, 14
15
16
17,18
19
20
SCART_VIN2
SCART CVBS or Luma Signal Input
__________________________________________________________________________
28

__________________________________________________________________________________________________________________
Rear Connection
Side AV Connection
Audio / Video In
Video CVBS (1 Vpp / 75 )
Audio L
Audio R
Headphone 3.5 mm
__________________________________________________________________________
29

__________________________________________________________________________________________________________________
5. MENU STRUCTURE
MAIN Menu
PICTURE
SOUND
PIP/PAP
FEATURES
INSTALLATION
PICTURE Menu
COLOR TEMP
PICTURE PRESET
Brightness
Contrast
Colour
Sharpness
TINT
SOUND Menu
Volume
SOUND PRESET
SURROUND
AVL
BALANCE
BASS
TREBLE
100 Steps
FLAT, MUSIC, MOVIE, SPEECH, USER
ON / OFF
ON / OFF
L50,R50
100Steps
100Steps
PIP/PAP Menu
ON/OFF
SOURCE
PIP SIZE
PIP POSITION
OFF/PIP/PAP1/PAP2
ALL SOURCE
SMALL/LARGE
FEATURES Menu
Language
(English /GERMAN /FRENCH/ITALIAN/

SPANISH/DUTCH/GREEK/DANISH/
SWEDISH/FINNISH/TURKISH/RUSSIAN
CZECH/HUNGARIAN/PORTUGISH/
NORWEGIAN/HIRVATSKI/SLOVENCE/
BULGARSKI/ARNAVUT/SLOVAKCA/
POLSKI/SIRPSKI/MAKEDONSKI/ARABIC)
TRANSPARENCY
RESET
TIMER
CLOCK
OFF TIME
ON TIME
PR
VOL
AUTO SHUT OFF
INSTALLATION
AUTO TUNNING
COUNTRY SELECTION
MANUAL TUNING
SYSTEM
NAME
SEARCH
FINE TUNE
PROGRAM LOCK
NORMAL, COOL, WARM

DYNAMIC, STANDARD, SOFT, USER
100 Steps
100Steps
100Steps
100Steps
-50, +50
100 Steps
HH:MM
HH:MM ON/OFF
HH:MM ON/OFF
NUMBER
100Steps
ON/OFF
(BELGIUM/FRANCE/GERMANY/ITALY/ NETHERLAND/
SPAIN/SWEDEN/SWITZERLAND/UK/TURKEY
POLAND/OTHER)
PROGRAMME NUMBER
EURO/FRANCE
ON/OFF
__________________________________________________________________________
30

__________________________________________________________________________________________________________________
Service Menu
(Will be displayed by pressing the digits 1923 while the top level Main menu is active)
Service Main
VCTI
MSTAR
ADJUST
AUTO COLOR
OPTION
RESET
DEFAULT
ISP
SOFTWARE INFORMATION
SOFTWARE DATE
MAIN VERSION
SUB VERSION
DISPLAY DEVICE INFORMATION
THE DATE OF MAKING THE SOFTWARE

THE MAIN MCU SOFTWARE REVISION NUMBER
THE SUB MCU SOFTWARE REVISION NUMBER
LCD AUO 32
VCTI ,MSTAR
(THIS ITEM MUST NOT CHANGED WHEN SERVICE, ONLY FOR ENGINEERING TEST)
ADJUST
(THIS ITEM IS USED WHEN NEED TO ADJUST THE WHITHE BALANCE)
__________________________________________________________________________
31

__________________________________________________________________________________________________________________
WE CAN ADJUST THE WHITE BALANCE BY CHANGING THE GAIN/OFFSET. IF ADJUSTING THE HIGH
BRIGHTNESS PART, PLEASE CHANGE THE GAIN. IF ADJUSTING THE LOW BRIGHTNESS ,PLEASE
CHANGE THE OFFSET.BUT THIS ADJUSTING IS NOT EFFECT IN OTHER SOURCE.
AUTO COLOR
THIS IS USED ONLY IN PC ANALOG OR COMPONENT SOURCE. WHEN ADJUSTING THE AUTO COLOR,
WE MUST USED THE SPECIAL COLOR PATTERN.
__________________________________________________________________________
32

__________________________________________________________________________________________________________________
OPTION
= HOTEL MODE
ON/OFF
TXT AREA
DONT TOUCH
TXT TOP
DONT TOUCH
LVDS
TI/NORMAL
* WHEN WE HAVE WRONG COLOR, PLEASE CHANGE THIS OPTION
TUNER
1/2
* ACCORDING TO 1 TUNER OR 2TUNER MODEL.
PIP ON
OFF/PC/AC
* DEPENDING ON THE TV MODEL
SIDE AV
ON/OFF
* DEPANDING ON THE TV MODEL
EXTERNAL
NO/DVB/WIRELESS/DVD
* DEPENDING ON THE TV MODEL
CUSTUM
TELRA/GRUNGDIG/PHILIPS
* DEPANDING ON THE TV MODEL
LCD
SELECT THE DISPLAY DEVICE
RESET
WHEN WE FINISH THE SERVICE, PUSH THE RESET THIS FUNCTION INITIALISE THE EEPROM
DEFAULT
DONT TOUCH THIS ITEM.
ISP
OFF/ISP
WHEN WE UDATE THE SOFTWARE, PLEASE THIS ITEM
WE NEED THE SPECIAL JIG AND SOFTWARE WHEN UPDATING S/W.
__________________________________________________________________________
33
C901
0.1uF
HDMI_CONN_V
1
2
3
4
U902
VCC
WP
SCL
SDA
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
24LC16
A0
A1
A2
VSS
2
2
DVI_RX1+
DVI_RX2-
DVI_RX2+
R947
75
R327
75
ROUT_M
LOUT_M
J502
2
R563
LCD ONLY
8
7
6
5
4
3
2
1
ZD501
ZD502
R555
MTZJ5.6B
MTZJ5.6B
ZD503
ZD504
R999
75
7
5
5
ZD952
MTZJ5.6B
D907
*
R997
75
2
2
2
2
R940 2
R941 2
R992
R988
R990
R993
R998
75
R991 2
R987 2
R989 2
1 0
1 0
R557 2
HP-R
HP-L
HP-SENSE
ZD930 ZD931
D902
*
2 *
2 *
1
1
1
100
100
100
470
VCR_ARIN_R
VCR_ARIN_L
75
R325
R10302,R10312
R10322 DELETE
SIDE A/V IS
1 15K
1 15K
1
1
1
1
7
7
7
7
7
7
2
2
2
2
2
2
2
2
100
5
5
3
VCR_IN
RX0RX0+
RX1RX1+
RX2RX2+
RXCRXC+
DTV_AIN_R
DTV_AIN_L
COM_PR
COM_PB
COM_Y
COM_SYNC
1 15K
J920
P4
P3
P2
P1
COND4P
4
3
2
1
4
4
5
5
5
5
VCR_ARIN_L
ROUT+
ROUTLOUTLOUT+
VCR_IN
ZD966
ZD964
ZD965
23
22
1 *
1 *
R1031 2
R1032 2
SP LSP L+
SP R+
SP R-
J922
P5
P4
P3
P2
P1
COND5P
5
4
3
2
1
LOUTLOUT+
ROUT+
ROUT-
PDP ONLY
ZD968
MTZJ5.6B
1 *
R1030 2
R344
150
R1010
75
HP L
GND
HP R
J919
P4
P3
P2
P1
COND4P
R1014
4
3
2
1
150
Q908
KSC1623
Q909
A1504
ZD924
1 10K
SCART_ROUT2 3
SCART_LOUT2 3
ZD916
ZD915
ZD914
C966
1uF
R1013
10K
SCART_VOUT2
3
C967 100UF/16V
R1011
18K
HP-SENSE 3
HP-L
HP-R
ZD934
ZD939
ZD937
ZD941
ZD940
ZD936
SCART_VBIN1 3
SCART_VGIN1 3
ZD938
ZD913
ZD923
ZD922
+5V_1TUNER
R1012
140
R1015
470
R1019 R1018
56K
56K
ZD919
R939 2
ZD918
SCART_FBLNK1 3
SCART_VRIN1 3
SCART_VIN1
ZD935
Monitor
Output OPTION
C969
22UF/16V
1
1 330 2
ZD920
R323
75
ZD945
ZD921
TXD_DVB
RXD_DVB
R329
75
75
1 10K
1 0
ZD946
ZD944
ZD932
R322
R1017 2
R458
75
1 *
75
R321
ZD943
C968
22UF/16V
1
ZD942
R975 2
R319 2
1 330 2
R938 2
R324
150
1 *
R326
75
R1016 2
SCART JACK
J907
R976 2
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
SCART JACK
J905
VCT_TXD
3
VCT_RXD 3
23
22
ZD967
SVHS-RIN
SVHS-LIN
C789
0.1uF
1K
R486
KEY_AD1
1K
R485
3 VOUT_M
4 ROUT_M
VCR_ARIN_R
7
7
4
3
2
1
4 LOUT_M
1 15K
DDC_SCLB
DDC_SDAB
DDC5V-DVI
CHK_DVI 6
DVI_RXCDVI_RXC+
5
5
5
5
5
5
5
5
J917
P1
P2
R943 2
LCD ONLY
SP R+
SP RSP LSP L+
KEY
GND
RX0RX0+
RX1RX1+
RX2RX2+
RXCRXC+
J909
P4
P3
P2
P1
3,6,7,8
3,6,7,8
+3.3V_VID
5
5
5
R453
COND4P
COND2P
+5VS
VCT_SCL
VCT_SDA
R_GND_S 5
G_GND_S 5
B_GND_S 5
RED_IN
GREEN_IN
BLUE_IN
R945 2
COM_PR_GND 5
COM_PB_GND 5
COM_Y_GND 5
ZD959 ZD956
1)SIDE A/V OPTION

BOX DELETE
2)R10302,R10312 15KOHM
3)R10322 0OHM
LEDRED 6
LEDWARNING
DDC_SCLB
DDC_SDAB
DDC5V-DVI
10
10
10
10
10
10
10
10
L103
*
2 100nF
2 100nF
2 100nF
2 100nF
2 100nF
2 100nF
IRRCVR
ZD958 ZD957
1 47nF
1 47nF
1 47nF
2 100
BOARD A/V INPUT
1 100 C953 2
1 100 C948 2
1 100 C950 2
1
1
1
1
1
1
1
1
DVI_RX0DVI_RX0+
DVI_RX1DVI_RX1+
DVI_RX2DVI_RX2+
R110
R109
R108
R107
R106
R105
R112
R111
D905
*
15PF
0.1uF
10
10
1 470U/16V
R918
R1000
R1001
PC_VSYNC_IN
PC_HSYNC_IN
COND3P
1
2
3
C9471
C9181
C9161
2 100
2 100
2 100
J912
C9191
C9171
C9151
2 100
2 100
2 100
CHK_DSUB
RCAJACK2P_R14222S
RED
1K
5
4
3
2
1
D901
*
J910
WHITE
ZD947
R901 1
D906
*
C955
C788 2
C734 2
J916
P5
P4
P3
P2
P1
COND5P
D912
BAV99
R986
R928
R926
R1022
LED_RED
+3.3V
IR
GND
C903
100P
R904 1
R903 1
D911
BAV99
+3.3V_SCALER
R556 2
HP-R
HP-L
1K
1
D910
BAV99
ZD902 ZD949 ZD948
ZD969 ZD928 ZD929
MTZJ5.6B ZD505
R565
2
ZD953
+5V_OFF
ZD951
E_DDC_CTL
DVI_DDC_CLK
DVI_DDC_DAT
D903
*
Q901
KSC1623
R905
1K
C902
22PF
2 1K
2 1K
MTZJ5.6B
P8
P7
P6
P5
P4
P3
P2
P1
2 100
2 100
C906
1uF
MTZJ5.6B
HP L
GND
HP R
V IN
GND
A-L
GND
A-R
COND8P
R554 *
1
CHK_SVIDEO 6
SVHS_CIN
3,8
SVHS_YIN
3,8
COMP-RIN
COMP-LIN
COMP-PR
COMP-PB
COMP-Y
DVI_CHK
DVI_RXCDVI_RXC+
DVI_RX0DVI_RX0+
DVI_RX1DVI_RX1+
DVI_RX2DVI_RX2+
D908
*
R910
10K
D904
*
HOT_PLUG
R906 1K
1
2
ZD905
COMP-PR-GND
COMP-PB-GND
COMP-Y-GND
DDC_SCLB R979 1
DDC_SDAB R980 1
VOUT_M
2 100
2 100
2 4.7K
2 4.7K
DDC5V-DVI
7
3
3
R907
2.7K
C905
1uF
R909 1
R908 1
ZD906
MTZJ5.6B
MTZJ5.6B
PDP ONLY
2.5mm for
future,delete
10
9
8
7
6
5
4
3
2
1
2
2
DVI_RX0+
DVI_RX1-
HDCP_CONTROL
2
2
DVI_RXC+
DVI_RX0-
DVI_RXC-
M_DDC_CTL 6
+5V_DDC
2 100
2 100
E_DDC_CTL
DDC_SCLA
DDC_SDAA
DDC5V_DSUB
2 10K
2 10K
MTZJ5.6B
ZD912
DDC5V_DSUB
R916 *
+3.3V_SCALER
R985 1
R927 1
R925 1
SCART_CIN2
SCART_VIN2
P1
P2
P3
P4
J925
COND4P
1
2
3
4
4
3
2
1
5
5
6
5
4
3
2
1
COMMUNICATION 2.0mm
P6
P5
P4
P3
P2
P1
R959
10K
3
4
5
2
1
SCART_ARIN_R2 4
R930
56K
DVB_ON
6
GPIO
6
DVB_MENU 6
TV_MENU
6
+5V_DVD
R1029 470
2
1
R966 15K
CONFIDENTIAL
R1024
140
R1028 0
2
R481
75
R482
75
IRR_MUTE
IRRCVR
DVD_AR5
DVD_AL 5
DVD_C 5
DVD_Y 5
Date
Thursday, April 27, 2006
Sheet
of
2
8
Size Rev
Document Number
<Doc>
Custom A4
D18
1N4148
Q911
KSC1623
C974 1nF
2
1
R967 15K
2
1
R969
4.7K
4
4
02. DVI/DSUB/SCART/RS232C
AM0005
INS60256487
PC-AIN-R
PC-AIN-L
2
1
Note
Designer
AddressDaeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
Title
R1023
470
Q910
KSC1623
100
R1026
R1027 *
2
12
11
10
9
8
7
6
5
4
3
2
1
+5VS
COND12P
1 15K
1 15K
SCART_ROUT2 3
SCART_LOUT2 3
SCART_VOUT2 3
SCART_ROUT1 3
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
J924
12P FCC CABLE
DVD/DVB
GND
C
GND
Y
GND
CVBS
GND
SPDIF
TV_MUTE
A-L
GND
A-R
R1025 150
ZD904
ZD907
ZD911
C929
22UF/16V
C924
22UF/16V
1
R911 2
R913 2
R949
56K
ZD910
+12V_DVD
C735
220uF/16V
C941
1uF
C934 100UF/16V
R960
18K
SCART_ALIN_L2 4
near the connector
COND6P
J927
R965
56K
C937
22UF/16V
R964
56K
SCART_ARIN_R1 4
2
SCART_LOUT1 3
SCART_AVSW1 6
SCART_VOUT1 3
SCART_ALIN_L1 4 C936
22UF/16V
2
1
R957
10K
SCART_AVSW2 6
R972
140
C935 100UF/16V
C940
1uF
+5V_1TUNER
R961
470
PHONEJACK STEREO
R915 2
1 *
J902
C972 C973
*
*
DVD_OPTION,IDTV
option
H:TV L:DVB
GPIO
H:MENU L:CLOSE FOR DVB
H:MENU L:CLOSE FOR TV
C971
*
Q904
KSC1623
R973 150
C727
220uF/16V
R968 *
2
C736
220uF/16V
RXD_DVB
TXD_DVB
DVB UPGADE 2.5mm
P4
P3
P2
P1
COND4P
J926
1 330
1 15K
1 330
Q906
A1504
1 15K
R970
140
R962 2
R955 2
R963 2
C970
*
18K
R958
+5V_1TUNER
R956
470
R954 2
1 330
1 15K
1 330
2
Q903
KSC1623
R971 150
1 15K
1 75
ZD917
DVD/DVB POWER 2.5mm
C931 C930 C925 C923

1.5nF *
1.5nF *
R950 2
R935 2
R934 2
R929
3.3K
1 75
Q905
A1504
C943
C942
*
*
C945
C944
1.5nF
1.5nF
R942 2
R937 2
3,8
R974
3.3K
ZD933
R977 2
MTZJ5.6B
J923
COND10P
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
MTZJ5.6B
SIDE A/V OPTION
ZD926
COMP-RIN
COMP-LIN
COMP-PR
COMP-PB
SVHS_CIN
SVHS_YIN
COMP-Y
R981 1
R978 1
R983 1
R982 1
ZD927
8
7
6
5
KDS184
DVI_RX2+
DVI_RX1+
DVI_RX2-
DVI_RX0+
DVI_RX1-
DVI_RXC+
DVI_RX0-
0
DVI_RXC-
HOT_PLUG
DDC5V-DVI
DVI_CHK
DDC_SDAB
DDC_SCLB
4.7K R951
2
1
8
7
6 R9121
5 R9141
3
3
R984 1
R902 1
D909 KDS184
4.7K R936
2
1
MTZJ5.6B
ZD925
CHK_SVIDEO
SVHS_CIN
SVHS_YIN
RCAJACKX2
COMP-Y-GND
COMP-PB-GND
COMP-PR-GND
J11
DDC_SCLA
DDC_SDAA
VCC
WP
SCL
SDA
24LC02
A0
A1
A2
VSS
U901
+5VS
R469
1
2
3
4
D913
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2 0.1uF
HPDET
+5V
CEC/GND
SDA
SCL
NC
CEC
CLKCLKS
CLK+
DATA0DATA0S
DATA0+
DATA1DATA1S
DATA1+
DATA2DATA2S
DATA2+
+5VS
C946 1
P402
Q902
KSC1623
E_DDC_CTL
+5V_DDC
10
ZD909
15
11
MTZJ5.6BMTZJ5.6B MTZJ5.6BMTZJ5.6B
ZD908
15
SCL
ZD950
14
VSYNC
ZD903
13
MTZJ5.6B
12
11
REDGREENBLUE-
ID0
REDRED+
GREENGREEN+
BLUEBLUE+
16
17
SDA
6
1
7
2
8
3
9
4
10
5
GND-R
R
1
GND-G
G
GND_B
B
5V
ID2
GND
GND
R994 R995 R996

75
75
75
2 HB-1608-300
2 HB-1608-300
2 HB-1608-300
HSYNC
20
21
T1
T2
2
1
J903
MTZJ5.6B
MTZJ5.6B
1
2
2
1
2
1
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
1
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
1
2
1
L9031
L9021
L9011
2
1
2
1
L-DSUB
VGA_SLIM_DVIMTG
COMMON
2
1
2
2
1
1
MTZJ5.6B
2
1
2
1
2
1
1
2
1
2
1
RED+
GREEN+
BLUE+
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
*
MTZJ5.6B
2
1
1
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
1
MTZJ5.6B
2
1
MTZJ5.6B
2
1
2
1
2
2
1
1
+
2
1
2
1
2
1
1
2
1
2
1
2
1
2
MTZJ5.6B
+
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
2
1
2
1
2
1
2
1
2
1
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
+
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
MTZJ5.6B
+
MTZJ5.6B
+
MTZJ5.6B
+
MTZJ5.6B
+
6.CIRCUIT DIAGRAMS AND PCB LAYOUTS

Main Board
MTZJ5.6B
5
5
1
2
3
2
2
2,6
2,6
R3110
2 100nF
C912 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
+3.3V_VID
2 100nF
C914 1
* RA304
R343
4.7K
4.7K
100
100
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
VSUP5.0BE
R260
SUB_RFSW
R337
6.8K
R336
R338
6.8K
6.8K
+5VS
VCTI49xyi
BOUT
VRD
XREF
VSUP3.3BE
GND2
GND3
VSUP3.3IO
VSUP3.3DAC
GNDDAC
SAFETY
HFLB
HOUT
VPROT
ADB11
ADB9
ADB8
ADB13
ADB14
ADB17
PSWEQ
ADB18
ADB16
ADB15
STOPQ
ENEQ
ADB12
ADB7
ADB6
ADB5
ADB4
ADB19
RDQ
WRQ
OCF
ALE
RSTQ
NC4
NC5
NC6
A18
A17
A16
A15
OE
I/O8
I/O7
VSS1
VCC1
I/O6
I/O5
A14
A13
A12
A11
A10
NC7
NC8
NC9
K6R4008V1D
NC0
NC1
A0
A1
A2
A3
A4
CS
I/O1
I/O2
VCC0
VSS0
I/O3
I/O4
WE
A5
A6
A7
A8
A9
NC2
NC3
U304
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
D5
D4
A141
A132
A123
A114
A10
* RA303
D7
D6
8
7
6
5
R373
R372
A17
A16
VCT49XYI
R370 *
RDQ_JACK
1 R371 * 2 VCT_DB5
1
2 VCT_DB4
2 *
2 * VCT_ADB18
VCT_ADB17
VCT_ADB16
VCT_DB7
VCT_DB6
VCT_ADB14
VCT_ADB13
VCT_ADB12
VCT_ADB11
8
7
6
5
2 0.1uF
2 0.1uF
* RA306
1
1
1
2
3
4
C341 1
C340 1
TTX 256 PAGE 3-1
R472
R470
R471
R473
RDQ_JACK
WRQ_JACK
VCT_ADB12
VCT_ADB7
VCT_ADB6
VCT_ADB5
VCT_ADB4
VCT_ADB11
VCT_ADB9
VCT_ADB8
VCT_ADB13
VCT_ADB14
VCT_ADB17
VCT_PSWEQ
VCT_ADB18
VCT_ADB16
VCT_ADB15
1K
4.7uF/35V
C333
SUB_TUNER_CVBS 6
KEY_AD1_VCTI 6
P_CTRL5
IRRCVR_VCTI 6
+3.3V_MICOM
R261
2
2
EEPROM_SCL 6
EEPROM_SDA 6
R401 *
R388 *
R398 *
R402 *
5
5
5
5
Q205
6
9
C339 10uF/16V
R3111
KEY_AD2
KEY_AD1_VCTI
VCT_RXD
VCT_TXD
2,6,7,8 VCT_SDA
2,6,7,8 VCT_SCL
1 *
VSUP3.3IO
VSUP3.3DAC
VSUP3.3BE
5
3
12
10
1
1
13
2
14
EEPROM_SCL
EEPROM_SDA
R363
0.1uF
C334
100
100
R306
R307
74HC4066
IN 4 CNTL 4
OUT 4
IN 3 CNTL 3
OUT 3
IN 2 CNTL 2
OUT 2
4.7K
4.7K
EEPROM_SCL 3
EEPROM_SDA 3
VDD
IN 1 CNTL 1
OUT 1
VSS
R302
R301
11
AD0
AD1
AD2
AD3
RA301 *
VCT_ADB0 8
1A0
VCT_ADB1 7
2A1
VCT_ADB2 6
3A2
VCT_ADB3 5
4A3
VCT_ADB4 8
1A4
VCT_CS
7
2CS
+3.3V_VID
R368
VCT_DB0
6
3D0
VCT_DB1
47K
5
4D1
RA302
*
1
2
WRQ_JACK
R369 1
2
*
RA305
D2
*
VCT_DB2
1
8
VCT_DB3
2
7D3
VCT_ADB5 3
6A5
VCT_ADB6 4
5A6
VCT_ADB7 1
8A7
VCT_ADB8 2
7A8
VCT_ADB9 3
6A9
VCT_ADB10 4
5
RD_SCALER
WR_SCALER
8
7
6
5
VCT_CS R366 2
VCC
WP
SCL
SDA
24LC32B
A0
A1
A2
VSS
COND3P
J915
1
2
3
4
U302
+3.3V_VID
R393 *
R394 *
R395 *
R397 *
2 0.1uF
DVD_C
C312 1
RF_CVBS
KEY_AD1
VSUP3.3FE
IRRCVR
1nF
C327
1nF
C328
1
IFIF+
TAGC
0.1uF
C326
RESETQ
VSUS5.0FE
VSUP5.0FEI
VSUP3.3DIG
GND4
GND5
VSUP1.8DIG
XTAL1
XTAL2
P22
P23
PSENQ
ADB10
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
ADB0
ADB1
ADB2
ADB3
P24/656CLKIO
P25/656HIO
P26/656VIO
P30/656IO0
P31/656IO1
P32/656IO2
VSUP3.3EIO
GNDEIO
P33/656IO3
P34/656IO4
P35/656IO5
U301
1
1
1
1
2
2
2
2
R314
R313
R312
R311
R381
R316
R315
R305 2
R318 2
R317
R308
16
12
11
10
9
8
7
6
5
27
26
23
25
4
28
29
3
2
30
1
VCT-X1
VCT-X2
47
47
VCC
OE#
CS#
WE#
24
22
31
32
13
14
15
17
18
19
20
21
8
7
6
5
8
7
6
5
C913
*
VSUP5.0FE
AV_DTV_L 4
AV_DTV_R 4
HDMI_AIN_L 4
HDMI_AIN_R 4
0.1uF
C330
R342
1
2
3
4
1
2
3
4
R3116
VCT_PSENQ
VCT_PSWEQ
VCT_DB0
VCT_DB1
VCT_DB2
VCT_DB3
VCT_DB4
VCT_DB5
VCT_DB6
VCT_DB7
C338
0.1uF
R364
*
C323
22pF
ALE_SCALER 5
IRRCVR_VCTI 2,6
VCT656_CLK
EEPROM_SCL 6
EEPROM_SDA 6
VCT656[0..7]
1 *
0.1uF
C325
VSUP8.0VAU
1
1
2,6,7,8 DDC_SCLA
2,6,7,8 DDC_SDAA
1
1
DDC_SCLB
6 DDC_SDAB
15
14
13
12
0.1uF
C321
R379 *
R380 *
R378 0
IF-OUT
R374 0
near the VCTif and use GND line.

use inside layer.
100pF
C911
+3.3V_VID
VCT_CVBS
8
SCART_VOUT1 2
SCART_VOUT2 2
SVHS_CIN
2,8
SVHS_YIN
2,8
SCART_VIN1 2
VCR_IN
4
SCART_VIN2 2,8
DVD_C
2
DVD_Y
2
SCART_FBLNK1 2
SCART_VBIN1 2
SCART_VGIN1 2
SCART_VRIN1 2
RA104VCT6560
VCT6561
VCT6562
VCT6563
RA105VCT6564
VCT6565
VCT6566
VCT6567
C910
1nF
1 *
1 *
C315
1uF
C322
22pF
C331
1uF
X301
20.25MHz
+8V_SW_OFF
R304 2
R334 2
VCT_PSENQ
VCT_ADB10
VCT_DB7
VCT_DB6
VCT_DB5
VCT_DB4
VCT_DB3
VCT_DB2
VCT_DB1
VCT_DB0
VCT_ADB0
VCT_ADB1
VCT_ADB2
VCT_ADB3
L904 1
2 HB-1608-102
near the VCTif and use GND line.
use inside layer.
VCT-X2
VCT-X1
LOUD_OUT_L 4
LOUD_OUT_R 4
SCART_LOUT1 2
SCART_ROUT1 2
SCART_LOUT2 2
SCART_ROUT2 2
VCT_RESETQ 6
VSUP1.8DIG
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
100
100
100
100
100
100
100
C317
1uF
VSUP5.0IF
VSUP3.3DIG
1 100
1 100
100
100
EN29LV040
VSS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
1 *
1 *
C318
0.1uF
C329
0.1uF
VSUP3.3EIO
R339 2
R340 2
3.3uF/50V
C332
SUB_TUNER_CVBS
U303
VCT_ADB0
VCT_ADB1
VCT_ADB2
VCT_ADB3
VCT_ADB4
VCT_ADB5
VCT_ADB6
VCT_ADB7
VCT_ADB8
VCT_ADB9
VCT_ADB10
VCT_ADB11
VCT_ADB12
VCT_ADB13
VCT_ADB14
VCT_ADB15
VCT_ADB16
VCT_ADB17
VCT_ADB18
100nF
100nF
100nF
100nF
2 100nF
2 100nF
2 100nF
C343 1
C308 1
C307 1
C306
C305
C304
C303
2 100nF
2 100nF
2 100nF
C311 1
C310 1
C309 1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
1
2
1
2
AGC
NO_PIN1
SAS
SCL
SDA
NO_PIN2
B+
NO_PIN3
BT
IF2
IF1
11
VDD
IN 4 CNTL 4
OUT 4
IN 3 CNTL 3
OUT 3
IN 2 CNTL 2
OUT 2
74HC4066
150
R606
12
10
6
9
5
3
13
2
14
2 C342
0.1uF
IN 1 CNTL 1
OUT 1
VSS
U305
510
R609
C608 0.01uF
1
2
1.3K
R608 R607
R601
*
0.1uF
1
1
27
C606
0.01uF
C607 1
R375 *
2
2
1
R623
C603 +
IN2
IN1
M_DDC_CTL
1 *
1 *
1 *
IF-
2,6,7,8
2,6,7,8
C313
1uF
Date
Sheet
3
8
of
Size Rev
Document Number
A4
<Doc>
Custom
VCTi down_load
HDCP Writing
ISP desable
FUNCTION
IF+
C610
0.01uF
R604
*
R603
8.2K
+5V_1TUNER
VCT_SCL
VCT_SDA
0.1uF
C301
+5V_1TUNER
0.1uF
C336
VSUP3.3FE
ISP_CTL2
OUT2
OUT1
CONFIDENTIAL
2 100
2 100
R602
100K
X6966M
ISP_CTL1
0.1uF
COIL-3.3UH L601
2
1
C623
20pF
C316
1uF
VSUP3.3IO
0.1uF
C320
C364
VSUP3.3EIO
0.1uF
C335
VSUP3.3DIG
03. Vcti49X7R&TUNER
AM0005
R622 1
R621 1
U603
+5V_1TUNER
C624
20pF
C604 +
*
INS60256487
2
2
R610
0
2 0.01uF
+33V_T
HH-2012-121
470U/16V
R351
+3.3V_VID
R361 2
R3115
R309 2
1 *
VSUP3.3BE
Note
Designer
AddressDaeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
Title
ISP_CTL1
VCT_SDA
VCT_SCL
ISP_CTL2
+3.3V_MICOM
R377 *
1
R376
4.7
R605
Q601
KSC1623
L709
R335
R360 2
+3.3V_VID
L602
C605
HH-2012-121
100UF/16V 2
1
C601
0.01uF
C602
10UF/50V
0.1uF
IF-OUT
C609
0.01uF
L603
560nH
1
2
3
4
5
6
7
8
9
10
11
1Tuner:TECH2949PS40B(D)
2Tuner/DVB:TECH2949PS40A(D)
U639
0.1uF
C319
1 *
R332 2
C324
1 *
R333 2
C314
1 *
R341 2
0.1uF
C337
VSUP5.0BE VSUP5.0IF VSUP5.0FE
1 *
VSUP3.3DAC
+5V_1TUNER
R365 2
+3.3V_VID
TECH2949PG40B
MAIN TUNER
TAGC
CHASSIS2
CHASSIS3
CHASSIS4
CHASSIS1
0.1uF
C302
VSUP1.8DIG VSUP1.8FE
1
2
1
R385
VSUP5.0BE
1
2
145
VSUP8.0VAU
P145
1
2
1
2
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
GOUT
ROUT
SVMOUT
BIN
GIN
RIN
FBIN
GNDM
SENSE
RSW1
RSW2
EW
VERTVERT+
TEST
VSUP5.0BE
GND6
GND7
VSUP8.0AU
VREFAU
SPEAKERL
SPEAKERR
AOUT1L
AOUT1R
AOUT2L
AOUT2R
AIN3L
AIN3R
AIN2L
AIN2R
AIN1L
AIN1R/SIF
TAGC
VREFIF
IFINIFIN+
1
2
1
2
1
2
2 C346
0.1uF
1
2
1
2
1
2
1
2
1
2
1
2
1
2
U306
1
2
1
2
+1.8V_VCTi
2
1
1
2
1
2
1
2
2
1
1
2
1
2
1
2
+3.3V_MICOM
1
2
1
2
1
2
1
1
2
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
1 2
2
1
2
2
GND
3
PWMV
DFVBL
SDA
SCL
P21
P20
P17
P16
P15
P14
P13
P12
P11
P10
XROMQ
EXTIFQ
VSUP3.3FE
GND0
GND1
VSUP1.8FE
VOUT3
VOUT2
VOUT1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
P37/656IO7
P36/656IO6
R303
2
1
2
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
VSUP1.8FE
VCR_ARIN_R
VCR_ARIN_L
DTV_AIN_L
DTV_AIN_R
R116
2 SCART_ALIN_L2
2 SCART_ARIN_R2
2 SCART_ALIN_L1
2 SCART_ARIN_R1
2
2
AUDIO_SWA
C958
1.5nF
C964
1.5nF
C938
1.5nF
C354
*
C927
1.5nF
4.7K
2 SVHS-LIN
2 SVHS-RIN
2 DVD_AL
2 DVD_AR
C360
1.5nF
C358
1.5nF
R3105 2
1 100 C353 2
R3101 2
C920
1.5nF
R948 2
R931 2
C939
1.5nF
R952 2
R953 2
1 4.7UF/16V
1 4.7UF/16V
1 4.7UF/16V
1 4.7UF/16V
1 100 C921 2
1 100
C928 2
1 100 C932 2
1 100
C933 2
1 4.7UF/16V
1 4.7UF/16V
1 4.7UF/16V
1 4.7UF/16V
C355
*
when side AV remove.1.5nF use
1 100 C352 2
1 4.7UF/16V
R114
1 4.7UF/16V
AV_SW_A
1 4.7UF/16V
4.7K
4.7K
R115
C115
*
R1020
*
1 4.7UF/16V
R1021
*
1 100
1 100
5 AUDIO_SWB
1 100 C357 2
1 100
C356 2
Q102
KSC1623
R391
1 100 C963 2
1 100
C965 2
1 100 C957 2
1 100
C959 2
R3100 2
C926
1.5nF
R933 2
R932 2
C116
*
R117
4.7K
R1009
1
2
4.7UF/16V
+8V_SW_OFF
C962
1.5nF
R1005 2
R1007 2
C956
1.5nF
R1002 2
R1003 2
C361
1 100
C359 4.7UF/16V
2
1 R1008 2
C922
1.5nF
1 100
HDMI1_AUDIOR
HDMI1_AUDIOL
1 4.7UF/16V
AV_SW_A
Q101
KSC1623
R390
+8V_SW_OFF
R389
7
16
10
9
1
5
2
4
12
14
15
11
AV_SW_B
74HC4052
VEE
VDD
EN
A
B
Y0
Y1
Y2
Y3
X0
X1
X2
X3
Y
74HC4052
VEE
VDD
EN
A
B
Y0
Y1
Y2
Y3
X0
X1
X2
X3
U308
U307
R392
7
16
10
9
1
5
2
4
12
14
15
11
13
13
C347
1uF
R386
1
R382
1
*
C348
1uF
R387
1
R383
1
AUDIO_SWB
1
2
AV_DTV_R 3
C344
0.1uF
R562
*
C553
+
47uF/50V
1 1K
VCTi 2:PC
VCTi 3:DTV
FUNCTION
12V-AMP
R231
*
1
2
3
4
+5V_1TUNER
2:DVD
3:SCART1
2:SVHS
3:SCART2
R227
*
VCTi
VCTi
VCTi
VCTi
2 C207
*
8
7
6
5
C551
1nF
R510 2
R507 2
R528 2
R532 2
*
Q907
C549
1nF
+3.3V_MICOM
C547
1nF
C546
1nF
C548
*
R511
2
1UF/16V
R533
*
+5V_1TUNER
L508
1
2
HH-2012-121
R400
L506
1
L507
1
C539
*
C515 +
47uF/50V
R534
47K
1UF/16V
2
100
1
C538
1nF
C541
1nF
L503
1
2
HH-2012-121
C510
Q504
KSC1623
C509
1 *
1 *
1 1K
R531
C540
1nF
HH-2012-121
2
HH-2012-121
2
12V-AMP
L510
1
C550
*
L509
1
1 3.3K
POP_NOISE
R225
*
LOUT+
LOUT-
HEADPHONE-VOLUME
3 LOUD_OUT_L
NC0
NC2
IN
VCC
NC1 OUT
GND DCAP
U203
R922
ROUT-
ROUT+
3 LOUD_OUT_R
+5VS
POP_NOISE1
Q506
KSC1623
R560
*
2,3,7,8
VCTi 2:HDMI1_MST6181
VCTi 3:VCR
+3.3V_MICOM
R558 2
R561
0
+3.3V_MICOM
12V-AMP
+3.3V_SCALER
HDMI_AIN_R
HDMI_AIN_L
AV_DTV_L
AUDIO_SWA
AMP_STANDBY
C345
0.1uF
+8V_SW_OFF
+8V_SW_OFF
C960
1.5nF
2
1
1
1 4.7UF/16V
2
1
1
2
1 100 C362 2
1 100
C363 2
1
2
R3104 2
C961
1.5nF
2
1
2
1
1
L505
1
+5V_AUDIO
C543
1nF
C542
*
L502
1
R535
43K
R536
8.2K
C520
HH-2012-301
2
3 HP-L
3 HP-R
HH-2012-301
2
HH-2012-301
2
R537
24K
49
1
2
3
4
5
6
7
8
9
10
11
12
0.01uF
2C516
0.01uF
HP-L
+5V_AUDIO
2C519
0.01uF
2C517
0.01uF
EPAD
/SD
RINN
RINP
V2P5
LINP
LINN
AVDDREF
VREF
VARDIFF
VARMAX
VOLUME
REFGND
U502
HP-R
C525
0.1uF
R538
15K
21uF
21uF
21uF
C522
0.1uF
HH-2012-301
2
C513 1
C511 1
C512 1
R1004 2
R1006 2
AV_SW_A
AV_SW_B
2
1
2
C365
+
+
1
2
1
1
2
1
2
1
2
1
2
1
2
1
2
48
47
46
45
44
43
42
41
40
39
38
37
2
R552
1K
2
0.1uF
C518
+
47uF/50V
C537
2
220uF/16V
1
2
1
C544
2
C514
TPA3004
2 0.1uF
C536
2
220uF/16V
R553
1K
C545 1
2
2
2
2
C528 2
R547
R551
R529
R530
VCLAMPR
MODE_OUT
MODE
AVCC
VAROUTR
VAROUTL
/FADE
AVDD
COSC
ROSC
AGND
VCLAMPL
BSRN
PVCCR1
PVCCR2
ROUTN1
ROUTN2
PGNDR1
PGNDR2
ROUTP1
ROUTP2
PVCCR3
PVCCR4
BSRP
BSLN
PVCCL1
PVCCL2
LOUTN1
LOUTN2
PGNDL1
PGNDL2
LOUTP1
LOUTP2
PVCCL3
PVCCL4
BSLP
13
14
15
16
17
18
19
20
21
22
23
24
36
35
34
33
32
31
30
29
28
27
26
25
1
1
1
1
12V-AMP
BYP
GND
SD
IN2
TPA6110A2
IN1
VO1
VDD
VO2
U503
R549 2
R550 2
R546
10K
C533
0.47uF
CONFIDENTIAL
R548
1
AUDIO_MUTE 5
HEADPHONE_MUTE
R503
R502
R542
1K
Q505
KSC1623
AMP_STANDBY
+5V_AUDIO
R545
10K
C531
1uF
1K
AUDIO_MUTE
Q507
KSC1623
HP-SENSE
Date
Tuesday, April 25, 2006
4
8
Sheet
of
Size Rev
Document Number
A4
<Doc>
Custom
100
1K
R559
R539
1K
R501
10K
10K
+5V_AUDIO
R504
C552
+
100uF/16V
C532
1uF
Q502
KSC1623
04. AUDIO SWITCH&AMP
AM0005
INS60256487
1
2
3
4
1 5.1K
1 5.1K
3 HEADPHONE_OUT_R
3 HEADPHONE_OUT_L
2 1uF
2 300P
1 91K
Q501
KSC1623
KSC1623
Q503
Note
Designer
Daeil Plaza #602, 528-3, Chonchun-Dong, Jangan-Gu,Suwon, Kyounggi-Do, 440-330, Korea
Address
Title
R505
10K
*
HEADPHONE_OUT_R 3
HEADPHONE_OUT_L 3
C523
0.1uF
8
7
6
5
+5VS
2 C529
1uF
1
C535
100uF/16V
C521
0.1uF
+ C534
470U/16V
C526 1
C527
1
R540 2
R541
12V-AMP
0/2012
0/2012
0/2012
0/2012
47uF/50V
10.1uF
1
2
1
PC-AIN-L
PC-AIN-R
2
1
R406
1
2
1
1 1
R403
2
2
1 2
1
2
AV_SW_B
2
2
2
R544 *
2
1
2
1
2 2
1
2
1
1
2 2
1
2
1
2
1
1
1
1 1
R405
2
+
2
1
2
1
2
2
1
1 R543 * 1
+
1
+
2
C108
0.1uF
C141
0.1uF
RX0+
RX0-
RXC+
RXC-
2
2
2
2
R127
R134
0.047uF
C954
7 HSYNC-HDMI
7 DE-HDMI
7,8 VCLK-HDMI
ADC-G7
ADC-G6
VDDC
ADC-G0
ADC-G1
ADC-G2
ADC-G3
ADC-G4
ADC-G5
VDDP
ADC-R0
ADC-R1
ADC-R2
ADC-R3
ADC-R4
ADC-R5
ADC-R6
ADC-R7
0.047uF
1nF
10K
10K
0.047uF
C951
C952
C168
0.1uF
C137 C127 C169 C165 C133 C103 C101

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Y101
14.318MHZ
1K
R121
1M
GND1
GND2
DVI_R+
DVI_RGND6
DVI_G+
DVI_GAVDD_DVI0
DVI_B+
DVI_BGND7
DVI_CK+
DVI_CKAVDD_DVI1
REXT
AVDD_PLL0
GND8
DDCD_DA
DDCD_CK
GND9
AVDD_ADC0
HSYNC1
VSYNC1
BIN1P
BIN1M
SOGIN1
GIN1P
GIN1M
RIN1P
RIN1M
BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
AVDD_ADC1
GND10
HSYNC0
VSYNC0
RMID
REFP
REFM
GND11
GND12
VDDP1
VI_DATA[16]
VI_DATA[17]
VI_DATA[18]
VI_DATA[19]
VI_DATA[20]
VI_DATA[21]
VI_DATA[22]
VI_DATA[23]
VI_DATA[8]
VI_DATA[9]
VI_DATA[10]
VI_DATA[11]
VI_DATA[12]
VI_DATA[13]
VDDC2
GND13
VI_DATA[14]
VDDC
R101
R1141
R1140
+1.8V_SCALER
VDDC
4 HDMI1_AUDIOR
MST6_AUWS
MST6_AUSD
MST6_AUSCK
AVDD_DVI VDD_MPLL AVDDA
7 HPD_CONTROL
4 AUDIO_SWA
4 AUDIO_MUTE
4 AMP_STANDBY
+3.3V_SCALER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
VDD_MPLL
22pF
R113
C107
1uF
C163 C139 C164 C136 C138 C134

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VDDM
C104 C102 C413 C113 C132 C167

0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
VDDC
AVDD_DVI
2 C129
0.1uF
2 C130
0.1uF
AVDDA
C949
6,7 SCALER_RESET
VDDP
ADC-G[7..0]
C110 C111
0.1uF 0.1uF
AVDDA
2
GREEN_IN
2
G_GND_S
2
RED_IN
2
R_GND_S
2 COM_PB_GND
2
COM_PB
2 COM_Y_GND
2
COM_Y
2
COM_SYNC
2 COM_PR_GND
2
COM_PR
RX1+
RX1-
2
2
390
2 AVDD_DVI
RX2+
RX2-
C106
2 22pF
1K
C105 1
2
2
R104
C114 1
0.1uF
ADC-R[7..0]
AVDD_DVI
2 PC_HSYNC_IN
2 PC_VSYNC_IN
2
BLUE_IN
2
B_GND_S
VDD_MPLL AVDD_PLL2
C112 C109
0.1uF 0.1uF
AVDD_DVI
2 DVI_DDC_DAT
2 DVI_DDC_CLK
R118
C118
1uF
ADC-B[7..0]
HEADPHONE-VOLUME
VCT656_CLK
ADC-B0
ADC-B1
ADC-B2
ADC-B3
ADC-B4
ADC-B5
ADC-B6
ADC-B7
7,8
C707
1uF
VCT656[0..7]
R102
*
AVDD_PLL2
R396
*
R3102 2
1
R158 1
R172 1
R173
VDDP
VDDP
VDDC
U101A
MST6181
11K
2
2 22
2 22
22
3
3
3
3
3
3
3
4.7K
C170
22pF
C171
22pF
R167
R103
C172
22pF
4.7K
+ C174
10uF/16V
1
2
3
4
5
6
7
1uF
C166
R171
WM8725
LRCIN
SCKI
DIN
FORMAT
BCKIN DEEMPH
NC0
NC1
CAP
MUTE
VOUTR
VOUTL
GND
VDD
U103
14
13
12
11
10
9
8
R3103
0.1UF
C175
C173
22pF
R174
SUB_RFSW
1
R176 1
R177
VDDM
22
5
6
7
8
RA115
5
6
7
8
5
6
7
8
5
6
7
8
1
4
3
2
22 1
1
22
R166
4
RA113 3
2
22 1
4
RA117 3
2
22 1
4
RA116 3
2
22 1
FSDQS
FSDQM1
2
1
2RA125
3
4 22
1
2RA126
3
4 22
VDDP
2
22
1K
R399
*
R149
22
HDMI1_AUDIOL
1K
*
0
22
1 RA120
2
3
4
1 RA114
2
3
4
1 RA118
2
3
4
FSCLK+
FSCLKFSCKE
FSVREF
FSADDR7
FSADDR6
FSADDR5
FSADDR4
FSADDR3
FSADDR2
FSADDR1
FSADDR0
C159
C160
+2.5V_MEM
C161
/FSRAS
FSBKSEL0
FSBKSEL1
/FSWE
/FSCAS
C158
FSDQM1
FSDQM0
C155
C144
C154
C153
C152
C151
C150
/FSRAS
/FSCAS
/FSWE
FSDQS
FSCLKFSCLK+
FSCKE
22
22
22
22
C145
R145
R143
R146
R142
C146
C147
C148
38
39
40
41
42
43
44
87
88
89
90
91
93
23
56
24
57
54
55
53
28
27
26
25
94
FSCLKFSCLK+
FSCKE
/FSRAS
/FSCAS
/FSWE
FSDQS
29
30
31
32
33
34
47
48
49
50
51
45
36
37
FSBKSEL0
FSBKSEL1
FSADDR0
FSADDR1
FSADDR2
FSADDR3
FSADDR4
FSADDR5
FSADDR6
FSADDR7
FSADDR8
FSADDR9
FSADDR10
FSADDR11
R615
R200
R201
PDP
open
short
*
*
* R200
* R201
LCD_VDD
TXA2TXA2+
TXA1TXA1+
TXA0TXA0+
C367
22uF/16V
LCD_VDD
TXA3TXA3+
+3.3V_SCALER
+5V_OFF
TXA3TXA3+
R438
R440
TP47
TP45
TP43
TP41
TP39
U102
HY5DU283222Q4H
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
*
*
R713
C366
*
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J102
MOLEX
P30
P29 P32
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2 P31
P1
PDP_DLP_SCL
PDP_DLP_SDA
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
2,6,7,8
2,6,7,8
31
32
R144
10K/1%
FSDATA8
FSDATA9
FSDATA10
FSDATA11
FSDATA12
FSDATA13
FSDATA14
FSDATA15
FSDATA16
FSDATA17
FSDATA18
FSDATA19
FSDATA20
FSDATA21
FSDATA22
FSDATA23
FSDATA24
FSDATA25
FSDATA26
FSDATA27
FSDATA28
FSDATA29
FSDATA30
FSDATA31
9
10
12
13
17
18
20
21
74
75
77
78
80
81
83
84
add
100
100
R718
R719
R168
R169
R186
R199
R187
R170
R715
R713
DLP
delete
100
R720
R168
R169
R186
R199
R187
R715
R713
add
AM0005
ASIC_READY
LAMP_STATUS
DLP_RESET
UART_BALAST 9
FAN_STATUS
2
2
Note
Date
Sheet
of
5
8
Size Rev
Document Number
Custom A4
<Doc>
R718
R719
R720
R721
OTHERS
delete
DLP OPTION
100
R721
INS60256487 CONFIDENTIAL
R718
R719
R720
R721
05. MST6181A & DDR SDRAM

Designer
Address
Title
FSDATA[31..0]
+2.5V_MEM
P30
P29 P32 32
P28
P27
P26
R715
0
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
J21
P6
DF14A_30P_125H
P5
P4
P3
P2 P31 31
P1
FSDATA0
FSDATA1
FSDATA2
FSDATA3
FSDATA4
FSDATA5
FSDATA6
FSDATA7
R141
12K/1%
FSVREF
0 R162
0 R168
0 R169
0 R170
60
61
63
64
68
69
71
72
97
98
100
1
3
4
6
7
0.1uF
C143
FSVREF
*
*
TP48
TP46
TP44
TP42
TP40
TP38
TP49
TP50
R408
R409
TP37
TP36
0.1uF
C729
TP113
TP106
TP105
TP110
TP103
TP109
TP102
TP101
TP107
TP111
TP701
TXA0-
TXA0+
TXA1-
TXA1+
TXA2-
TXA2+
TXAC-
TXAC+
TXA3-
TXA3+
TXACTXAC- TXAC+
TXAC+
TXA2TXA2+
TXA1TXA1+
TXA0TXA0+
+3.3V_SCALER
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
NC10
NC11
NC12
DM0
DM1
DM2
DM3
/CLK
CLK
CKE
/CS
/RAS
/CAS
/WE
DQS
BA0
BA1
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
R189
*
*
INV_CTRL
9
+2.5V_MEM
*
*
TP104
C162
*
INV_CTRL
LCD_VDD
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C149
+2.5V_MEM
*
*
FSBKSEL0
FSBKSEL1
FSADDR[11..0]
R615
R200
R201
LCD
short
VCT_SCL
2,6,7,8
open
VCT_SDA
PDP_DLP_SDA
2,6,7,8
R615
PDP_DLP_SCL
2,6,7,8
PDP/DLP OPTION
R189
R192
R193
short
R165
R164
R163
R181
Q208
KSC1623
1K
R275
TP108
R710
R711
2,6,7,8
Q104
KSC1623
R712
1K
PDP
R162
R170
open
LVDS_OPTION
+3.3V_SCALER
+5V_OFF
LG32;GND
LCD_VDD
R162
R170
R184
LCD
short
INV_CTRL
9
PDP OPTION
R714
R189
R192
R193
open
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
C157
+2.5V_MEM
+2.5V_SCALER
R1146
VDDM
22
22
22
1 RA122
2
3
4
1 RA123
2
3
4
22
22
1 RA119 FSADDR11
FSADDR10
2
FSADDR9
3
FSADDR8
4
+5V_OFF
UART_BALAST 9
HEADPHONE_MUTE
HDCP_CONTROL
DLP_RESET
9
SW_PANEL 9
FSDQS
FSDATA0
FSDATA1
FSDATA2
FSDATA3
FSDATA4
FSDATA5
FSDATA6
FSDATA7
FSDATA8
FSDATA9
FSDATA10
FSDATA11
R183
1 RA121 FSDATA12
FSDATA13
2
FSDATA14
3
FSDATA15
4
FSDQS
22
FSDQM0
MST6_AUMUTE
+5V_1TUNER
MST6_AUMCK
R1144
R1145
2 *
2 *
22
22
22
22
R155
R154
R156
R157
C142 1
C140 1
AVDD_PLL2
R148
R150
R151
VDDM
10uF/16V
DCAP_50D250
C176
8
7
6
5
8
7
6
5
8
7
6
5
22
8
7
6
5
R152
R153
22
22
R147
22
*
*
*
AUDIO_SWB
100
10
R159
R136
R137
R135
2 0.1uF
R140
22
8
7
6
5
22
8
7
6
5
22
8
7
6
5
VDDC
R139
R175
C135 1
+3.3V_SCALER
+2.5V_MEM
192
191
190
189
188
187
186
185
184
183
182
181
180
179
178
177
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
R1142
2
2 10K
10K
1
R178
BYPASS
NC0
PWM5
PWM4
PWM3
NC1
GPO[6]
GPO[5]
GPO[4]
VDDP2
GND14
GND15
VDDC3
GPO[3]
GPO[2]
GPO[1]
GPO[0]
GND16
VDDM2
DQS[0]
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
GND17
VDDM3
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
DQS[1]
DQM[0]
GND18
VDDC4
MADR[11]
MADR[10]
MADR[9]
MADR[8]
GND19
VDDM4
MADR[7]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]
WEZ
CASZ
GND20
VDDM5
RASZ
BADR[0]
BADR[1]
AVDD_PLL2
266
1
2
2
MST6_AUMUTE
MST6_AUWS
MST6_AUSCK
MST6_AUSD
MST6_AUMCK
TXA0TXA0+
TXA1TXA1+
TXA2TXA2+
TXACTXAC+
8
7
6
5
8
7
6
5
TXA3TXA3+
1
2RA127
3
4 22
8
7
6
5
GND
ALE_SCALER
RD_SCALER
WR_SCALER
AD0
AD1
AD2
AD3
VSYNC-HDMI
FIELD-HDMI
7
7
FSDQS
INV_DIM
1
2
256
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
239
238
237
236
235
234
233
232
231
230
229
228
227
226
225
224
223
222
221
220
219
218
217
216
215
214
213
212
211
210
209
208
207
206
205
204
203
202
201
200
199
198
197
196
195
194
193
1
1
2
AVDD_PLL1
XIN
XOUT
PWM1
PWM0
VI_CKB
NC2
NC3
NC4
NC5
VDDC5
GND21
VI_DATA[31]
VI_DATA[30]
VI_DATA[29]
VI_DATA[28]
BUSTYPE
GND22
VDDP3
VI_DATA[27]
VI_DATA[26]
VI_DATA[25]
VI_DATA[24]
NC6
NC7
NC8
NC9
NC10
NC11
LVBOM
LVBOP
VDDC6
GND23
GND24
VDDP4
LVB1M
LVB1P
LVB2M
LVB2P
LVBCKM
LVBCKP
LVB3M
LVB3P
VDDC7
GND25
LVA0M
LVA0P
LVA1M
LVA1P
LVA2M
LVA2P
LVACKM
LVACKP
GND26
VDDP5
LVA3M
LVA3P
NC12
NC13
NC14
NC15
NC16
NC17
GND27
2
2
8
14
22
59
67
73
79
86
96
VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VSSQ0
VSSQ1
VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8
5
11
19
62
70
76
82
92
99
VI_DATA[15]
DHSYNC
DE
VI_CKA
VI_DATA[0]
VI_DATA[1]
VI_DATA[2]
VI_DATA[3]
VI_DATA[4]
VI_DATA[5]
VI_DATA[6]
VI_DATA[7]
VDDC0
GND0
GND28
VDDP0
HWRESET
INT
ALE
RDZ
WRZ
DBUS[0]
DBUS[1]
DBUS[2]
DBUS[3]
DBUS[4]
DBUS[5]
DBUS[6]
DBUS[7]
DDCR_CK
DVSYNC
FIELD
DDCR_DA
PWM2
VDDC1
GND29
DQS[3]
MDATA[31]
MDATA[30]
MDATA[29]
MDATA[28]
VDDM0
GND3
MDATA[27]
MDATA[26]
MDATA[25]
MDATA[24]
MDATA[23]
MDATA[22]
MDATA[21]
MDATA[20]
MDATA[19]
MDATA[18]
MDATA[17]
MDATA[16]
DQS[2]
DQM[1]
VDDM1
GND4
MVREF
MCLKE
MCLKZ
MCLK
GND5
2
15
35
65
95
VDD0
VDD1
VDD2
VDD3
VSS0
VSS1
VSS2
VSS3
16
46
66
85
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
2
2
1
1
2
58
VREF
MCL
FSDATA28
FSDATA29
FSDATA30
FSDATA31
52
1
2
VCT6564
VCT6565
VCT6566
VCT6567
0 R199
0 R186
VCT6560
VCT6561
VCT6562
VCT6563
FSDATA16
FSDATA17
FSDATA18
FSDATA19
FSDATA20
FSDATA21
FSDATA22
FSDATA23
FSDATA24
FSDATA25
FSDATA26
FSDATA27
2
2
2
SDI PDP
DELETE C208
C208 1nF
R224 1
2 R226 1
R919 1
1
R243 1
R244 1
R245
2 R230 1
R6
2.2K
2
2 100
2 100
100
+3.3V_MICOM
R232 1
1
R270 1
R271 1
R272
VCT_SDA
IRRCVR
2,3,7,8
2,3
OTHER
8
7
6
5
2 C2
0.1uF
VCT_SCL
M51958
NC0
NC2
IN
VCC
NC1 OUT
GND DCAP
2,3,7,8
DVB_ON
GPIO
IRR_MUTE
R13
1K
1
2
3
4
U1
1 2
R5
2.4K
+5VS
2
2
2
2
2
4.7K
4.7K
4.7K
*
100
2 *
2
2
C205
68P
C206
68P
2 R238
2 R236
R207 1
R206 1
R208 1
C208
*
2 LAMP_STATUS
2 ASIC_READY
R240 2
R241 2
R242 2
+3.3V_MICOM
CHK_DVI
CHK_DSUB
FAN_STATUS
M_DDC_CTL
+3.3V_MICOM
SDI PDP ONLY
+3.3V_MICOM
DA5/P5.5
P5.6/HSCL2
P5.7/HSDA2
RST
HSCL1/RXD/P3.0
NC1
HSDA1/TXD/P3.1
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
10K
10K
C202
1uF
2
2
C204
33pF
7
8
9
10
11
12
13
14
15
16
17
U202
2
X201
12MHz
C203
33pF
R221 1M
X1
1 *
1 *
1 0
1
2
X2
1
1
2
6
5
4
3
2
1
44
43
42
41
40
+3.3V_MICOM
1
R274 1
R273
X2
X1
MTV512
2
2
2
1
1
2
2
2
2
2
2
2
2
2
2
100
*
*
*
*
1 100
1 100
1
2
2
1
1
4.7K
15K
R213 2
R246 2
R215 2
R248
R249
R209
R211
KEY_AD2
KEY_AD1
ISP_CTL1
ISP_CTL2
1
1
1
1
*
*
*
*
AM0005
LEDWARNING4
LEDRED
2
SCALER_RESET 5,7
SW_REG_EN 9
+5V_OFF
C210
100nF
R233
R259
R250
R269
R237
R239
R210
R212
R214
R251
R216
2
2
Note
Date
of
6
8
Sheet
Size Rev
Document Number
A4
A4
<Doc>
TV_MENU
DVB_MENU
DTV_IDENT
THD_SS
ACD
TW_RESET
8
VCT_RESETQ 3
ISP_CTL1
2
ISP_CTL2
2
+3.3V_MICOM
5V_D
SCART_AVSW2 2
SCART_AVSW1 2
KEY_AD2
2,3
KEY_AD1
2,3
R218
R228
1 *
1 100
1 100
C209
1uF
1K
1K
1K
1K
1
1
1
1
100
100
*
*
1 100
CHK_DSUB
10K
CHK_DVI
10K
ASIC_READY 10K
LAMP_STATUS 10K
DTV_IDENT
10K
THD_SS
10K
ACD
10K
R204
R253
R247
R254
R252 2
+3.3V_MICOM
5V_D
39
38
37
36
35
34
33
32
31
30
29
R258
INS60256487CONFIDENTIAL
06. MICOM
Designer
Address
Title
2
2 4.7K
4.7K
R222
R223
R217
R219
R220
R924
R921
P1.4
P1.5
P1.6
P1.7
NC2
NC3
NC4
VSYNC
P6.7
P6.6/CLK01
P6.5
1K
1
2
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
NC5
VCC
P1.0/ET2
P1.1
P1.2
P1.3
P7.6/CLK02
P7.7
X2
X1
VSS
NC0
P6.0/AD0
P6.1/AD1
P6.2/AD2
P6.3/AD3
P6.4
18
19
20
21
22
23
24
25
26
27
28
1
2
+2.5V_TW
R465
2
R454
RF_CVBS
DVD_Y
SVHS_YIN
SUB_CVBS
SVHS_CIN
DVD_C
+2.5V_TW
2,3
2,3
SUB_CVBS
C447
0.1UF
2
2
L403
COIL-10UH
C431
0.1UF
C429
TW_AVDPLL
0.1UF
C432
TW9906
RST#
SDAT
SCLK
SIAD0
PDN
INTREQ
YBOUT
CLKX1
CLKX2
FIELD
VSYNC
HSYNC
DVALID
MPOUT
VD[0]
VD[1]
VD[2]
VD[3]
VD[4]
VD[5]
VD[6]
VD[7]
VD[8]
VD[9]
VD[10]
VD[11]
VD[12]
VD[13]
VD[14]
VD[15]
VD[16]
VD[17]
VD[18]
VD[19]
TW_VDDE
TW_VDDE
TW_AVDPLL
0.1UF
0.1UF
NC0
NC1
NC2
NC3
NC4
NC5
NC6
NC7
NC8
NC9
XTO
XTI
TMODE
AMCLK
AMXCLK
ASCLK
ALRCLK
0.1UF 0.1UF
+3.3V_TW
21
22
23
24
25
26
27
28
29
20
19
14
15
16
17
MUX3
MUX2
MUX1
MUX0
CIN0
CIN1
VIN0
VIN1
TW_AVD
C445
TW_AVD
R452
2
27p
C434
+3.3V_TW
2
1M
1
1
1
1
35
36
37
38
42
43
31
32
U405
VCT_CVBS
TW_VDD
C446 C441
0.1UF
C439
C440
C438
C437
27Mhz
1
2
2
2
2
1
1
1
1
1 C444
1 C436
XTAL
TW_VDD
1
R456
TW_VDD
C435
*
*
*
*
2
2
2
2
X401
2
100nF
100nF
100nF
100nF
1 C443
1 C442
R310 75
100nF 2
100nF 2
*
*
R467
R466
R457
R455
C433
27p
C430
R484
R483
R461
R460
100
100
100
100
0.1UF
R328
R459
100
100
1K
1 R320
R464
R463
1 *
*
*
L404
COIL-10UH
R330 2
Q301
KSC1623
+5V_2TUNER
AVS0
AVS1
30
40
VSSE2
VSSE1
VSSE0
71
59
4
R331
470
11
53
74
VDD0
VDD1
VDD2
VSS0
VSS1
VSS2
VSS3
12
18
52
65
3
60
72
VDDE0
VDDE1
VDDE2
TW_AVDPLL
46
YGND
39
33
44
AVD0
AVD1
AVSPLL
45
AVDPLL
CGND
41
51
50
49
48
47
54
34
*
R477
*
R475
R478
*
100
R474
100
R476
R462
2
+2.5V_VID
+3.3V_VID
5
6 RA406
7
*
8
1 R468 *
5RA405
6 *
7
8
5 RA404
6 *
7
8
5
6RA403
7 *
8
ADC-B0
5
ADC-B1
6
ADC-B2
7
ADC-B3
8
ADC-B4
5
ADC-B5
6
ADC-B6
7
ADC-B7
8
47
R450 47
2
2
4
3
2
1
13
10
9
8
7
73
70
4
3
2
1
4
3
2
1
4
3
2
1
4
RA402 3
47 2
1
4
3
2
1
RA401
2
1
80
79
78
77
76
75
69
68
67
66
64
63
62
61
58
57
56
55
R480
2
R479
2
+2.5V_TW
2 TUNER
1 TUNER
1
C611
2 R613
0.01UF
2 HH-2012-121
+ C618
C621
20pF
1 R618
1 R617
C622
20pF
0.01UF
470U/16V
C614
10UF/50V
C613
1.5nF
C620
+ C619
R612 68
2
1
R619
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
+5V_2TUNER
AM0005
U601
Note
Date
Friday, April 07, 2006
Sheet
7
8
of
Size Rev
Document Number
<Doc>
Custom A4
TCLW3001PC29A(H)
21
20
19
18
2 TUNER PAGE
Designer
Address
Title
NC1
NC2
NC3
NC4
ADDRESS:C6
IFOUT
NC5
NC6
AGC
SAS
SCL
SDA
5V/B+
SIF
NC7
CHASSIS3
AUDIO_OUT
CHASSIS2
AFT
CHASSIS1
VIDEO_OUT
CHASSIS0
CHANGE : U639 TECH2949PS40A(D), U602 TCPW3001PC29A(H)
DELETE :
CHANGE : U639 TECH2949PG40B(D)
DELETE : THIS PAGE & POWER OPTION
R611
75
L604
C612
2
100 1
100 2
100 2
1
2
L605 COIL-3.3UH
4.7UF/16V
1
RF_CVBS
+33V_T2
RF_MONO
5,7
+3.3V_TW
TW_RESET 6
VCT_SDA 2,3,6,7
VCT_SCL 2,3,6,7
VCLK-HDMI 5,7
ADC-B[7..0]
+5V_2TUNER
2,3,6,7 VCT_SCL
2,3,6,7 VCT_SDA
1
2
TW_VDDE
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
2
1
1
2
3
4
5
6
7
8
9
10
11
12
R1851
R1881
R1871
2 0
2 *
2 *
12V-AMP_CD
+12V_CD
+12V_DVD_CD
INV_DIM 5
INV_CTRL 5
+3.3V_SCALER
+5VS
+5V_OFF_CD
C706 +
0.1uF
C524 +
47uF/50V
R120
R229
1
5V_IDTV
+12V_DVD_CD
10k
47K
P6
AP1501_ADJ
KSC1623
Q207
R706
C530
*
R203
1
5V_IDTV
MBRS340
L70133UH
R702
1K 1%
U701
2
1uF
R707 47K
1
C117
ZD701
J913
COND3P
SS PDP 9-2
+5VS
THD_SS
P_CTRL_SS
+3.3V_OFF_SS
+5V_OFF_SS
R191 0
IRF7404
S1
S2
S3
G
U309
D1
D2
D3
D4
+5V_OFF
IN
IN
C726
220uF/16V
8
7
6
5
12V-AMP_CD
12V-AMP_SS
12V-AMP_LG
+12V_CD
+12V_SS
+12V_LG
+5V_OFF_LG
+5V_OFF_SS
+5V_OFF_CD
+5V_DVD_CD
+5V_DVD_SS
+5V_DVD_LG
+12V_DVD_SS
+12V_DVD_CD
+12V_DVD_LG
C794SOT-223
0.1uF
U716
RC1117-3.3
C792SOT-223
0.1uF
470U/16V
C732
+
9.1K 1%
C733
*
0.1uF
C728
TAB
OUT
TAB
OUT
4
2
4
2
C524 47uF/50V
R701 9.1K 1%
R702 3K 1%
100uF/16V
C716
7
6
5
4
3
2
1
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
J704
DELETE
R192
R229
R193
12
11
10
9
8
7
6
5
4
3
2
1
3
VCC
U706
J705
P4
P3
P2
P1
SMAW250
Q206
KSC1623
1K
R262
R708
1K
R179
0
Q204
KSC1623
R701 9.1K 1% OHM

R702 1K 1% OHM
C524:IDTV_only
J913
R202
R203
DELETE
ADD
LCD 12V
DELETE
R161
470
SW_PANEL
R267
+3.3V_MICOM
0.1uF
C718
0.1uF
C715
+1.8V_VCTi
R268
P_CTRL1 5
0.1uF
C721
+3.3V_MICOM
+24V_LG
+5V_OFF
Q103
KSC1623
4
3
2
1
COND4P_SMW250
R263
C724
220uF/16V
2
4
4
2
C714
100uF/16V
TAB
OUT
KSC1623
Q203
I_DTV
1K
1K
OUT
TAB
9
SW_PANEL_P
P_CTRL
R180
*
LG PDP
U701 AP1501 ADJ

R192 0 OHM
R193 0 OHM
ADD
IN
U705
RC1117-1.8
LG PDP 9-3
+12V_DVD_LG
+12V_LG
+5V_DVD_LG
+5V_OFF_LG
SMW250
NORMAL
SW_PANEL_P 5
5V_D
5
1k
R257
R256
+5VS
C720
0.1uF
RC1117-3.3
ACD
5
P_CTRL1 5
+5VS
COND12P_SMW250
J706
P7
P6
P5
P4
P3
P2
P1
COND7P_SMW250
R255
R264
3
C713
0.1uF SOT-223
+3.3V_OFF_SS
R778
R777 0
+5VS
+5V_OFF
SW_REG_EN
IDTV LCD 5V
U701 AP1501 ADJ

R202 0 OHM
R203 0 OHM
ADD
12V-AMP
+12V
+5V_OFF
+5V_DVD
+12V_DVD
+3.3V_VID
+3.3V_SCALER
LCD_VDD
5
12V-AMP_LG
C796
0.01uF 0.001uF
C795
R192
1
GND
U715
RC1117-3.3
LCD 9-7
1
2
3
4
R701
IDTV LCD 5V PANEL, LG PDP 9-6
0.1uF
C705
+24V_LG
11
10
9
8
7
6
5
4
3
2
1
+5V_OFF
+12V_CD
J921
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
COND11P_35155-1000
5 SW_PANEL
MOLEX
J702
+5V_OFF
ZD601
UDZ33B
220uF/16V
C625
0.1uF
C731
+5V_2TUNER
R614 4.7K
+33V_2TUNER
P_CTRL_SS
C725
220uF/16V
C615
0.1uF
3
IN
+12V
R198
*
OUT
C719
100uF/16V
C177
C793
0.1uF 100uF/16V
D701 BAV99
C781 0.1uF
1
2
C737
0.1uF
R196 *
C179
0.1uF
VCC
U96
+12V 1
0.1uF
OUT
IN
RC1117-5
OUT
TAB
2
4
78M08
U702
IN
U704
RC1117-1.8
C717
VCC
U95
AM0005
2
4
R195
*
+5V_1TUNER
Note
Date
Wednesday, April 12, 2006
Sheet
8
8
of
Size Rev
Document Number
A4
<Doc>
A2
RC1117-5
OUT
TAB
0.1uF
C156
0.1uF
+2.5V_SCALER
C711
+1.8V_SCALER
C785
100uF/16V
4
2
+33V_T
C779
0.1uF
R197
*
1
R194 *
C722
0.1uF
<OrgAddr4>
Designer
Address
Title
4
2
C712
100uF/16V
TAB
OUT
TAB
OUT
UDZ33B
U713
RC1117-2.5
IN
ZD707
SOT-223
C784
0.1uF
+8V_SW_OFF
+5V_2TUNER
100uF/16V
+5V_OFF
100K
R771
R772 4.7K
+33V_2TUNER
C710
0.1uF SOT-223
+3.3V_OFF_SS
BAV99
C783
0.1uF
D703
0.1uF
C730
R776
R775 0
+5V_OFF
+3.3V_VID
1
C778
+5V_1TUNER
C626
BAV99
0.1uF
220uF/16V
C777
1
C776 0.1uF
1
2
C782 0.1uF
1
2
D702
C178
0.1uF
+2.5V_VID
+8V_SW_OFF
2 TUNER 9-5
IN
U703 78M08
C791
100uF/16V
1
2
C786
100uF/16V
4
2
P14
P13
P12
P11
P10
P9
P8
C775
0.1uF
+3.3V_SCALER
TAB
OUT
4069
P1
P2
P3
P4
P5
P6
P7
U712
U714
RC1117-2.5
SOT-223
C787
0.1uF
+33V_T2
C723
220uF/16V
+5V_OFF
+12V
+5V_OFF
C780
1nF
R770 10K
1
2
P_CTRL1 5
COND10P_35155-1000
R182
0
2 +5V_DVD_SS
P10 10 1
MOLEX
P9 9
+12V_SS
P8 8
+3.3V_OFF_SS
+3.3V_SCALER
P7 7
1
2
12V-AMP_SS
P6 6
+12V_DVD_SS
P5 5
R190 0
4
P4
P3 3
+3.3V_OFF_SS
+3.3V_VID
2
P2
1
2
P1 1
LCD 9-1
COND12P
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
3
DELETE THIS WHEN THE SS PDP 9-4
+5V_DVD_CD
1
2
GND
1
2
1
2
GND
1
R266
1
2
1
2
1
2
1
2
1
2
1
2
1
2
GND
1
1
2
1
2
1
2
GND
1
1
2
J701
R202
1
R193
1
P1
P2
P3
P4
P5
1
2
3
4
5
1
2
1
2
1
2
GND
3
2
1
1
2
1
2
1
2
GND
1
1
2
1
2
2
1
G
4
1
2
G
4
1
2
1
2
1
2
1
2
2
GND
1
2
1
1
2
GND
1
2
1

__________________________________________________________________________________________________________________
41

__________________________________________________________________________________________________________________
42

__________________________________________________________________________________________________________________
43

__________________________________________________________________________________________________________________
44
TP1
R304
R305
150K
TP10 150K
Q300
BC337
J315
C317
100nF
TP15 R339
R341
270R
HS34
SMPS HEATSINK
3
TP2
TP21
TP3
J307
OFC
TP9
1N4148
T300
R307
33R
TP13
100R
TP16
D325
1N4007
VB2 1
BEAD
3
4
L310
100nF 275VAC
C357
TP59
3
TP60
2X27mH
TP61
C337
TP63
BL_ON/OFF
12
POWER
C328
8.2nF 400V
C361
8.2nF 400V
F301
TP28
TP31
R320
100R
5A
11
D310
MBR1045
MBR1045
10uH 7A
R310
12K
C948
C330
24V
L308
TP32
10
J300
TP17
5VMAIN
C336
220pF
1000uF/16V 1000uF 16V
D305
C315
100nF
TP36
C334
1000uF/16V
J301
TP53
TP62
1
TP55
4
5
TP96
TP97
7
TP92
C321
1nF/1KV
C319
5VSTBY
RS406
TP64
TP74
1nF/1KV
TP78
D304
BAT85
TP75
IC37
6
5
J314
TP72
J305
A_DIM 14
C359
100nF
C343
10uF
470R
J308
J309
TP83
C342
47pF
C338
TP67
1nF 400VAC
T301
4.7M 1/2W
C206
R317
4.7K 1%
12V
S301
R330
22K 1%
TP81
R346
FD2
FD3
5VMAIN
2
1
R336
1K 1%
CON4
STDBY
TP84 3.3K
T302
BC848B
GND
TP86
R347
33K
R203
TR20
TP73
5VSTBY
1K
L200
D200
STPS5L40
C210
470uF/35V
20uH 2.5A
TP82
C204
J320
J322
TP87
C211
100nF
470uF/16V
C205
100nF
TP112
D201
BYV36C
10
TP110
5
VFB VCC
GND
GND
GND VST
TP113
C213
33uF
TP116
SMPS STANDBY LCD
IC21
FSD200
IC20
6
5
C203
100nF
D326
1N4007
TP117
R201
1K
R202
TP118 470R
TCDT1101G
TP122
C207
47pF
100uF/400V
TP105
R343
1.2M
C208
15nF
C362
TP126
D202
TL431
R316
R332
150K
C335
100nF
R402
56K
TP111
TP103
TP102
D317
12V
NC
VCC
PCS
OUT
Q303
BC848B
J304
J302
TP130
4
TP131
R400
8.2K
C400
10pF
J317
RZI
GND
SRC
OFC
4.7K
R342
270R
BYV36C
5VOC
TP127
D309
1N4148
TP134
6
TP135
D400
1N4148
L400
BEAD
L305
100R
R405
BEAD
T401
SPP07N60
TP136 33R
TP137
C307
10pF
L306
D402
BYW76
TP120
C416
1nF 1KV
MBR20200CT
TP115
TP121
C417
1nF 1KV
R413
12
TP144 10R
R335
2.7K
L402
10uH 7A
TP124
C414
2200uF/35V
C405
100nF
24V
J327
TP129
C420
470uF/35V
C406
100nF
TP146
BEAD
C411
33nF/630V
TP138
R410
68K 1W
BEAD
TP139
C403
330pF
TP128
TP119 10R
D404
C413
680pF 2000V
L401
1M
R412
11
TP109
R404
TR40
TP108
R403
J316
TP133
TP114
ICE1QS01
C401
100nF
TP107
D324
8.2V
D401
C410
47uF/50V
8
2
4.7K
TP104 R340
IC40
TP132
D323
33V
R334
D319
2.4V
22pF
Q301
BC337
TP106
C304
R337
2.4K 1%
VB3
TP101150K
10uF/25V
C360
TP100
TP125
C200
47nF
R200
2.4K 1%
TP123
R205
33K
45
C202
R204
68K 1W
R331
TP89
1nF 400VAC
2.2nF 400VAC
CON14
HS35
POWER HEATSINK
STB
TP77 1K
R326
1K
BC848B
HS32
POWER HEATSINK
D303
TL431
C340
TP66
C358
47nF
5.6K 1%
TP69
TP71
2.2nF 400VAC
R303
HS30
POWER HEATSINK
TP85
R321
33K
TP80
FD1
TP68
2
OPS.
TP88
R322
C344
15nF
TP70
1nF 400VAC
C339
J311
CON10_W
13
R315
TP93
BL_ON/OFF 12
R345
47R
TP76
R314
1K
TCDT1101G
TP99
TP95
10
11
TP79
R344
47R
5VOC
10
D306
BAT85
8
TP98
5VMAIN
S302
5
BGND
SMPS LCD MAIN
TP65
24V
S305
C316
100nF
TP29
11
4
2X27mH
11
TP57
C308
100nF 275VAC
100nF 275VAC
L800
A_DIM
1
TP58
VR30
V320
F300
TP56 T3.15AL/250V
C320
1nF/1KV
TP35
7
12V
12
TP24
C318
1nF/1KV IC36
5
6
TP41
C312
100nF
C332
1000uF/25V
TP27
L303
VB
TP23
C324
R319
1.2M
4
L311
PFC
TP12
C347
100nF
14
270uF/400V
POWER
R327
2.2K
13
68K 1W
J303
C302
330pF
S303
C354
100nF/50V
10
C341
33nF 630V
TP22
R329
J313
1M
TP5
C351
1000uF/25V
C314
100nF
TP38
BEAD
R302
TP4
D308
BYW76
L301
C306
10pF
R309
16
TP25
C325
680pF 2000V
BEAD
SPP07N60
ICE1QS01
C301
47nF
BEAD
L304
C329
2200uF/25V
J324
20uH 2.5A
J329
5VSTBY
12V
L307
TP34
C300
10pF
TP8
D300
J331
TP43
C305
220pF
TP30
C303
220pF
R300
8.2K
SRC
L302
TP37
100R
D302
MBR20200CT
13
TP6
100R
2
3
J330
R308
15
TP26
R306
GND
TR30
OUT
RZI
TP20
12
S300
1
TP50
HS33
SMPS HEATSINK
PCS
11
STDBY
10
5VMAIN
VCC
NC
BYV36C
C322
47uF/50V
TP19
D322
12V
4.7K
Q302 4.7K
BC848B
TP11
D315
12V
33pF
IC30
D321
33V
TP18
R333
TP14
D318
2.4V
C345
Comment
J319
10uF/25V
C356
TP7
R301
56K
D301
C404
8.2nF 400V
6
TP140
C402
SMPS LCD BL
8.2nF 400V
6
J312
5
4
5VOC
J306
IC41
1
2
TP141
D320
5.1V
J318
C421
10uF
24V
J323
TP142 470R
TCDT1101G
J310
C408
100nF
R416
1K
R417
TP149
C418
47pF
C409
47nF
R418
33K
TP145
D403
TL431
R419
30K 1%
C419
15nF
TP148
R338
3.4K 1%
T400
R414
TP143 1K
BC848B
J328 STB J326
J325
TP147
R415
1K
10
11
12

__________________________________________________________________________________________________________________
Power Board
__________________________________________________________________________

__________________________________________________________________________________________________________________
__________________________________________________________________________
46

__________________________________________________________________________________________________________________
__________________________________________________________________________
47

__________________________________________________________________________________________________________________
__________________________________________________________________________
48
__________________________________________________________________________
AGND
S105
S104
S102
49
4
S106
S_VHS
AGND
AGND
75R
R105
AGND
75R
R104
47pF
C100
AGND
47pF
C101
AGND
AGND
AGND
C114
1nF
15K
BEAD
C110
1nF
R103
L111
AGND
15K
BEAD
C113
1nF
R102
AGND
C111
10pF
AGND
L110
BEAD
L107
C109
1nF
AGND
7
3
1
2
4
HEADPHONE 7P
S100
AGND
C116
1nF
AGND
C115
1nF
AGND
C100
220nF
AV_L
AV_CVBS
AGND
C101
220nF
22uH
L101
22uH
L100
AV_R
AGND
C102
100nF
AGND
C103
100nF
AGND
C104
10nF
R100
4.7R
AGND
C105
10nF
R101
4.7R
AGND
AGND
AGND 5
10
11
12
CON5
S103

__________________________________________________________________________________________________________________
Side AV
SW06
P(-)
SW05
V(+)
SW04
V(-)
R004
1.5K 1/6W
SW03
SOURCE
R003
2.7K 1/6W
SW02
MENU
R002
5.6K 1/6W
To main pcb
To infra pcb
S001
2
S002
C001
100nF
C002
100nF
MULTI BUTTON
R005
820R 1/6W
R006
470R 1/6W
GND
SW07
P(+)
R007
220R 1/6W

__________________________________________________________________________________________________________________
__________________________________________________________________________
50

__________________________________________________________________________________________________________________
B
1
2
VCC
IR
SW01
STBY
R004
15K 1/6W
1
2
S002
S001
GND
C002
100nF
470R
R003
33R 1/4W
R001
LED1
LED
GND
IR01
IR
C001
100uF
Infraled
INFRA RED
1
To mbutton pcb
__________________________________________________________________________
51

__________________________________________________________________________________________________________________
7. TROUBLESHOOTING
FAULT TRACING DIAGRAM FOR POWER SUPPLY
Check 220 V AC Mains
NO
Check AC Power Cable is Plugged
YES
Check C 020 Voltage
NO
Check X102 Fuse
YES
Check 5VSTBY
NO
Check T530 and Peripheral

Components
YES
Check 5V_OFF
NO
Check P_CTRL Pin

LOW
YES
Check 24V,33V,12V
8V
StandBy
Mode
NO
YES
HIGH
Normal Mode
Check Components
For 5V
Check Related Components for

Defective Outputs
NO
Check 3.3V,2.5V and 1.8V
YES
Check Related Components
POWER IS OK
__________________________________________________________________________
52

__________________________________________________________________________________________________________________
8.DATA SHEETS
Tuner Data Sheets
Specification
specification : PAL FST TU
SEM Model No.
TECH2949PS40A(D)
1. General Characteristics
1-1. Receiving System : CCIR Standard system
1-2. Channel
BAND
START CH
FREQ
END CH
FREQ
VHF Low
E2
45.75
S6
140.25
VHF High
S7
147.25
S36
423.25
UHF
S37
431.25
E69
855.25
1-3. Intermediate Frequency

SYSTEM
B/G
PICTURE
38.9
COLOR
SOUND
34.47
33.4
1-4. Input/Output Impedance

Input Impedance
75
Unbalanced
Output Impedance
Balanced
For Aymmetrical use of IF output, IF2 must be connected with 56
load to ground.
1-5. Tuning System : Frequency Synthesized Type

1-6. Band Change Over System : PLL System
1-7. Terminals for External Connection
NO
TERMINAL NAME
DESCRIPTION
AGC
NC
No Internal connection
SAS
Serial Address Selection
SCL
Serial Clock Line
SDA
Serial Data Line
NC
No Internal connection
BP
B+ for Internal IC
ADC
BT
Tuning Voltage supply
10
IF2
IF output 2
11
IF1
IF output 1
12
ANT
13
SUB P/J
AGC Voltage input
Analog/Digital Converter input
VHF/UHF signal input

VHF/UHF signal output for PIP sub-tuner.
______________________________________________________________________
__________________________________________________________________________
53

__________________________________________________________________________________________________________________
Specification
specification : PAL FST TU
TECH2949PS40A(D)
SEM Model No.
2. Limiting Values
2-1. Environmental condition
PAR
DESCRIPTION
MIN
TYP
MAX
TS
Storage Temperature
-20
+80
TO
Operation Temperature
-15
+65
RH
Relative Humidity for operation
UNIT
90
2-2. Electrical conditions

PAR
VB+
DESCRIPTION
MIN
TYP
MAX
UNIT
4.75
5.0
5.5
B+ Supply Current (LNA OFF)
90
120
B+ Supply Current (LNA ON)
120
150
5.0
5.5
4.0
4.5
33
35
B+ Supply Voltage
IB+
VFM
2nd Input activationg voltage
VAGC
AGC Input Voltage
VT
Tuning Supply voltage
VRIPPLE
Permissible ripple (20
4.75
30
to 500
P-P
VSCL
Serial clock input Voltage (see Note1)
5.5
VSDA
Serial data input Voltage (see Note1)
5.5
Note 1. I2C bus electrical requirements for operation are in 7-2.
3. Internal Semiconductors
3-1. Tuner section
PARTS
MAIN
Mixer+Oscillator+PLL IC
SN761672A
RF amplifier
UHF
BF1202
VHF
BF904
Tuning diode
UHF
BB555
VHF
BB659C, BB689
Tuning correction diode
SUB
BF909
EQUIVALENCE
BF2030
BF904WR, BF909WR
BB179
HVU202A, 1SV214
HVU300A, HVU306A
BB555
BB179
HVU202A, 1SV214
3-2. LNA section

PARTS
Pre-amplifier
MAIN
SUB
NE34018
EQUIVALENCE
NE38018
_______________________________________________________________________
__________________________________________________________________________
54

__________________________________________________________________________________________________________________
CAT24WC01/02/04/08/16
1K/2K/4K/8K/16K-Bit Serial EEPROM
FEATURES
Self-Timed Write Cycle with Auto-Clear
400 KHz I2C Bus Compatible*
1,000,000 Program/Erase Cycles
1.8 to 6.0Volt Operation
100 Year Data Retention
Low Power CMOS Technology
8-pin DIP, 8-pin SOIC or 8 pin TSSOP
Write Protect Feature
(Also available in new Lead-Free packages)
Entire Array Protected When WP at VIH
Commercial, Industrial, Automotive and
Page Write Buffer
Extended Temperature Ranges
DESCRIPTION
The CAT24WC01/02/04/08/16 is a 1K/2K/4K/8K/16Kbit Serial CMOS EEPROM internally organized as 128/
256/512/1024/2048 words of 8 bits each. Catalysts
advanced CMOS technology substantially reduces device power requirements. The the CAT24WC01/02/04/
08/16 feature a 16-byte page write buffer. The device

operates via the I2C bus serial interface, has a special
write protection feature, and is available in 8-pin DIP, 8pin SOIC or 8-pin TSSOP.
PIN CONFIGURATION
BLOCK DIAGRAM
SOIC Package (J, W)
DIP Package (P, L)
EXTERNAL LOAD
A0
A1
A2
1
2
3
8
7
6
VSS
A1
A2
1
2
3
8
7
6
VCC
WP
SCL
VSS
SDA
A0
VCC
WP
SCL
SDA
SENSE AMPS
SHIFT REGISTERS
DOUT
ACK
VCC
VSS
5020 FHD F01
WORD ADDRESS
BUFFERS
COLUMN
DECODERS
TSSOP Package (U, Y)

(MSOP and TSSOP available for CAT24WC01,
CAT24WC02 and CAT24WC04 only)
MSOP Package (R, Z)

NC
NC
NC
VSS
1
2
3
4
8
7
6
5
A0
A1
A2
2
3
7
6
VSS
VCC
WP
SCL
SDA
SDA
VCC
WP
SCL
SDA WP
START/STOP
LOGIC
XDEC
E2PROM
CONTROL
LOGIC
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
Device Address Inputs
SDA
Serial Data/Address
SCL
Serial Clock
WP
Write Protect
VCC
+1.8V to +6.0V Power Supply
VSS
Ground
DATA IN STORAGE
HIGH VOLTAGE/
TIMING CONTROL
SCL
A0
A1
A2
* Catalyst Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
STATE COUNTERS
SLAVE
ADDRESS
COMPARATORS
24WCXX F03
__________________________________________________________________________
55

__________________________________________________________________________________________________________________
Philips Semiconductors
Product specification
74HC4066; 74HCT4066
FEATURES
GENERAL DESCRIPTION
Very low ON-resistance:
The 74HC4066 and 74HCT4066 are high-speed Si-gate

CMOS devices and are pin compatible with the
HEF4066B. They are specified in compliance with JEDEC
standard no. 7A.
50 (typical) at VCC = 4.5 V

45 (typical) at VCC = 6.0 V
35 (typical) at VCC = 9.0 V.
The 74HC4066 and 74HCT4066 have four independent

analog switches. Each switch has two input/output pins
(pins nY or nZ) and an active HIGH enable input pin
(pin nE). When pin nE = LOW the belonging analog switch
is turned off.
Complies with JEDEC standard no. 8-1A

ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
The 74HC4066/74HCT4066 is pin compatible with the

74HC4016/74HCT4066 but exhibits a much lower
on-resistance. In addition, the on-resistance is relatively
constant over the full input signal range.
Specified from 40 to +85 C and 40 to +125 C.
QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 C; tr = tf = 6 ns.
TYPICAL
SYMBOL
PARAMETER
CONDITIONS
UNIT
74HC4066
74HCT4066
tPZH/tPZL
turn-on time nE to Vos
CL = 15 pF; RL = 1 k; VCC = 5 V
11
12
ns
tPHZ/tPLZ
turn-off time nE to Vos
CL = 15 pF; RL = 1 k; VCC = 5 V
13
16
ns
CI
input capacitance
3.5
3.5
pF
CPD
power dissipation
capacitance per switch
11
12
pF
CS
maximum switch
capacitance
pF
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + [(CL + CS) VCC2 fo] where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
CS = maximum switch capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
[(CL + CS) VCC2 fo] = sum of the outputs.
2. For 74HC4066 the condition is VI = GND to VCC.
For 74HCT4066 the condition is VI = GND to VCC 1.5 V.
__________________________________________________________________________
56

__________________________________________________________________________________________________________________
Philips Semiconductors
Product specification
74HC4066; 74HCT4066
FUNCTION TABLE
See note 1.
INPUT nE
SWITCH
off
on
Note
1. H = HIGH voltage level.
L = LOW voltage level.
ORDERING INFORMATION
PACKAGE
TYPE NUMBER
TEMPERATURE RANGE
PINS
PACKAGE
MATERIAL
CODE
74HC4066N
40 to 125 C
14
DIP14
plastic
SOT27-1
74HCT4066N
40 to 125 C
14
DIP14
plastic
SOT27-1
74HC4066D
40 to 125 C
14
SO14
plastic
SOT108-1
74HCT4066D
40 to 125 C
14
SO14
plastic
SOT108-1
74HC4066DB
40 to 125 C
14
SSOP14
plastic
SOT337-1
74HCT4066DB
40 to 125 C
14
SSOP14
plastic
SOT337-1
74HC4066PW
40 to 125 C
14
TSSOP14
plastic
SOT402-1
74HCT4066PW
40 to 125 C
14
TSSOP14
plastic
SOT402-1
74HC4066BQ
40 to 125 C
14
DHVQFN14
plastic
SOT762-1
74HCT4066BQ
40 to 125 C
14
DHVQFN14
plastic
SOT762-1
PINNING
PIN
SYMBOL
DESCRIPTION
1Y
independent input/output
1Z
2Z
2Y
2E
enable input (active HIGH)
3E
GND
handbook, halfpage
1Y
14 VCC
1Z
13 1E
2Z
12 4E
2Y
ground (0 V)
2E
10 4Z
3Y
3E
3Z
GND
8 3Y
10
4Z
11
4Y
12
4E
13
1E
14
VCC
supply voltage
4066
11 4Y
3Z
MGR253
Fig.1
Pin configuration DIP14, SO14 and

(T)SSOP14.
__________________________________________________________________________
57

__________________________________________________________________________________________________________________
Revised April 2002
CD4069UBC
Inverter Circuits
General Description
Features
The CD4069UB consists of six inverter circuits and is manufactured using complementary MOS (CMOS) to achieve
wide power supply operating range, low power consumption, high noise immunity, and symmetric controlled rise
and fall times.
This device is intended for all general purpose inverter
applications where the special characteristics of the
MM74C901, MM74C907, and CD4049A Hex Inverter/Buffers are not required. In those applications requiring larger
noise immunity the MM74C14 or MM74C914 Hex Schmitt
Trigger is suggested.
Wide supply voltage range:
3.0V to 15V
High noise immunity: 0.45 VDD typ.

Low power TTL compatibility:
or 1 driving 74LS
Equivalent to MM74C04
Fan out of 2 driving 74L
CD4069UBC Inverter Circuits
October 1987
All inputs are protected from damage due to static discharge by diode clamps to VDD and VSS.
Ordering Code:
Order Number
Package Number
Package Description
CD4069UBCM
M14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4069UBCSJ
M14D
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4069UBCN
N14A
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix X to the ordering code.
Connection Diagram
Schematic Diagram
__________________________________________________________________________
58

__________________________________________________________________________________________________________________
DATA SHEET
128M bits DDR SDRAM

EDD1232AAFA (4M words 32 bits)
Description
Features
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__________________________________________________________________________
59

__________________________________________________________________________________________________________________
EDD1232AAFA
Pin Configurations
[[[LQGLFDWHVDFWLYHORZVLJQDO
/CK
CKE
MCL
A8 (AP)
CK
VDDQ
VREF
DM3
DM1
DQ9
DQ8
DQ11
DQ10
VSSQ
DQ25
DQ24
VDDQ
DQ15
DQ14
VSSQ
DQ13
DQ12
VDDQ
VSS
VDD
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ28
VDDQ
DQ27
DQ26
VSSQ
100-pin plastic LQFP
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
A7
A6
A5
A4
VSS
A9
NC
NC
NC
NC
NC
NC
NC
A11
A10
VDD
A3
A2
A1
A0
/RAS
/CS
BA0
BA1
/CAS
VDDQ
DM0
DM2
/WE
DQ22
DQ23
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
DQ19
VDDQ
VDD
VSS
DQ20
DQ21
VSSQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
20 14mm2
0.65mm pin pitch
DQ3
VDDQ
DQ4
DQ5
VSSQ
DQ29
VSSQ
DQ30
DQ31
VSS
VDDQ
NC
NC
NC
NC
NC
VSSQ
NC
DQS
VDDQ
VDD
DQ0
DQ1
VSSQ
DQ2
(Top view)
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__________________________________________________________________________
60

__________________________________________________________________________________________________________________
EN29LV040
EN29LV040
da0.
4 Megabit (512K x 8-bit ) Uniform Sector,

CMOS 3.0 Volt-only Flash Memory
FEATURES
x High performance program/erase speed
- Byte/Word program time: 8s typical
- Sector erase time: 500ms typical
x Single power supply operation

- Full voltage range: 2.7-3.6 volt read and write
operations for battery-powered applications.
- Regulated voltage range: 3.0-3.6 volt read
and write operations for high performance
3.3 volt microprocessors.
x JEDEC Standard program and erase

commands
x JEDEC standard DATA polling and toggle
bits feature
x High performance
- Access times as fast as 45 ns
x Single Sector and Chip Erase

x Embedded Erase and Program Algorithms
x Low power consumption (typical values at 5

MHz)
- 7 mA typical active read current
- 15 mA typical program/erase current
- 1 PA typical standby current (standard access
time to active mode)
x
-
x Erase Suspend / Resume modes:

Read or program another Sector during
Erase Suspend Mode
x triple-metal double-poly triple-well CMOS
Flash Technology
x Low Vcc write inhibit < 2.5V
Flexible Sector Architecture:

Eight 64 Kbyte sectors
Supports full chip erase
Individual sector erase supported
Sector protection and unprotection:
Hardware locking of sectors to prevent
program or erase operations within individual
sectors
x >100K program/erase endurance cycle
x Package options
- 8mm x 20mm 32-pin TSOP (Type 1)
- 8mm x 14mm 32-pin TSOP (Type 1)
- 32-pin PLCC
x Commercial and industrial Temperature
Range
GENERAL DESCRIPTION
The EN29LV040 is a 4-Megabit, electrically erasable, read/write non-volatile flash memory,
organized as 524,288 bytes. Any byte can be programmed typically in 8s. The EN29LV040
features 3.0V voltage read and write operation, with access times as fast as 45ns to eliminate the
need for WAIT states in high-performance microprocessor systems.
The EN29LV040 has separate Output Enable ( OE ), Chip Enable ( CE ), and Write Enable (WE)
controls, which eliminate bus contention issues. This device is designed to allow either single
Sector or full chip erase operation, where each Sector can be individually protected against
program/erase operations or temporarily unprotected to erase or program. The device can sustain a
minimum of 100K program/erase cycles on each Sector.
__________________________________________________________________________
61

__________________________________________________________________________________________________________________
EN29LV040
CONNECTION DIAGRAMS
TABLE 1. PIN DESCRIPTION
FIGURE 1. LOGIC DIAGRAM
Pin Name
Function
A0-A18
Addresses
DQ0-DQ7
8 Data Inputs/Outputs
WE#
Write Enable
CE#
Chip Enable
OE#
Output Enable
Vcc
Supply Voltage
CE#
Vss
Ground
OE#
EN29LV040
A0 - A18
DQ0 DQ7
WE#
__________________________________________________________________________
62

__________________________________________________________________________________________________________________
August 1998
FDC6326L
Integrated Load Switch
General Description
Features
VDROP=0.20V @ VIN=12V, IL=1.5A.RDS(ON) = 0.125
VDROP=0.20V @ VIN=5V, IL=1A.RDS(ON) = 0.20 .
This device is particularly suited for compact power

management in portable electronic equipment where 3V to
20V input and 1.8A output current capability are needed.
This load switch integrates a small N-Channel power
MOSFET (Q1) which drives a large P-Channel power
MOSFET (Q2) in one tiny SuperSOTTM-6 package.
SOT-23
TM
SuperSOTTM-6 package design using copper lead frame for

superior thermal and electrical capabilities.
SO-8
TM
SuperSOT -6
SuperSOT -8
6
.32
Vin,R1
ON/OFF
SOIC-16
SOT-223
Vout,C1
Vout,C1
R2
EQUIVALENT CIRCUIT
Q2
+
IN
VDROP
OUT
Q1
R1,C1
pin 1
SuperSOT TM-6
ON/OFF
See Application Circuit
Absolute Maximum Ratings
T A = 25C unless otherwise noted
Symbol
Parameter
VIN
Input Voltage Range
VON/OFF
On/Off Voltage Range
IL
Load Current
PD
Maximum Power Dissipation
TJ,TSTG
Operating and Storage Temperature Range
ESD
Electrostatic Discharge Rating MIL-STD-883D Human Body

Model (100pf/1500Ohm)
- Continuous
- Pulsed
(Note 1)
FDC6326L
Units
3 - 20
2.5 - 8
1.8
(Note 1 & 3)
(Note 2)
0.7
-55 to 150
kV
THERMAL CHARACTERISTICS
RJA
Thermal Resistance, Junction-to-Ambient
(Note 2)
180
C/W
RJC
Thermal Resistance, Junction-to-Case
(Note 2)
60
C/W
__________________________________________________________________________
63

__________________________________________________________________________________________________________________
TECHNICAL DATA
IL1117A-x
1.0A Low Dropout Positive Voltage Regulator

Features
Adjustable and Fixed of 1.25, 1.5, 1.8, 2.5, 2.85, 3.3, 5.0V
Space saving SMD types of SOT-223
1.2V Drop-out Voltage
1.0A Output Current
Line Regulation Typically at 0.2% max
Current Limiting and Thermal Protection
IL1117A-x
General Description
The IL1117A is a series of low dropout voltage regulators which can provide
up to 1A of output current. The IL1117A is available in seven fixed voltage,
1.25, 1.5, 1.8, 2.5, 2.85, 3.3 and 5.0V. Additonally it is also available in
adjustable version. On chip precision trimming adjusts the reference/
output voltage to within 2%. Current limit is also trimmed to ensure
specified output current and controlled short-circuit current.
The IL1117A series is available in SOT-223 packages.
A minimum of 10uF tantalum capacitor is required at the output to
improve the transient response and stability.
Applications
Post Regulator for switching DC/DC Converter
High Efficiency Linear Regulator
Battery Chargers
PC Add on Card
Motherboard clock supplies
LCD Monitor
Set-top Box

Maximum Input Voltage ~ 15.0V
Operating Junction Temperature Range -25 ~ 125
Storage Temperature Range -50 ~ 150
__________________________________________________________________________
64

__________________________________________________________________________________________________________________
TECHNICAL DATA
IL1117A-x
Electrical Characteristics
(Vin = 5V, Co = 10uF, Ta = 25, unless otherwise specified)
__________________________________________________________________________
65

__________________________________________________________________________________________________________________
MST6181LDA
SXGA/WXGA LCD Multi-Function Monitor Controller with Dual LVDS Transmitter
FEATURES
Input supports up to UXGA & 1080P
Panel supports up to SXGA/WXGA
Auto-Configuration/Auto-Detection
Auto input signal format (SOG, Composite,
Integrated 8-bit triple-ADC/PLL
Separated HSYNC, VSYNC, and DE), and input
Integrated DVI/HDCP/HDMI compliant receiver
mode (all VESA & IBM modes w/ resolution
RGB/YUV 444 and YUV422 digital video input
and polarity) detection

Auto-tuning function including phasing,
ports
Dual high-quality scaling engines
positioning, offset, gain, and jitter detection
Built-in 3-D video de-interlacer
Sync Detection for H/V Sync
Video-over-graphic PIP
Dual High-Performance Scaling Engine
Video-by-graphic split screen
Fully Programmable shrink/zoom capabilities
MStarACE-2 picture/color processing engine
Nonlinear video scaling supports various
Embedded On-screen display controller (OSD)
modes including Panorama

Flexible independent control of sharpness for
engine
Digital audio I/O & sync processor
TV and graphic windows
Built-in dual-link LVDS transmitter
5 Volt tolerant inputs
3-D motion adaptive video de-interlacer with
Low EMI and power saving features
upgraded edge-oriented adaptive algorithm for
Supports PWM & GPO controls
smooth low-angle edges
256-pin LQFP
Automatic 3:2 pull-down & 2:2 pull-down

detection and recovery
Analog RGB Compliant Input Ports
PIP with programmable size and location,
Dual analog ports support up to 165Mhz

Supports PC RGB input up to UXGA@60Hz
supports multi-video applications
Supports HDTV RGB/YPbPr/YCbCr up to 1080P
Video-over-graphic overlay
On-chip high-performance PLLs
Video-by-graphic split screen
Supports Composite Sync and SOG
Frame rate conversion for both main window

and sub window
(Sync-on-Green) separator
MStar 2nd Generation Advanced Color Engine
Automatic color calibration

DVI/HDCP/HDMI Compliant Input Port
(MStarACE-2) automatic picture enhancement
Operates up to 165 MHz (up to UXGA @60Hz)
gives:
Single link on-chip DVI 1.0 compliant receiver
Brilliant and fresh color
High-bandwidth Digital Content Protection
Intensified contrast and details

Vivid skin tone
(HDCP) 1.1 compliant receiver

High Definition Multimedia Interface (HDMI)
Sharp edge
1.0 compliant receiver with I2S and S/PDIF
Enhanced depth of field perception
digital audio outputs
Accurate and independent color control
Long-cable tolerant robust receiving

Video Processing & Conversion
Independent picture control for main and sub

windows
Video Input Port
sRGB compliance allows end-user to
One RGB/YUV 4:4:4 24-bit and one 4:2:2
experience the same colors as viewed on CRTs
ITU656 8-bit digital video input ports

24-bit port supports 8/16-bit YUV 4:2:2 or
and other displays
24-bit RGB/YUV 4:4:4 interlaced/ progressive
Programmable 10-bit RGB gamma CLUT
video input up to 1080i/720P
3-D video noise reduction
__________________________________________________________________________
66

__________________________________________________________________________________________________________________
MST6181LDA
Supports 2 data output formats: Thine & TI
On-Screen OSD Controller

16/256 color palette
data mappings
256/512 1-bit/pixel font
Compatible with TIA/EIA
128/256/512 4-bit/pixel font
With 6/8 bits options
Supports texture function
Reduced swing for LVDS for low EMI
Supports 4K attribute/code
Supports flexible spread spectrum frequency
Horizontal and vertical stretch of OSD menus
with 360Hz~11.8MHz and up to 25%
Supports button function
modulation
Pattern generator for production test
Supports OSD MUX and alpha blending
Support 8051 parallel MCU bus

Supports 4-wire double-data-rate direct MCU
capability
Supports blinking and scrolling for closed
bus
32-bit data bus for external frame buffer (SDR
caption applications
External Connection/Component
or DDR DRAM)
LVDS Panel Interface
All system clocks synthesized from a single
Supports dual link up to 135MHz dot clock for
external clock
SXGA
GENERAL DESCRIPTION
The MST6181LDA is a high performance and fully integrated graphics processing IC solution for multi-function
LCD monitor/TV with resolutions up to SXGA/WXGA.
It is configured with an integrated triple-ADC/PLL, an
integrated DVI/HDCP/HDMI receiver, a video de-interlacer, two high quality scaling engines, an on-screen
display controller, and a built-in output clock generator.
multimedia applications.
By use of external frame buffer, PIP is provided for
It supports de-interlaced full-screen video, video-on-graphic overlay, split screen,
frame rate conversion, and aspect ratio conversion for various video sources.
To further reduce system costs,
the MST6181LDA also integrates intelligent power management control capability for green-mode requirements
and spread-spectrum support for EMI management.
__________________________________________________________________________
67

__________________________________________________________________________________________________________________
MST6181LDA
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
192
191
190
Pin 1
189
188
187
186
185
184
10
183
11
182
12
181
13
180
14
179
15
178
16
177
17
176
18
175
19
174
20
173
21
172
22
171
23
170
24
169
25
168
26
167
27
166
28
165
29
164
30
163
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
MST6181LDA
XXXXXXXXXXX
XXXXX
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
BYPASS
NC
PWM5
PWM4
PWM3
NC
GPO[6]
GPO[5]
GPO[4]
VDDP
GND
GND
VDDC
GPO[3]
GPO[2]
GPO[1]
GPO[0]
GND
VDDM
DQS[0]
MDATA[0]
MDATA[1]
MDATA[2]
MDATA[3]
MDATA[4]
MDATA[5]
MDATA[6]
MDATA[7]
MDATA[8]
MDATA[9]
MDATA[10]
MDATA[11]
GND
VDDM
MDATA[12]
MDATA[13]
MDATA[14]
MDATA[15]
DQS[1]
DQM[0]
GND
VDDC
MADR[11]
MADR[10]
MADR[9]
MADR[8]
GND
VDDM
MADR[7]
MADR[6]
MADR[5]
MADR[4]
MADR[3]
MADR[2]
MADR[1]
MADR[0]
WEZ
CASZ
GND
VDDM
RASZ
BADR[0]
BADR[1]
AVDD_PLL2
VI_DATA[15]
DHSYNC
DE
VI_CKA
VI_DATA[0]
VI_DATA[1]
VI_DATA[0]
VI_DATA[3]
VI_DATA[4]
VI_DATA[5]
VI_DATA[6]
VI_DATA[7]
VDDC
GND
GND
VDDP
HWRESET
INT
ALE
RDZ
WRZ
DBUS[0]
DBUS[1]
DBUS[2]
DBUS[3]
DBUS[4]
DBUS[5]
DBUS[6]
DBUS[7]
DDCR_CK
DVSYNC
FIELD
DDCR_DA
PWM2
VDDC
GND
DQS[3]
MDATA[31]
MDATA[30]
MDATA[29]
MDATA[28]
VDDM
GND
MDATA[27]
MDATA[26]
MDATA[25]
MDATA[24]
MDATA[23]
MDATA[22]
MDATA[21]
MDATA[20]
MDATA[19]
MDATA[18]
MDATA[17]
MDATA[16]
DQS[2]
DQM[1]
VDDM
GND
MVREF
MCLKE
MCLKZ
MCLK
GND
85
129
84
130
64
83
131
63
82
132
62
81
133
61
80
134
60
79
135
59
78
136
58
77
137
57
76
138
56
75
139
55
74
140
54
73
141
53
72
142
52
71
143
51
70
144
50
69
145
49
68
146
48
67
147
47
66
46
65
GND
GND
DVI_R+
DVI_RGND
DVI_G+
DVI_GAVDD_DVI
DVI_B+
DVI_BGND
DVI_CK+
DVI_CKAVDD_DVI
REXT
AVDD_PLL
GND
DDCD_DA
DDCD_CK
GND
AVDD_ADC
HSYNC1
VSYNC1
BIN1P
BIN1M
SOGIN1
GIN1P
GIN1M
RIN1P
RIN1M
BIN0M
BIN0P
GIN0M
GIN0P
SOGIN0
RIN0M
RIN0P
AVDD_ADC
GND
HSYNC0
VSYNC0
RMID
REFP
REFM
GND
GND
VDDP
VI_DATA[16]
VI_DATA[17]
VI_DATA[18]
VI_DATA[19]
VI_DATA[20]
VI_DATA[21]
VI_DATA[22]
VI_DATA[23]
VI_DATA[8]
VI_DATA[9]
VI_DATA[10]
VI_DATA[11]
VI_DATA[12]
VI_DATA[13]
AVDD_APLL
GND
VI_DATA[14]
255
256
AVDD_MPLL
XIN
XOUT
PWM1
PWM0
VI_CKB
AIWS
AISCK
AISD
AIMCK
VDDC
GND
VI_DATA[31]
VI_DATA[30]
VI_DATA[29]
VI_DATA[28]
BUSTYPE
GND
VDDP
VI_DATA[27]
VI_DATA[26]
VI_DATA[25]
VI_DATA[24]
SPDIFO
AUMUTE
AUWS
AUSCK
AUSD
AUMCK
LVB0M
LVB0P
VDDC
GND
GND
VDDP
LVB1M
LVB1P
LVB2M
LVB2P
LVBCKM
LVBCKP
LVB3M
LVB3P
VDDC
GND
LVA0M
LVA0P
LVA1M
LVA1P
LVA2M
LVA2P
LVACKM
LVACKP
GND
VDDP
LVA3M
LVA3P
NC
NC
NC
NC
NC
NC
GND
PIN DIAGRAM (MST6181LDA)
__________________________________________________________________________
68

__________________________________________________________________________________________________________________
MST6181LDA
PIN DESCRIPTION
MCU Interface
Pin Name
Pin Type
Function
Pin
HWRESET
Schmitt Trigger Input
Hardware Reset, active high
81
w/ 5V-tolerant
DBUS[7:0]
I/O w/ 5V-tolerant
MCU Direct bus; 4mA driving strength
93-86
ALE
I w/ 5V-tolerant
MCU Bus ALE, active high
83
RDZ
I w/ 5V-tolerant
MCU Bus RDZ, active high
84
WRZ
I w/ 5V-tolerant
MCU Bus WDZ, active high
85
INT
Output
MCU Bus Interrupt; 4mA driving strength
82
BUSTYPE
Input (not 5V-tolerant)
MCU bus type selection
240
Low (0V): 4-bit (DBUS[3:0]) DDR Direct Bus

High (3.3V): 8-bit (DBUS[7:0]) Direct Bus
Analog Interface
Pin Name
Pin Type
Function
Pin
RMID
Mid-Scale Voltage Bypass
42
REFP
Internal ADC Top De-coupling Pin
43
REFM
Internal ADC Bottom De-coupling Pin
44
REXT
Analog Input
External Resister 390 ohm to AVDD_DVI
15
HSYNC0
Analog HSYNC Input from Channel 0
40
Analog VSYNC Input from Channel 0
41
w/ 5V-tolerant
VSYNC0

w/ 5V-tolerant
BIN0M
Analog Input
Reference Ground for Analog Blue Input from Channel 0
31
BIN0P
Analog Input
Analog Blue Input from Channel 0
32
GIN0M
Analog Input
Reference Ground for Analog Green Input from Channel 0
33
GIN0P
Analog Input
Analog Green Input from Channel 0
34
SOGIN0
Analog Input
Sync On Green Input from Channel 0
35
RIN0M
Analog Input
Reference Ground for Analog Red Input from Channel 0
36
RIN0P
Analog Input
Analog Red Input from Channel 0
37
Analog HSYNC Input from Channel 1
22
Analog VSYNC Input from Channel 1
23
Reference Ground for Analog Blue Input from Channel 1
25
HSYNC1
w/ 5V-tolerant
VSYNC1

w/ 5V-tolerant
BIN1M
Analog Input
__________________________________________________________________________
69

__________________________________________________________________________________________________________________
MST6181LDA
Pin Name
Pin Type
Function
Pin
BIN1P
Analog Input
Analog Blue Input from Channel 1
24
SOGIN1
Analog Input
Sync On Green Input from Channel 1
26
GIN1M
Analog Input
Reference Ground for Analog Green Input from Channel 1
28
GIN1P
Analog Input
Analog Green Input from Channel 1
27
RIN1M
Analog Input
Reference Ground for Analog Red Input from Channel 1
30
RIN1P
Analog Input
Analog Red Input from Channel 1
29
DVI/HDMI Interface
Pin Name
Pin Type
Function
Pin
DVI_R+
Input
DVI/HDMI Input Channel Red +
DVI_R-
Input
DVI/HDMI Input Channel Red -
DVI_G+
Input
DVI/HDMI Input Channel Green +
DVI_G-
Input
DVI/HDMI Input Channel Green -
DVI_B+
Input
DVI/HDMI Input Channel Blue +
DVI_B-
Input
DVI/HDMI Input Channel Blue -
10
DVI_CK+
Input
DVI/HDMI Input Clock +
12
DVI_CK-
Input
DVI/HDMI Input Clock -
13
Video Interface
Pin Name
Pin Type
Function
Pin
VI_CKA
Input w/ 5V-tolerant
Digital Video Input Clock for VI_DATA[23:0]
68
VI_CKB
Digital Video Input Clock for VI_DATA[31:24]
251
VI_DATA[23:0]
Digital Video Input Data[23:0]
55-48, 65, 64,

61-56, 76-69
VI_DATA[31:24] Input
Digital Video Input Data[31:24]
244-241, 237-234
FIELD
FIELD Input
96
DVSYNC
Digital VSYNC Input
95
DHSYNC
Digital HSYNC Input
66
DE
DE Input
67
Digital Audio Interface

Pin Name
Pin Type
Function
Pin
AUMCK
Output
Audio Master Clock Output
228
AUSD
Output
Audio Serial Data Output; 4mA driving strength
229
AUSCK
Output
Audio Serial Clock Output; 4mA driving strength
230
__________________________________________________________________________
70

__________________________________________________________________________________________________________________
MST6181LDA
Pin Name
Pin Type
Function
Pin
AUWS
Output
Word Select Output; 4mA driving strength
231
AUMUTE
Output
Audio Output Mute Control
232
SPDIFO
Output
S/PDIF Audio Output; 4mA driving strength
233
AIMCK
Audio Master Clock Input
247
AISD
Audio Serial Data Input
248
AISCK
Audio Serial Clock Input
249
AIWS
Word Select Input
250
LVDS Interface
Pin Name
Pin Type
Function
Pin
LVA0M
Output
A-Link Negative LVDS Differential Data Output
211
LVA0P
Output
A-Link Positive LVDS Differential Data Output
210
LVA1M
Output
209
LVA1P
Output
208
LVA2M
Output
207
LVA2P
Output
205
LVA3M
Output
201
LVA3P
Output
200
LVACKM
Output
205
LVACKP
Output
204
LVB0M
Output
B-Link Negative LVDS Differential Data Output
227
LVB0P
Output
B-Link Positive LVDS Differential Data Output
226
LVB1M
Output
221
LVB1P
Output
220
LVB2M
Output
219
LVB2P
Output
218
LVB3M
Output
215
LVB3P
Output
214
LVBCKM
Output
217
LVBCKP
Output
216
__________________________________________________________________________
71

__________________________________________________________________________________________________________________
MST6181LDA
GPO Interface
Pin Name
Pin Type
Function
Pin
PWM0
Output
PWM; 4mA driving strength
252
PWM1
Output
253
PWM2
Output
98
PWM3/GPO[7]
Output
GPO with PWM Function; 6mA driving strength
188
PWM4/GPO[8]
Output
189
PWM5/GPO[9]
Output
190
GPO[6:0]
Output
GPO; 6mA driving strength
186-184,
179-176
DRAM Interface
Pin Name
Pin Type
Function
Pin
MVREF
Input
Reference Voltage for DDR SDRAM Interface
124
MCLKE
Output
DRAM Memory Clock Enable
125
MCLKZ
Output
DRAM Memory Clock Complementary / Input
126
(for differential clocks)

MCLK
Output
DRAM Memory Clock
127
RASZ
Output
Row Address Strobe, active low
132
CASZ
Output
Column Address Strobe, active low
135
WEZ
Output
Write Enable, active low
136
DQM[1:0]
Output
Data Mask Byte Enable
121, 153
DQS[3:0]
Output
Data Strobe
101, 120, 154, 173
BADR[1:0]
Output
Memory Bank Address
130, 131
MADR[11:0]
Output
Memory Address
150-147, 144-137
MDATA[31:0]
I/O
Memory Data
102-105, 108-119,
155-158, 161-172
Misc. Interface
Pin Name
Pin Type
Function
Pin
DDCD_DA
I/O w/ 5V-tolerant
HDCP Serial Bus Data / DDC Data of DVI Port; 4mA driving 18
strength
DDCD_CK
HDCP Serial Bus Data / DDC Clock of DVI Port
19
DDCR_CK
DDC Clock for ROM
94
DDCR_DA
I/O w/ 5V-tolerant
DDC Data for ROM
97
For External Bypass Capacitor
192
BYPASS
__________________________________________________________________________
72

__________________________________________________________________________________________________________________
MST6181LDA
Pin Name
Pin Type
Function
Pin
XIN
Crystal Oscillator Input
Xin
255
XOUT
Crystal Oscillator Output Xout
254
Power Pins
Pin Name
Pin Type
Function
Pin
AVDD_DVI
3.3V Power
DVI/HDMI Power
8, 14
AVDD_ADC
3.3V Power
ADC Power
21, 38
AVDD_PLL
3.3V Power
PLL Power
16
AVDD_PLL2
3.3V Power
PLL Power
129
AVDD_APLL
1.8V Power
Audio PLL Power
62
AVDD_MPLL
3.3V Power
PLL Power
256
3.3V Power (SDRAM) /
Memory Interface Power
106, 122, 133, 145, 159,
VDDM
2.5V Power (DDR)

VDDP
3.3V Power
174
Digital Output Power
47, 80, 183, 202, 222,

238
VDDC
1.8V Power
Digital Core Power
77, 99, 151, 180, 213,

225, 246
GND
Ground
Ground
1, 2, 5, 11, 17, 20, 39,

45, 46, 63, 78, 79, 100,
107, 123, 128, 134, 146,
152, 160, 175, 181, 182,
193, 203, 212, 223, 224,
239, 245
No Connects
Pin Name
NC
Pin Type
Function
Pin
No connect. Leave these pins floating.
187, 191, 194-199
__________________________________________________________________________
73

__________________________________________________________________________________________________________________
MST6181LDA
ELECTRICAL SPECIFICATIONS
Analog Interface Characteristics
Parameter
Min
Resolution
Typ
Max
Unit
Bits
DC ACCURACY
Differential Nonlinearity
0.5
Integral Nonlinearity
+1.50/-1.0
No Missing Codes
LSB
LSB
Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum
Maximum
0.5
1.0
V p-p
V p-p
Input Bias Current
uA
Input Full-Scale Matching
1.5
%FS
Brightness Level Adjustment
62
%FS
SWITCHING PERFORMANCE
Maximum Conversion Rate
165
MSPS
Minimum Conversion Rate
12
MSPS
HSYNC Input Frequency
15
200
kHz
PLL Clock Rate
12
165
MHz
PLL Jitter
500
ps p-p
Sampling Phase Tempco
TBD
ps/C
DIGITAL INPUTS
Input Voltage, High (VIH)
2.5
Input Voltage, Low (VIL)
0.8
Input Current, High (IIH)
-1.0
uA
Input Current, Low (IIL)
1.0
uA
Input Capacitance
pF
DIGITAL OUTPUTS
Output Voltage, High (VOH)
VDDP-0.1
Output Voltage, Low (VOL)
0.1
55
Duty Cycle
DCK, /DCK
45
Output Coding
50
Binary
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power
Channel to Channel Matching
250
MHz
0.5%
Full-Scale
Specifications subject to change without notice.
__________________________________________________________________________
74

__________________________________________________________________________________________________________________
MST6181LDA

Parameter
Symbol
Min
3.3V Supply Voltages
VVDD_33
Typ
Max
Units
-0.3
3.6
VVDD_25
-0.3
2.75
VVDD_18
-0.3
1.98
Input Voltage (5V tolerant inputs)
VIN5Vtol
-0.3
5.0
Input Voltage (non 5V tolerant inputs)
VIN
-0.3
VVDD_33
Ambient Operating Temperature
TA
70
Storage Temperature
TSTG
-40
150
Junction Temperature
TJ
150
Thermal Resistance (Junction to Air) Natural

Conversion
JA
18
C/W
Thermal Resistance (Junction to Case) Natural
JC
1.2
C/W
Conversion
Note: Stress above those listed under Absolute Maximum Rating may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or any other conditions outside of those indicated in the
operation sections of this specification is not implied. Exposure to absolute maximum ratings for extended periods may
affect device reliability.
ORDERING GUIDE
Model
DISCLAIMER
Temperature
Package
Package
Range
Description
Option
0C to +70C
LQFP
256
MST6181LDA-LF 0C to +70C
LQFP
256
MST6181LDA
MSTAR SEMICONDUCTOR RESERVES THE

RIGHT
TO
MAKE
CHANGES
WITHOUT
FURTHER NOTICE TO ANY PRODUCTS HEREIN
TO IMPROVE RELIABILITY, FUNCTION OR
DESIGN. NO RESPONSIBILITY IS ASSUMED
BY MSTAR SEMICONDUCTOR ARISING OUT OF
THE APPLICATION OR USER OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER
DOES IT CONVEY ANY LICENSE UNDER ITS
PATENT RIGHTS, NOR THE RIGHTS OF
OTHERS.
Note: Product suffix LF represents lead-free version.
MARKING INFORMATION
MST6181LDA
Part Number
Lot Number
Operation Code A
Operation Code B
Date Code (YYWW)
Electrostatic charges accumulate on both test equipment and human body and can discharge
without detection. MST6181LDA comes with ESD protection circuitry; however, the device may be
permanently damaged when subjected to high energy discharges. The device should be handled
with proper ESD precautions to prevent malfunction and performance degradation.
REVISION HISTORY
Document
Description
Date
MST6181LDA_ds_v01
Initial release
Jul 2005
MST6181LDA_ds_v02
Updated Features / On-Screen OSD Controller
Aug 2005
Updated Register Table
__________________________________________________________________________
75

__________________________________________________________________________________________________________________
MTV512M
8051 Embedded Monitor Controller with 64K Flash ROM
GENERAL DESCRIPTIONS
The MTV512M micro-controller is an 8051 CPU core
embedded device especially tailored for flat panel
display applications. It includes an 8051 CPU core,
768-byte SRAM, 4 channels of 6-bit ADC, 3 external
counters/timers, 6 channels of PWM DAC, VESA
DDC interface, and a 64K-byte internal program
Flash-ROM memory.
FEATURES
8051 core, CPU operating frequency up to 24MHz
3.3V power supply
768-byte RAM; 64K-byte program Flash memory
Maximum 6 channels of PWM DAC
Compliant with VESA DDC1/2B/2Bi/2B+/CI
standard
Watchdog timer with programmable interval

Support external counters/timers, T0, T1, and ET2
Single/double frequency clock output
Two clock output ports
Two external interrupts, INT1 is shared with Slave
IIC interrupt source
Maximum 4 channels of 6-bit ADC
Flash-ROM code protection selection
Hardware ISP (In System Programming), no Boot
Code required
Embedded Dual Ports DDCRAM (128-byte x 2)
40-pin PDIP, 42-pin SDIP, or 44-pin PLCC/QFP
package
Green products like Pb-Free Packages or All
Green Packages available
BLOCK DIAGRAM
P0.0-7
P1.0-7
P2.0-3
P3.0-3.4
8051
CORE
RST
X1
X2
CKO
RD
WR
ALE
INT1
P0.0-7
P2.0-7
RD
WR
ALE
INT1
XFR
AUXRAM &
DDCRAM1 &
DDCRAM2
ADC
AD0-3
PWM DAC
DA0-5
P7.6-7
P6.0-7
P5.0-6
AUX
I/O
DDC & IIC

INTERFACE
HSCL1
HSDA1
HSCL2
HSDA2
**This datasheet is the confidential information of MYSON CENTURY, INC. and is subject to various privileges
against unauthorized disclosure. Recipient shall not disclose this confidential information to any other person,
nor shall one use the confidential information for the purpose of competing with MYSON CENTURY, INC.
__________________________________________________________________________
76

__________________________________________________________________________________________________________________
MTV512M
NC
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
P5.6/HSCL2
P5.7/HSDA2
RST
HSCL1/P3.0/RXD
HSDA1/P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P7.6/CLKO2
P7.7
X2
X1
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
MTV512MS 42-pin SDIP
DA0/P5.0
DA1/P5.1
DA2/P5.2
DA3/P5.3
DA4/P5.4
DA5/P5.5
P5.6/HSCL2
P5.7/HSDA2
RST
HSCL1/P3.0/RXD
HSDA1/P3.1/TXD
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.5/T1
P7.6/CLKO2
P7.7
X2
X1
VSS
MTV512MN 40-pin PDIP
PIN CONNECTION DIAGRAMS
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
VCC
P1.0/ET2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
NC
NC
VSYNC
P6.7
P6.6/CLKO1
P6.5
P6.4
P6.3/AD3
P6.2/AD2
P6.1/AD1
P6.0/AD0
VCC
P1.0/ET2
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
NC
NC
NC
VSYNC
P6.7
P6.6/CLKO1
P6.5
P6.4
P6.3/AD3
P6.2/AD2
P6.1/AD1
P6.4/AD0
__________________________________________________________________________
77

__________________________________________________________________________________________________________________
MTV512M
DA4/P5.4
DA3/P5.3
DA2/P5.2
DA1/P5.1
DA0/P5.0
VCC
NC
P1.0/ET2
P1.1
P1.2
P1.3
44
43
42
41
40
DA5/P5.5
39
P1.4
P5.6/HSCL2
38
P1.5
P5.7/HSDA2
37
P1.6
RST
10
36
P1.7
HSCL1/RXD/P3.0
11
35
NC
34
NC
33
NC
32
VSYNC
MTV512MV
44-pin
PLCC
NC
12
HSDA1/TXD/P3.1
13
P3.2/INT0
14
P3.3/INT1
15
31
P6.7
P3.4/T0
16
30
P6.6/CLKO1
P3.5/T1
17
29
P6.5
23
24
25
26
27
28
NC
P6.0/AD0
P6.1/AD1
P6.2/AD2
P6.3/AD3
P6.4
X2
VSS
P7.7
X1
20
P7.6/CLKO2
21
19
22
18
P1.3
34
39
35
40
36
NC
41
P1.2
DA0/P5.0
42
P1.1
DA1/P5.1
43
37
DA2/P5.2
44
P1.0/ET2
DA3/P5.3
VCC 38
DA4/P5.4
DA5/ P5.5
P5.6/HSCL2
33
P1.4
32
P1.5
P5.7/HSDA2
31
P1.6
RST
30
P1.7
HSCL1/RXD/P3.0
29
NC
NC
28
NC
HSDA1/TXD/P3.1
27
NC
P3.2/INT0
26
VSYNC
P3.3/INT1
25
P6.7
P3.4/T0
10
24
P6.6/CLKO1
P3.5/T1
11
23
P6.5
MTV512MF
44-pin
QFP
15
17
18
19
20
21
22
X1
VSS
NC
P6.0/AD0
P6.2/AD2
P6.1/AD1
P6.3/AD3
P6.4
P7.7
X2
16
14
P7.6/CLKO2
13
12
__________________________________________________________________________
78

__________________________________________________________________________________________________________________
www.fairchildsemi.com
RC1117
1A Adjustable/Fixed Low Dropout Linear Regulator
Features
Description
The RC1117 and RC1117-2.5, -2.85, -3.3 and -5 are low

dropout three-terminal regulators with 1A output current
capability. These devices have been optimized for low voltage
where transient response and minimum input voltage are
critical. The 2.85V version is designed specifically to be
used in Active Terminators for SCSI bus.
Low dropout voltage

Load regulation: 0.05% typical
Trimmed current limit
On-chip thermal limiting
Standard SOT-223, TO-263, and TO-252 packages
Three-terminal adjustable or fixed 2.5V, 2.85V, 3.3V, 5V
Current limit is trimmed to ensure specified output current

and controlled short-circuit current. On-chip thermal limiting
provides protection against any combination of overload and
ambient temperatures that would create excessive junction
temperatures.
Applications
Active SCSI terminators

High efficiency linear regulators
Post regulators for switching supplies
Battery chargers
5V to 3.3V linear regulators
Motherboard clock supplies
Unlike PNP type regulators where up to 10% of the output

current is wasted as quiescent current, the quiescent current
of the RC1117 flows into the load, increasing efficiency.
The RC1117 series regulators are available in the industrystandard SOT-223, TO-263 (D2PAK), and TO-252 (DPAK)
power packages.
Typical Applications
RC1117
VIN = 3.3V
VIN
VOUT
10F
R1
124
ADJ
1.5V at 1A
+
22F
R2
24.9
VOUT = VREF(1 + R2/R1) + IAdj R2
RC1117-2.85
VIN = 5V
VIN
VOUT
10F
2.85V at 1A
+
22F
GND
__________________________________________________________________________
79

__________________________________________________________________________________________________________________
PRODUCT SPECIFICATION
RC1117
Pin Assignments
Tab is
VOUT
Front View
Tab is
VOUT
Tab is
VOUT
IN
OUT
ADJ/GND
ADJ/
GND
OUT
IN
4-Lead Plastic SOT-223

JC = 15C/W*
ADJ/
GND
IN
3-Lead Plastic TO-252

JC = 3C/W*
3-Lead Plastic TO-263

JC = 3C/W*
*With package soldered to 0.5 square inch copper area over backside ground plane or internal power plane., JA can vary from
30C/W to more than 50C/W. Other mounting techniques may provide better thermal resistance than 30C/W.

Parameter
Min.
Max.
7.5
125
-65
150
300
VIN
Operating Junction Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 10 sec.)
Unit
__________________________________________________________________________
80

__________________________________________________________________________________________________________________

www.ti.com
SLOS407D FEBRUARY 2003 REVISED AUGUST 2004

FEATURES
D 12-W/Ch Into an 8- Load From 15-V Supply
D Efficient, Class-D Operation Eliminates
D
D
D
D
D
DESCRIPTION
The TPA3004D2 is a 12-W (per channel) efficient, Class-D
audio amplifier for driving bridged-tied stereo speakers.
The TPA3004D2 can drive stereo speakers as low as 4 .
The high efficiency of the TPA3004D2 eliminates the need
for external heatsinks when playing music.
Heatsinks and Reduces Power Supply

Requirements
32-Step DC Volume Control From 40 dB to
36 dB
Line Outputs For External Headphone
Amplifier With Volume Control
Regulated 5-V Supply Output for Powering
TPA6110A2
Space-Saving, Thermally-Enhanced
PowerPAD Packaging
Thermal and Short-Circuit Protection
Stereo speaker volume is controlled with a dc voltage

applied to the volume control terminal offering a range of
gain from 40 dB to 36 dB. Line outputs, for driving
external headphone amplifier inputs, are also dc voltage
controlled with a range of gain from 56 dB to 20 dB.
An integrated 5-V regulated supply is provided for
powering an external headphone amplifier.
APPLICATIONS
D LCD Monitors and TVs
D Powered Speakers
10 F
Cs
0.1 F
Cs
0.1 F
RINN
RINP
Crinn
Crinp 1 F
1 F
Clinp
LINP
LINN
1 F
C2p5
1 F
Clinn
10 nF
Cbs
RINN
RINP
MODE
V2P5
AVCC
LINP
1 F
MODE_OUT
SYSTEM CONTROL
VAROUTR
RLINE_OUT
VAROUTL
TPA3004D2
AVDDREF
FADE
VREF
AVDD
VARDIFF
VARDIFF
COSC
VARMAX
VARMAX
ROSC
Cs
Cbs
10 nF
PVCC
BSLP
PVCCL
PVCCL
LOUTP
LOUTP
PGNDL
PGNDL
LOUTN
LOUTN
VCLAMPL
PVCCL
AGND
REFGND
PVCCL
VOLUME
BSLN
VOL
Ccpr
VCLAMPR
MODE_OUT
LINN
1 F
BSRP
PVCCR
PVCCR
ROUTN
PGNDR
Cs
PGNDR
PVCCR
SD
ROUTN
BSRN
SYSTEM CONTROL
PVCCR
Cs
PVCC
ROUTP
Cbs
10 F
ROUTP
PVCC
10 nF
AVCC
Cs
0.1 F
Cvcc
10 F
LLINE_OUT
AVDD
Cvdd
Cosc
100 nF
220 pF
SYSTEM CONTROL
Rosc
120 k
Ccpl
1 F
10
k
10
k
Cs
0.1 F
Cs
0.1 F
10 F
10 F
Cbs
Cs
10 nF
PVCC
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
81

__________________________________________________________________________________________________________________
TPA3004D2
www.ti.com
AVAILABLE OPTIONS
TA
PACKAGED DEVICE
48-PIN HTQFP (PHP)(1)
40C to 85C
TPA3004D2PHP
(1) The PHP package is available taped and reeled. To order a taped and
reeled part, add the suffix R to the part number (e.g., TPA3004D2PHPR).
PIN ASSIGNMENTS
PHP PACKAGE
PVCCR
41 40 39 38
37
ROUTP
BSRP
43 42
ROUTP
PGNDR
PGNDR
ROUTN
ROUTN
46 45 44
PVCCR
48 47
PVCCR
PVCCR
BSRN
(TOP VIEW)
SD
36
VCLAMPR
RINN
35
MODE_OUT
RINP
34
MODE
V2P5
33
AVCC
LINP
32
VAROUTR
LINN
31
VAROUTL
AVDDREF
30
FADE
VREF
29
AVDD
VARDIFF
28
COSC
VARMAX
10
27
ROSC
VOLUME
11
26
AGND
REFGND
12
25
VCLAMPL
LOUTP
BSLP
PVCCL
PGNDL
PVCCL
24
LOUTP
20 21 22 23
PGNDL
18 19
LOUTN
15 16 17
LOUTN
PVCCL
BSLN
13 14
PVCCL
TPA3004D2
__________________________________________________________________________
82

__________________________________________________________________________________________________________________
TPA3004D2
www.ti.com
Terminal Functions
TERMINAL
NO.
NAME
I/O
DESCRIPTION
AGND
26
Analog ground for digital/analog cells in core
AVCC
AVDD
33
High-voltage analog power supply (8.5 V to 18 V)
29
5-V Regulated output capable of 100-mA output
AVDDREF
BSLN
5-V Reference outputprovided for connection to adjacent VREF terminal.
13
I/O
Bootstrap I/O for left channel, negative high-side FET
BSLP
24
I/O
Bootstrap I/O for left channel, positive high-side FET
BSRN
48
I/O
Bootstrap I/O for right channel, negative high-side FET
BSRP
37
I/O
Bootstrap I/O for right channel, positive high-side FET
COSC
28
I/O
I/O for charge/discharging currents onto capacitor for ramp generator triangle wave biased at V2P5
FADE
30
Input for controlling volume ramp rate. A logic low on this pin places the amplifier in fade mode. A logic high on
this pin allows a quick transition to the desired volume setting when cycling SD or during power-up.
LINN
Negative differential audio input for left channel
LINP
Positive differential audio input for left channel
LOUTN
16, 17
Class-D 1/2-H-bridge negative output for left channel
LOUTP
20, 21
Class-D 1/2-H-bridge positive output for left channel
MODE
34
Input for MODE control. A logic high on this pin places the amplifier in the variable output mode and the Class-D
outputs are disabled. A logic low on this pin places the amplifier in the Class-D mode and Class-D stereo outputs
are enabled. Variable outputs (VAROUTL and VAROUTR) are still enabled in Class-D mode to be used as
line-level outputs for external amplifiers.
MODE_OUT
35
Output for control of the variable output amplifiers. When the MODE pin (34) is a logic high, the MODE_OUT
pin is driven low. When the MODE pin (34) is a logic low, the MODE_OUT pin is driven high. This pin is intended
for MUTE control of an external headphone amplifier. Leave unconnected when not used for headphone
amplifier control.
PGNDL
18, 19
Power ground for left channel H-bridge
PGNDR
42, 43
Power ground for right channel H-bridge
PVCCL
14, 15
Power supply for left channel H-bridge (tied to pins 22 and 23 internally), not connected to PVCCR or AVCC.
PVCCL
22, 23
Power supply for left channel H-bridge (tied to pins 14 and 15 internally), not connected to PVCCR or AVCC.
PVCCR
38,39
Power supply for right channel H-bridge (tied to pins 46 and 47 internally), not connected to PVCCL or AVCC.
PVCCR
46, 47
Power supply for right channel H-bridge (tied to pins 38 and 39 internally), not connected to PVCCL or AVCC.
REFGND
12
Ground for gain control circuitry. Connect to AGND. If using a DAC to control the volume, connect the DAC
ground to this terminal.
RINP
Positive differential audio input for right channel
RINN
Negative differential audio input for right channel
ROSC
27
I/O
Current setting resistor for ramp generator. Nominally equal to 1/8*VCC
ROUTN
44, 45
Class-D 1/2-H-bridge negative output for right channel
ROUTP
40, 41
Class-D 1/2-H-bridge positive output for right channel
SD
Shutdown signal for IC (low = shutdown, high = operational). TTL logic levels with compliance to VCC.
VARDIFF
DC voltage to set the difference in gain between the Class-D and VAROUT outputs. Connect to GND or
AVDDREF if VAROUT outputs are unconnected.
VARMAX
10
DC voltage that sets the maximum gain for the VAROUT outputs. Connect to GND or AVDDREF if VAROUT
outputs are unconnected.
VAROUTL
31
Variable output for left channel audio. Line level output for driving external HP amplifier.
__________________________________________________________________________
83

__________________________________________________________________________________________________________________
TPA3004D2
www.ti.com
Terminal Functions (Continued)

TERMINAL
NO.
I/O
NAME
DESCRIPTION
VAROUTR
32
Variable output for right channel audio. Line level output for driving external HP amplifier.
VCLAMPL
25
Internally generated voltage supply for left channel bootstrap capacitors.
VCLAMPR
36
Internally generated voltage supply for right channel bootstrap capacitors.
VOLUME
11
DC voltage that sets the gain of the Class-D and VAROUT outputs.
VREF
Analog reference for gain control section.
V2P5
2.5-V Reference for analog cells, as well as reference for unused audio input when using single-ended inputs.
Thermal
Pad
Connect to AGND and PGNDshould be center point for both grounds.
ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range unless otherwise noted(1)
UNIT
Supply voltage range: AVCC, PVCC
0.3 V to 20 V
3.6
Load impedance, RL
MODE, VREF, VARDIFF, VARMAX, VOLUME, FADE
Input voltage range, VI
0 V to 5.5 V
SD
0.3 V to VCC + 0.3 V
RINN, RINP, LINN, LINP

Supply current
AVDD
AVDDREF
Output current
VAROUTL, VAROUTR
0.3 V to 7 V
120 mA
10 mA
20 mA
Continuous total power dissipation
See Dissipation Rating Table
Operating free-air temperature range, TA
40C to 85C
Operating junction temperature range, TJ(2)
40C to 150C
Storage temperature range, Tstg
65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
260C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The TPA3004D2 incorporates an exposed PowerPAD on the underside of the chip. This acts as a heatsink and must be connected to a thermally
dissipating plane for proper power dissipation. Failure to do so may result in exceeding the maximum junction temperature that could permanently
damage the device. See TI Technical Brief SLMA002 for more information about utilizing the PowerPAD thermally enhanced package.
PACKAGE DISSIPATION RATINGS

PACKAGE
PHP
TA 25C
4.3 W
DERATING FACTOR
34.7 mW/C(1)
TA = 70C
2.7 W
TA = 85C
2.2 W
(1) The PowerPAD must be soldered to a thermal land on the printed circuit board. Please refer to the PowerPAD
Thermally Enhanced Package application note (SLMA002
__________________________________________________________________________
84

__________________________________________________________________________________________________________________
TPA6110A2
150-mW STEREO AUDIO POWER AMPLIFIER
SLOS314 DECEMBER 2000
DGN PACKAGE
(TOP VIEW)
150 mW Stereo Output

PC Power Supply Compatible
Fully Specified for 3.3 V and 5 V
Operation
Operation to 2.5 V
Pop Reduction Circuitry
Internal Mid-Rail Generation
Thermal and Short-Circuit Protection
Surface-Mount Packaging
PowerPAD MSOP
Pin Compatible With LM4881
BYPASS
GND
SHUTDOWN
IN2
IN1
VO 1
VDD
VO 2
description
The TPA6110A2 is a stereo audio power amplifier packaged in an 8-pin PowerPAD MSOP package capable
of delivering 150 mW of continuous RMS power per channel into 16- loads. Amplifier gain is externally
configured by means of two resistors per input channel and does not require external compensation for settings
of 1 to 10.
THD+N when driving a 16- load from 5 V is 0.03% at 1 kHz, and less than 1% across the audio band of 20
Hz to 20 kHz. For 32- loads, the THD+N is reduced to less than 0.02% at 1 kHz, and is less than 1% across
the audio band of 20 Hz to 20 kHz. For 10-k loads, the THD+N performance is 0.005% at 1 kHz, and less than
0.5% across the audio band of 20 Hz to 20 kHz.
typical application circuit
325 k
325 k
VDD 6
VDD
C(S)
Rf
VDD/2
Audio
Input
Ri
IN 1
BYPASS
IN 2
Ci
VO1 7
VO2 5
C(C)
C(B)
Audio
Input
Ri
Ci
From Shutdown
Control Circuit
SHUTDOWN
C(C)
Bias
Control
Rf
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
__________________________________________________________________________
85

__________________________________________________________________________________________________________________
TPA6110A2
150-mW STEREO AUDIO POWER AMPLIFIER
SLOS314 DECEMBER 2000
AVAILABLE OPTIONS
TA
PACKAGED DEVICE
MSOP
MSOP
Symbolization
40C to 85C
TPA6110A2DGN
TI AIZ
The DGN package is available in left-ended tape and reel only (e.g.,
TPA6110A2DGNR).
Terminal Functions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
BYPASS
Tap to voltage divider for internal mid-supply bias supply. Connect to a 0.1 F to 1 F low ESR capacitor for
best performance.
GND
GND is the ground connection.
IN1
IN1 is the inverting input for channel 1.
IN2
IN2 is the inverting input for channel 2.
SHUTDOWN
Puts the device in a low quiescent current mode when held high.
VDD
VO1
VDD is the supply voltage terminal.

VO1 is the audio output for channel 1.
VO2
VO2 is the audio output for channel 2.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 V
Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to VDD + 0.3 V
Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . internally limited
Operating junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40C to 150C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65C to 150C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA 25C
POWER RATING
DERATING FACTOR
ABOVE TA = 25C
TA = 70C
POWER RATING
TA = 85C
POWER RATING
DGN
2.14 W
17.1 mW/C
1.37 W
1.11 W
Please see the Texas Instruments document, PowerPAD Thermally Enhanced Package Application Report
(literature number SLMA002), for more information on the PowerPAD package. The thermal data was
measured on a PCB layout based on the information in the section entitled Texas Instruments Recommended
Board for PowerPAD on page 33 of the before mentioned document.
recommended operating conditions

Supply voltage, VDD
Operating free-air temperature, TA
High-level input voltage, VIH, (SHUTDOWN)
MIN
MAX
UNIT
2.5
5.5
40
85
60% x VDD
Low-level input voltage, VIL, (SHUTDOWN)
V
25% x VDD
2 __________________________________________________________________________
86

__________________________________________________________________________________________________________________
Techwell
Mixed Signal Semiconductor Solutions

TECHWELL
VIDEO
DECODERS
NTSC/PAL/SECAM Video Decoder for Multimedia Applications
TW9906
Features
3x10-bit Multi-Standard Comb Filter Video Decoder

with YCbCr Component Input
* Pin to Pin with TW9909
Target Applications
CRT, LCD, PDP and Projection TV
Multifunction LCD Monitor (Monitor TV)
DVD-Recorder
PC TV Capture Card
CCTV Digital Video Recorder
Analog Video Decoder

NTSC (M, 4.43) and PAL (B, D, G, H, I, M, N, N
combination), PAL (60), SECAM support with
automatic format detection
Advanced synchronization processing for VCR
fast forward, backward, and pause mode
Software selectable analog inputs
Up to five composite video inputs
Four composite, one S-video or one YCbCr
input
Two composite, two S-Video or two YCbCr
inputs
Three composite, one S-Video and one YCbCr
inputs
Three 10-bit ADCs with analog clamping circuit
and anti-aliasing filter built in
Fully programmable static gain or automatic
gain control for the Y channel
Programmable white peak control for the Y
channel
Techwell's TW9906 is a high quality NTSC/PAL/SECAM video decoder

that is designed for multimedia applications. It uses the mixed-signal
2.5V/3.3V CMOS technology to provide a low-power integrated solution.
The TW9906 analog front-end is equipped with three separate analog
channels that enable it to accept all three possible analog video signal
standards: composite, S-video or YCbCr component video. All channels
include an analog multiplexer (MUX) for maximum flexibility in software
controlled input selection. It is possible to connect up to five composite
inputs at one time and allow the software to switch between them.
Alternatively several combinations of composite inputs and S-Video
component inputs may be switched under software control. (Four input
channels of any format can be accommodated with but there is a
maximum of 2 S-Video inputs or 2 component inputs.)
The front-end contains all the necessary circuits to simplify the system
design. The built-in three high quality 10-bit analog-to-digital converters
(ADCs) convert inputs into digital signals for processing.
The TW9906 uses proprietary adaptive 4H comb filter for chroma and luma
separation to achieve high video quality. The image enhancement
includes horizontal and vertical peaking, CTI and BCS control.
The advanced synchronization processing can produce stable pictures for
non-standard signal such as those produced by VCR trick mode.
The high quality scaler uses multi-tap poly-phase decimation filter to
accurately scale down the image with minimum phase error. It can be
programmed to scale-down the output picture to an arbitrary ratio with
cropping.
The TW9906 supports flexible pixel interface. It outputs YCbCr (4:2:2) data
stream over 10-bit or 20-bit data path. It also supports both free-running
clock and line-locked clock output.
A 2-wire serial MPU interface is used to simplify system integration. All the
functions can be controlled through this interface.
Techwell
www.techwellinc.com
__________________________________________________________________________
87

__________________________________________________________________________________________________________________
NTSC/PAL/SECAM Video Decoder for Multimedia Applications
TW9906
3x10-bit Multi-Standard Comb Filter Video Decoder
with YCbCr Component Input
* Pin to Pin with TW9909
H/V Down
Scaler/Cropping
Filter
Filter
Luma/Chroma
processor
10-bit
ADC
10-bit
ADC
Chroma
Demodulation
Clamp
Anti-alias
Filter
Clamp
CIN (1)
MUX
Video Processing
VBI Pass
through
MPOUT
VSYNC
HSYNC
FIELD
DVALID
CLKX2
CLKX1
PDN
INTREQ
2 Wire
Serial
Bus
VBI Slicer
VBI FIFO
AMXCLK
Audio Clock
SIAD0
SCLK
SDAT
VD(19:0)
Video output Interface
4-H adaptive
comb filter
Y/C separation
Filter
10-bit
ADC
Line-lock
clock
Generator
27 Mhz
Clock
Sync
MUX3
MUX
MUX0
AGC/Cla
Y
YBOUT
Anti-alias
Filter
Analog Video In
CIN (0)
Anti-alias
Filter
VIN (0)
VIN (1)/MUX4
MUX
TW9906 Block Diagram
Adaptive 4H comb filter for the best image

quality
PAL delay line for color phase error correction
Digital sub-carrier PLL for accurate color
decoding
Digital Horizontal PLL and advanced
synchronization processing for non-standard
video signals
Programmable hue, brightness, saturation,
contrast, and sharpness
Blue stretch
Image enhancement with 2D peaking and CTI.
Automatic color control and color killer
IF compensation filter
Detection of level of copy protection
according to Macrovision standard
YCbCr input supports 480i/576i and subsampled 480p/576p with auto-detection.
AMCLK
ASCLK
ALRCLK
Miscellaneous
Video Output
Supports both free-running and line-locked clock outputs
Programmable output cropping
High quality horizontal filtered scaling with arbitrary scale down
ratio
VMI 1.4 compatible 10-bit or 20-bit pixel interface
ITU-R 601 or ITU-R 656 compatible output YCbCr(4:2:2) output
format
VBI slicer supporting industrial standard data services with data
packet filter capability
Built-in VBI FIFO for convenient access through host interface
VBI data pass through, raw ADC data for Intercast
Field locked audio clock generator
Two wire MPU serial bus interface

Power-down mode
Typical power consumption 0.25W
Single 27MHz crystal for all standards
Supports 24.54MHz and 29.5MHz crystal
for high quality square pixel format
3.3V / 5V tolerant I/O
2.5V / 3.3V Power Supply
80 pin TQPF package
About Techwell
Techwell designs and sells mixed signal semiconductor solutions for digital video applications.The company's products enable the
conversion of analog video sources to digital form and facilitate the display, storage and transport of digital video, HDTV, and personal
computer display information. Headquartered in San Jose, CA, Techwell currently has over 50 employees in the U.S., Korea, and Taiwan.
Techwell
For more information on Techwell, please contact us at 1-408-435-3888

2005 Techwell Inc. All rights reserved.
All other trademarks are property of their respective owners
TECHWELL INC.
TEL 1-408-435-3888 www.techwellinc.com
__________________________________________________________________________
88

__________________________________________________________________________________________________________________
VCT 49xyI, VCT 48xyI
ADVANCE INFORMATION
Volume 1: General Description

General Description
1.1. Features
Release Note: This data sheet describes functions

and characteristics of the VCT 49xyI, VCT 48xyIC4.
The VCT 49xyI, VCT 48xyI family offers a rich feature

set, covering the whole range of state-of-the-art 50/60Hz TV applications.
PSSDIP88-1/-2 package
1. Introduction
PMQFP144-2 package
Submicron CMOS technology
The VCT 49xyI, VCT 48xyI is an IC family of high-quality single-chip TV processors. Modular design and
deep-submicron technology allow the economic integration of features in all classes of single-scan TV
sets. The VCT 49xyI, VCT 48xyI family is based on
functional blocks contained and approved in existing
products like DRX 396xA, MSP 34x5G, VSP 94x7B,
DDP 3315C, and SDA 55xx.
Low-power standby mode

Single 20.25 MHz reference crystal
8-bit 8051 instruction set compatible CPU
Up to 256 kB on-chip program ROM
WST, PDC, VPS, and WSS acquisition
Closed Caption and V-chip acquisition
Each member of the family contains the entire IF,

audio, video, display, and deflection processing for 4:3
and 16:9 50/60-Hz mono and stereo TV sets. The integrated microcontroller is supported by a powerful OSD
generator with integrated Teletext & CC acquisition
including on-chip page memory.
Up to 10 pages on-chip teletext memory

Multi-standard QSS IF processing with single SAW
FM Radio and RDS with standard TV tuner
TV-sound demodulation:
all A2 standards
all NICAM standards
BTSC/SAP with MNR (DBX optional)
EIA-J
Video & Sound IF

DRX 396xA
Baseband sound processing for loudspeaker channel:

volume and balance
bass/treble or equalizer
loudness and spatial effect (e.g. pseudo stereo)
Micronas AROUND (virtual Dolby optional)
Micronas BASS
further optional and licence requiring sound
enhancements as BBE, SRS Wow and Micronas
VOICE
Audio Processing
MSP 34x5G
Video Processing
VSP 94x7B
VCT 49xyI
Display & Deflection

DDP 3315C
CVBS, S-VHS, YCrCb and RGB inputs

4H adaptive comb filter (PAL/NTSC)
multi-standard color decoder (PAL/NTSC/SECAM)
Nonlinear horizontal scaling panorama vision
Control, OSD, Text

SDA 55xx
Luma and chroma transient improvement (LTI, CTI)

Non-linear color space enhancement (NCE)
Fig. 11: Single-chip VCT 49xyI, VCT 48xyI
Dynamic black level expander (BLE)

Scan velocity modulation output
Soft start/stop of H-drive
Vertical angle and bow correction
Average and peak beam current limiter
Nonlinear and dynamic EHT compensation
Black switch off procedure (BSO)
89

__________________________________________________________________________________________________________________
ADVANCE INFORMATION
IFIN+
IFIN-
IF
Frontend
IF
Processor
Sound
Demodulator
SPEAKER
AOUT
AIN
SIF
TAGC
1.2. Chip Architecture
Audio
Processor
PROT
HOUT
HFLB
CVBS in
YCrCb in
RGB in
Video
Frontend
CVBS out
Comb
Filter
VERT
Color
Decoder
Panorama
Scaler
Component
Interface
Display &
Deflection
Processor
Video
Backend
EW
SVM
RGB out
RGB in
SENSE
RSW
Slicer
Bus
Arbiter
Display
Generator
24kB
Char ROM
20kB XRAM
CPU
8051
256kB
Prog ROM
Memory
Interface
ADB, DB, PSENQ,

PSWEQ, WRQ, RDQ
I2C Master/
Slave
Timer
CRT
PWM
ADC
UART
Watchdog
RTC
I/O-Ports
I2C
Reset & Test

Logic
Clock
Generator
RESETQ
TEST
XTAL1
XTAL2
Pxy
Fig. 12: Block diagram of the VCT 49xyI, VCT 48xyI
__________________________________________________________________________
90

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

4.2. Pin Connections and Short Descriptions
NC = not connected
LV = if not used, leave vacant
OBL = obligatory; connect as described in circuit diagram
IN = Input Pin
OUT = Output Pin
SUPPLY = Supply Pin
Type
Connection
Short Description
88
128
GND
SUPPLY
OBL
Ground Platform
87
129
VSUP5.0BE
SUPPLY
OBL
Supply Voltage Analog Video Back-end, 5.0 V
86
130
TEST
IN
GND
Test Input, reserved for Test
85
131
VERT+
OUT
GND
Differential Vertical Sawtooth Output
84
132
VERT-
OUT
GND
Differential Vertical Sawtooth Output
83
133
EW
OUT
GND
Vertical Parabola Output
82
134
RSW2
OUT
LV
Range Switch 2 Output
81
135
RSW1
OUT
LV
Range Switch 1 Output
80
136
SENSE
IN
GND
Sense ADC Input
10
79
137
GNDM
IN
GND
Reference Ground for Sense ADC
11
78
138
FBIN
IN
GND
Fast Blank Input, Back-end
12
77
139
RIN
IN
GND
Analog Red Input, Back-end
13
76
140
GIN
IN
GND
Analog Green Input, Back-end
14
75
141
BIN
IN
GND
Analog Blue Input, Back-end
15
74
142
SVMOUT
OUT
VSUP5.0BE
Scan Velocity Modulation Output
16
73
143
ROUT
OUT
VSUP5.0BE
Analog Red Output
17
72
144
GOUT
OUT
VSUP5.0BE
Analog Green Output
18
71
BOUT
OUT
VSUP5.0BE
Analog Blue Output
19
70
VRD
OBL
Reference Voltage for RGB DACs
20
69
XREF
OBL
Reference Current for RGB DACs
21
68
VSUP3.3BE
SUPPLY
OBL
Supply Voltage Analog Video Back-end, 3.3 V
22
67
GND
SUPPLY
OBL
Ground Platform
23
66
GND
SUPPLY
OBL
Ground Platform
24
65
VSUP3.3IO
SUPPLY
OBL
Supply Voltage I/O Ports, 3.3 V

(main and standby supply)
25
64
VSUP3.3DAC SUPPLY
OBL
Supply Voltage Video DACs, 3.3 V
26
63
GNDDAC
OBL
Ground Video DACs
PSSDIP88-1
PMQFP144-2
Pin Name
PSSDIP88-2
Pin No.
(If not used)
SUPPLY
__________________________________________________________________________
91

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

Connection
Short Description
PMQFP144-2
Type
PSSDIP88-2
Pin Name
PSSDIP88-1
Pin No.
27
62
10
SAFETY
IN
GND
Safety Input
28
61
11
HFLB
IN
HOUT
Horizontal Flyback Input
29
60
12
HOUT
OUT
LV
Horizontal Drive Output
30
59
13
VPROT
IN
GND
Vertical Protection Input
37
PWMV
OUT
LV
PWM Vertical Output
38
DFVBL
OUT
LV
Dynamic Focus Vertical Blanking Output
(If not used)
31
58
39
SDA
IN/OUT
OBL
I2C Bus Data Input/Output
32
57
40
SCL
IN/OUT
OBL
I2C Bus Clock Input/Output
33
56
41
P21
IN/OUT
LV
Port 2, Bit 1 Input/Output
34
55
42
P20
IN/OUT
LV
35
54
43
P17
IN/OUT
LV
36
53
44
P16
IN/OUT
LV
37
52
45
P15
IN/OUT
LV
38
51
46
P14
IN/OUT
LV
39
50
47
P13
IN/OUT
LV
40
49
48
P12
IN/OUT
LV
41
48
49
P11
IN/OUT
LV
42
47
50
P10
IN/OUT
LV
43
46
53
VSUP3.3FE
SUPPLY
OBL
Supply Voltage Analog Video Front-end, 3.3 V

44
45
54
GND
SUPPLY
OBL
Ground Platform
45
44
55
GND
SUPPLY
OBL
Ground Platform
46
43
56
VSUP1.8FE
SUPPLY
OBL
Supply Voltage Analog Video Front-end, 1.8 V

47
42
57
VOUT3
OUT
LV
Analog Video 3 Output
48
41
58
VOUT2
OUT
LV
49
40
59
VOUT1
OUT
LV
50
39
60
VIN1
IN
GND
Analog Video 1 Input
51
38
61
VIN2
IN
GND
52
37
62
VIN3
IN
GND
53
36
63
VIN4
IN
GND
54
35
64
VIN5
IN
GND
55
34
65
VIN6
IN
GND
56
33
66
VIN7
IN
GND
92

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

Connection
Short Description
PMQFP144-2
Type
PSSDIP88-2
Pin Name
PSSDIP88-1
Pin No.
57
32
67
VIN8
IN
GND
58
31
68
VIN9
IN
GND
59
30
69
VIN10
IN
GND
60
29
70
VIN11
IN
GND
61
28
98
P23
IN/OUT
LV
62
27
99
P22
IN/OUT
LV
63
26
100
XTAL2
OUT
OBL
Analog Crystal Output
64
25
101
XTAL1
IN
OBL
Analog Crystal Input
65
24
102
VSUP1.8DIG
SUPPLY
OBL
Supply Voltage Digital Core, 1.8 V

66
23
103
GND
SUPPLY
OBL
Ground Platform
67
22
104
GND
SUPPLY
OBL
Ground Platform
68
21
105
VSUP3.3DIG
SUPPLY
OBL
Supply Voltage Digital Core, 3.3 V
69
20
106
VSUP5.0IF
SUPPLY
OBL
Supply Voltage IF ADC, 5.0 V
70
19
107
VSUP5.0FE
SUPPLY
OBL
Supply Voltage Analog IF Front-end, 5.0 V
71
18
108
RESETQ
IN/OUT
OBL
Reset Input/Output
72
17
109
IFIN+
IN
VREFIF
Differential IF Input
73
16
110
IFIN-
IN
VREFIF
Differential IF Input
74
15
111
VREFIF
OBL
Reference Voltage, IF ADC
75
14
112
TAGC
OUT
LV
Tuner AGC Output
76
13
113
AIN1R /
SIF
IN/OUT
GND
Analog Audio 1 Input, Right

Analog 2nd Sound IF Output
77
12
114
AIN1L
IN
GND
Analog Audio 1 Input, Left
78
11
115
AIN2R
IN
GND
79
10
116
AIN2L
IN
GND
117
AIN3R
IN
GND
118
AIN3L
IN
GND
119
AOUT2R
OUT
LV
Analog Audio 2 Output, Right
120
AOUT2L
OUT
LV
Analog Audio 2 Output, Left
(If not used)
80
AIN3R /
AOUT2R
IN /
OUT
LV

81
AIN3L /
AOUT2L
IN /
OUT
LV

82
121
AOUT1R
OUT
LV
83
122
AOUT1L
OUT
LV
93

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

Pin Name
Type
PMQFP144-2
PSSDIP88-2
PSSDIP88-1
Pin No.
Connection
Short Description
(If not used)
84
123
SPEAKERR
OUT
LV
Analog Loudspeaker Output, Right
85
124
SPEAKERL
OUT
LV
Analog Loudspeaker Output, Left
86
125
VREFAU
OBL
Reference Voltage, Audio
87
126
VSUP8.0AU
SUPPLY
OBL
Supply Voltage Analog Audio, 8.0 V
88
127
GND
SUPPLY
OBL
Ground Platform
71
P37 /
656IO7
IN/OUT
LV

Digital 656 Bus 7 Input/Output
72
P36 /
656IO6
IN/OUT
LV

73
P35 /
656IO5
IN/OUT
LV

74
P34 /
656IO4
IN/OUT
LV

75
P33 /
656IO3
IN/OUT
LV

76
GNDEIO
SUPPLY
OBL
Ground Extended I/O Ports
77
VSUP3.3EIO
SUPPLY
OBL
Supply Voltage Extended I/O Ports, 3.3 V
78
P32 /
656IO2
IN/OUT
LV

79
P31 /
656IO1
IN/OUT
LV

80
P30 /
656IO0
IN/OUT
LV

81
P26 /
656VIO
IN/OUT
LV

Digital 656 Vsync Input/Output
82
P25 /
656HIO
IN/OUT
LV

Digital 656 Hsync Input/Output
83
P24 /
656CLKIO
IN/OUT
LV

Digital 656 Clock Input/Output
31
ADB19
OUT
LV
Address Bus 19 Output
21
ADB18
OUT
LV
19
ADB17
OUT
LV
22
ADB16
OUT
LV
23
ADB15
OUT
LV
18
ADB14
OUT
LV
17
ADB13
OUT
LV
26
ADB12
OUT
LV
94

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

Pin Name
Type
PMQFP144-2
PSSDIP88-2
PSSDIP88-1
Pin No.
Connection
Short Description
(If not used)
14
ADB11
OUT
LV
96
ADB10
OUT
LV
15
ADB9
OUT
LV
16
ADB8
OUT
LV
27
ADB7
OUT
LV
28
ADB6
OUT
LV
29
ADB5
OUT
LV
30
ADB4
OUT
LV
84
ADB3
OUT
LV
85
ADB2
OUT
LV
86
ADB1
OUT
LV
87
ADB0
OUT
LV
88
DB0
IN/OUT
LV
Data Bus 0 Input/Output
89
DB1
IN/OUT
LV
90
DB2
IN/OUT
LV
91
DB3
IN/OUT
LV
92
DB4
IN/OUT
LV
93
DB5
IN/OUT
LV
94
DB6
IN/OUT
LV
95
DB7
IN/OUT
LV
32
RDQ
OUT
LV
Data Read Enable Output
33
WRQ
OUT
LV
Data Write Enable Output
34
OCF
OUT
LV
Opcode Fetch Output
35
ALE
OUT
LV
Address Latch Enable Output
36
RSTQ
OUT
LV
Internal CPU Reset Output
97
PSENQ
OUT
LV
Program Store Enable Output
20
PSWEQ
OUT
LV
Program Store Write Enable Output
51
XROMQ
IN
OBL
External ROM Enable Input
52
EXTIFQ
IN
LV
Enable External Interface Input
24
STOPQ
IN
LV
Stop CPU Input
25
ENEQ
IN
LV
Enable Emulation Input
95

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

4.3. Pin Descriptions
lines to the power supply. Decoupling capacitors from

VSUPxx to GND have to be placed as closely as possible to these pins. It is recommended to use more
than one capacitor. By choosing different values, the
frequency range of active decoupling can be extended.
4.3.1. Supply Pins

VSUP1.8DIG Supply Voltage 1.8 V
This pin is main and standby supply for the digital core
logic of controller, video, display and deflection processing.
4.3.2. IF Pins
VSUP1.8FE Supply Voltage 1.8 V

This pin is main and standby supply for the analog
video front-end.
VREFIF Reference Voltage for analog IF (Fig. 46)

This pin must be connected to GND via a circuitry
according to the application circuit. Low inductance
caps are necessary.

This pin is main and standby supply for the analog
video front-end.
IFIN+, IFIN- Balanced IF Input (Fig. 44)

These pins must be connected to the SAW filter output. The SAW filter has to be placed as close as possible. The layout of the IF input should be symmetrical
with respect to GND.
VSUP3.3IO Supply Voltage 3.3 V

This pin is main and standby supply for the digital I/Oports.
SIF 2nd Sound IF Output (Fig. 47)

Output level is set via I2C-Bus. An appropriate sound
processor (e.g. MSP) can be connected to this pin.
This pin is also configurable as audio input (see
Fig. 48).
VSUP3.3DIG Supply Voltage 3.3 V

This pin is main supply for the digital core logic of IF
and audio processing and digital video back-end.
VSUP3.3BE Supply Voltage 3.3 V
This pin is main supply for the analog video back-end.
This pin is main supply for the analog IF front-end.
TAGC Tuner AGC Output (Fig. 45)

This pin controls the delayed tuner AGC. As it is a
noise-shaped-I-DAC output, it has to be connected
according to the application circuit.
VSUP5.0IF Supply Voltage 5.0 V

This pin is main supply for the IF ADC.
4.3.3. Audio Pins
VSUP5.0BE Supply Voltage 5.0 V

This pin is main supply for the analog video back-end.
VREFAU Reference Voltage for Analog Audio (Fig.

412)
This pin serves as the internal ground connection for
the analog audio circuitry. It must be connected to the
GND pin with a 3.3 F and a 100 nF capacitor in parallel. This pins shows a DC level of typically 3.77 V.
VSUP8.0AU Supply Voltage 8.0 V

This pin is main supply for the analog audio processing.
GND Ground Platform
This pin is main ground for all above supplies.
AIN1 L Audio 1 Inputs (Fig. 48)

The analog input signal for audio 1 is fed to this pin.
Analog input connection must be AC coupled.
VSUP3.3DAC Supply Voltage 3.3 V

This pin is main supply for the video DACs.
AIN1 R Audio 1 Inputs (Fig. 48)

Analog input connection must be AC coupled. This pin
is also configurable as sound IF output (see Fig. 47).
GNDDAC Ground for 3.3 V Video DAC Supply

VSUP3.3EIO Supply Voltage 3.3 V
This pin is main and standby supply for the extended
digital I/O-ports available in QFP package only. It is
internally connected to VSUP3.3IO.
AIN2 R/L Audio 2 Inputs (Fig. 48)

GNDEIO Ground for 3.3 V Extended I/O Supply

It is internally connected to GND.
AIN3 R/L Audio 3 Inputs (Fig. 48)

Application Note:
All GND pins must be connected to a low-resistive
ground plane underneath the IC. All supply pins must
be connected separately with short and low-resistive
96

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

XREF DAC Current Reference (Fig. 418)
External reference resistor for DAC output currents,
typical 10 k to adjust the output current of the D/A
converters. (see recommended operating conditions).
This resistor has to be connected to ground as closely
as possible to the pin.
AOUT1 R/L Audio 1 Outputs (Fig. 49)

Output of the analog audio 1 signal. Connections to
these pins are intended to be AC coupled.
AOUT2 R/L Audio 2 Outputs (Fig. 49)
Output of the analog audio 2 signal. Connections to
these pins are intended to be AC coupled.
SPEAKER R/L Loudspeaker Outputs (Fig. 411)
Output of the loudspeaker signal. A 1 nF capacitor to
GND must be connected to these pins. Connections to
these pins are intended to be AC-coupled.
4.3.5. CRT Pins

HOUT Horizontal Drive Output (Fig. 419)
This open source output supplies the drive pulse for
the horizontal output stage. An external pulldown
resistor has to be used. The polarity and gating with
the flyback pulse are selectable by software.
4.3.4. Video Pins

VIN 111 Analog Video Input (Fig. 413)
These are the analog video inputs. A CVBS, S-VHS,
YCrCb or RGB/FB signal is converted using the luma,
chroma and component AD converters. The input signals must be AC-coupled by 100nF. In case of an analog fast blank signal carrying alpha blending information
the input signal must be DC-coupled.
HFLB Horizontal Flyback Input (Fig. 420)

Via this pin the horizontal flyback pulse is supplied to
the VCT 49xyI, VCT 48xyI.
VPROT Vertical Protection Input (Fig. 420)
The vertical protection circuitry prevents the picture
tube from burn-in in the event of a malfunction of the
vertical deflection stage. If the peak-to-peak value of
the sawtooth signal from the vertical deflection stage is
too small, the RGB output signals are blanked.
VOUT 1-3 Analog Video Output (Fig. 414)

The analog video inputs that are selected by the video
source select matrix are output at these pins.
SAFETY Safety Input (Fig. 420)

This input has two thresholds. A signal between the
lower and upper threshold means normal function. A
signal below the lower threshold or above the upper
threshold is detected as malfunction and the RGB signals will be blanked.
RIN, GIN, BIN Analog RGB Input (Fig. 415)

These pins are used to insert an external analog RGB
signal, e.g. from a SCART connector which can be
switched to the analog RGB outputs with the fast blank
signal. Separate brightness and contrast settings for
the external analog signals are provided.
VERT+, VERT Vertical Sawtooth Output (Fig. 421)

These pins supply the symmetrical drive signal for the
vertical output stage. The drive signal is generated
with 15-bit precision. The analog voltage is generated
by a 4 bit current-DAC with an external resistor of
6.8 k and uses digital noise shaping.
FBIN Fast Blank Input (Fig. 416)

This pin is used to switch the RGB outputs to the external analog RGB inputs. The active level (low or high)
can be selected by software.
ROUT, GOUT, BOUT Analog RGB Output (Fig. 4
17)
These pins are the analog Red/Green/Blue outputs of
the back-end. The outputs are current sinks.
EW East-West Parabola Output (Fig. 422)

This pin supplies the parabola signal for the East-West
correction. The drive signal is generated with 15 bit
precision. The analog voltage is generated by a 4 bit
current-DAC with an external resistor of 6.8 k and
uses digital noise shaping.
SVMOUT Scan Velocity Modulation Output (Fig. 4

17)
This output delivers the analog SVM signal. The D/A
converter is a current sink like the RGB D/A converters. At zero signal the output current is 50% of the
maximum output current.
PWMV PWM Vertical Output (Fig. 419)

This pin provides an adjustable vertical parabola with 7
bit resolution and approx. 79.4 kHz PWM frequency.
DFVBL Dynamic Focus Vertical Blanking (Fig. 419)
This pin supplies the blank pulse for dynamic focus
during vertical blanking period or a free programmable
horizontal pulse for horizontal dynamic focus generation. Alternatively it can be programmed as FIELD output, delivering even/odd field information.
VRD DAC Reference Decoupling (Fig. 418)

Via this pin the RGB-DAC reference voltage is decoupled by an external capacitor. The DAC output currents
depend on this voltage, therefore a pulldown transistor
can be used to shut off all beam currents. A decoupling
capacitor of 4.7 F in parallel to 100 nF (low inductance) is required.
97

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

SENSE Measurement ADC Input (Fig. 425)
This is the input of the analog to digital converter for
the picture and tube measurement. Three measurement ranges are selectable with RSW1 and RSW2.
ADB0ADB19 Address Bus Output (Fig. 433)

These 20 lines provide the CPU address bus output to
access external memory.
DB0DB7 Data Bus Input/Output (Fig. 434)
These 8 lines provide the bidirectional CPU data bus
to access external memory.
GNDM Measurement ADC Reference Input

This is the reference ground for the measurement A/D
converter. Connect this pin to GND.
WRQ Data Write Enable Output (Fig. 433)

This pin controls the direction of data exchange
between the CPU and the external data memory
device (SRAM).
RSW1 Range Switch1 for Measuring ADC (Fig. 4

23)
These pin is an open drain pull-down output. During
cutoff and white drive measurement the switch is off.
During the rest of time it is on. The RSW1 pin can be
used as second measurement ADC input for picture
beam current measurement.
RDQ Data Read Enable Output (Fig. 433)

This pin is used to enable the output driver of the
external data memory device (SRAM) for read access.
PSENQ Program Store Enable Output (Fig. 433)
This pin is used to enable the output driver of the
external program memory device (ROM/FLASH) for
read access.
RSW2 Range Switch2 for Measuring ADC (Fig. 4

24)
These pin is an open drain pull-down output. During
cutoff measurement the switch is off. During white
drive measurement the switch is on. Also during the
rest of time it is on. It is used to set the range for white
drive current measurement.
PSWEQ Program Store Write Enable Output (Fig. 4

33)
This pin is used to write into the external program flash
memory device.
4.3.6. Controller Pins
XROMQ External ROM Enable Input (Fig. 435)

This pin must be pulled low to access the external program memory. XROMQ has an internal pull-up resistor.
XTAL1 Crystal Input and XTAL2 Crystal Output (Fig.

426)
These pins connect a 20.25 MHz crystal to the internal
oscillator. An external clock can be fed into XTAL2.
EXTIFQ Enable External Memory Interface Input

(Fig. 435)
This pin must be pulled low to enable the external
memory interface. EXTIFQ has an internal pull-up
resistor.
RESETQ Reset Input/Output (Fig. 427)

A low level on this pin resets the VCT 49xyI, VCT
48xyI. The internal CPU can pull down this pin to reset
external devices connected to this pin.
STOPQ Stop CPU Input (Fig. 435)

Applying a low level during the input phase freezes the
real-time relevant internal peripherals such as timers
and interrupt controller. STOPQ has an internal pull-up
resistor.
TEST Test Input (Fig. 428)

This pin enables factory test modes. For normal operation, it must be connected to ground.
SCL I2C Bus Clock (Fig. 429)
This pin delivers the I2C bus clock line. The signal can
be pulled down by external slave ICs to slow down
data transfer.
ENEQ Enable Emulation Input (Fig. 435)

Only if this pin is set to low level, STOPQ and OCF are
operational. ENEQ has an internal pull-up resistor.
SDA I2C Bus Data (Fig. 429)

This pin delivers the I2C bus data line.
ALE Address Latch Enable Output (Fig. 433)

This signal indicates changes on the address bus.
P10P13, P20P23 I/O Port (Fig. 430)

These pins provide CPU controlled I/O ports.
OCF Opcode Fetch Output (Fig. 433)

A high level driven by the CPU during output phase
indicates the beginning of a new instruction.
P14P17 I/O Port (Fig. 431)

These pins provide CPU controlled I/O ports. Additionally they can be used as analog inputs for the controller ADC.
RSTQ Internal CPU Reset Input/Output (Fig. 436)

This pin is used for emulation purpose only. A low level
on this pin resets the CPU. It also indicates an internal
reset of the CPU. RSTQ has an internal pull-up resistor.
P24P26, P30P37 I/O Port (Fig. 432)

These pins provide CPU controlled I/O ports.
98

__________________________________________________________________________________________________________________
ADVANCE INFORMATION

4.4. Pin Configuration
44
46
43
47
42
48
41
49
40
50
39
51
38
52
37
53
36
54
35
55
34
56
33
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
81
82
83
84
85
86
87
88
GND
VSUP3.3FE
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
SCL
SDA
VPROT
HOUT
HFLB
SAFETY
GNDDAC
VSUP3.3DAC
VSUP3.3IO
GND
GND
VSUP3.3BE
XREF
VRD
BOUT
GOUT
ROUT
SVMOUT
BIN
GIN
RIN
FBIN
GNDM
SENSE
RSW1
RSW2
EW
VERTVERT+
TEST
VSUP5.0BE
GND
Fig. 41: PSSDIP88-1 package
GND
VSUP3.3FE
P10
P11
45
44
46
43
47
42
48
41
P12
P13
P14
P15
P16
P17
P20
P21
SCL
SDA
VPROT
HOUT
HFLB
SAFETY
GNDDAC
VSUP3.3DAC
VSUP3.3IO
GND
GND
VSUP3.3BE
XREF
VRD
BOUT
GOUT
ROUT
SVMOUT
BIN
GIN
RIN
FBIN
GNDM
SENSE
RSW1
RSW2
EW
VERTVERT+
TEST
VSUP5.0BE
GND
49
40
50
39
51
38
52
37
53
36
54
35
55
34
56
33
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
VCT 49xyI PZ
45
VCT 49xyI PY
GND
VSUP1.8FE
VOUT3
VOUT2
VOUT1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
P23
P22
XTAL2
XTAL1
VSUP1.8DIG
GND
GND
VSUP3.3DIG
VSUP5.0IF
VSUP5.0FE
RESETQ
IFIN+
IFINVREFIF
TAGC
SIF / AIN1R
AIN1L
AIN2R
AIN2L
AIN3R / AOUT2R
AIN3L / AOUT2L
AOUT1R
AOUT1L
SPEAKERR
SPEAKERL
VREFAU
VSUP8.0AU
GND
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
80
81
82
83
84
85
86
87
88
GND
VSUP1.8FE
VOUT3
VOUT2
VOUT1
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
VIN9
VIN10
VIN11
P23
P22
XTAL2
XTAL1
VSUP1.8DIG
GND
GND
VSUP3.3DIG
VSUP5.0IF
VSUP5.0FE
RESETQ
IFIN+
IFINVREFIF
TAGC
SIF / AIN1R
AIN1L
AIN2R
AIN2L
AIN3R / AOUT2R
AIN3L / AOUT2L
AOUT1R
AOUT1L
SPEAKERR
SPEAKERL
VREFAU
VSUP8.0AU
GND
Fig. 42: PSSDIP88-2 package (pinning mirrored)
99

__________________________________________________________________________________________________________________
ADVANCE INFORMATION
P34 / 656IO4
P35 / 656IO5
74
73
GNDEIO
P33 / 656IO3
75
76
77
P31 / 656IO1
P32 / 656IO2
VSUP3.3EIO
78
80
79
81
82
ADB3
P24 / 656CLKIO
P25 / 656HIO
P26 / 656VIO
P30 / 656IO0
84
83
86
85
88
87
89
DB3
DB2
DB1
DB0
ADB0
ADB1
ADB2
90
91
DB5
DB4
92
93
94
ADB10
DB7
DB6
96
XTAL1
XTAL2
101
95
VSUP1.8DIG
102
P23
PSENQ
GND
103
97
GND
104
P22
VSUP3.3DIG
105
98
VSUP5.0IF
106
99
VSUP5.0FE
107
100
RESETQ
108
IFIN+
109
72
IFINVREFIF
TAGC
110
71
111
70
112
69
AIN1R / SIF
AIN1L
113
68
114
67
AIN2R
115
66
AIN2L
116
65
AIN3R
AIN3L
AOUT2R
117
64
118
63
119
62
AOUT2L
AOUT1R
120
61
121
60
AOUT1L
SPEAKERR
122
59
123
58
SPEAKERL
VREFAU
124
57
125
56
VSUP8.0AU
126
GND
GND
127
VSUP5.0BE
TEST
VERT+
129
52
130
51
131
50
VERT-
132
49
EXTIFQ
XROMQ
P10
P11
EW
133
48
P12
RSW2
134
47
P13
RSW1
135
46
P14
SENSE
GNDM
136
45
P15
137
44
P16
FBIN
138
43
P17
RIN
139
42
P20
GIN
140
41
P21
BIN
141
40
SCL
SVMOUT
142
39
SDA
ROUT
143
38
DFVBL / FIELD
GOUT
144
37
PWMV
36
34
OCF
ALE
RSTQ
35
33
32
WRQ
31
30
ADB4
ADB19
RDQ
29
27
28
25
ENEQ
ADB12
ADB7
ADB6
ADB5
26
24
13
VPROT
ADB11
ADB9
ADB8
23
12
HOUT
STOPQ
100
22
11
Fig. 43: PMQFP144-2 package
21
10
HFLB
20
GNDDAC
SAFETY
PSWEQ
ADB18
ADB16
ADB15
VSUP3.3DAC
19
VSUP3.3IO
18
GND
53
ADB17
GND
17
VSUP3.3BE
54
ADB13
ADB14
XREF
16
VRD
15
BOUT
14
VCT 49xyI
128
55
P36 / 656IO6
P37 / 656IO7
VIN11
VIN10
VIN9
VIN8
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
VOUT1
VOUT2
VOUT3
VSUP1.8FE
GND
GND
VSUP3.3FE

__________________________________________________________________________________________________________________
WM8725
99dB Stereo DAC

DESCRIPTION
FEATURES
WM8725 is a high-performance stereo DAC designed for

use in portable audio equipment, video CD players and
2
similar applications. It comprises selectable normal or I S
compatible serial data interfaces for 16 to 24-bit digital
inputs, high performance digital filters, and sigma-delta
output DACs, achieving an excellent 99dB signal-to-noise
performance.
The device is available in a 14-pin SOIC package that

offers selectable mute and de-emphasis functions using a
minimum of external components.
99dB SNR performance

Stereo DAC with input sampling from 8kHz to 96kHz
Additional mute feature
Normal or I2S compatible data format
Sigma-delta design with 64x oversampling
System clock 256fs or 384fs
Supply range 3V to 5V
14-pin SOIC package
APPLICATIONS
Portable audio equipment

Video CD players
BLOCK DIAGRAM
__________________________________________________________________________
101

__________________________________________________________________________________________________________________
WM8725
Production Data
PIN CONFIGURATION
LRCIN
14
SCKI
DIN
13
FORMAT
BCKIN
12
DEEMPH
NC
11
NC
CAP
10
MUTE
VOUTR
VOUTL
GND
VDD
WM8725
ORDERING INFORMATION
DEVICE
TEMPERATURE
RANGE
WM8725ED
WM8725ED/R
WM8725GED/V
WM8725GED/RV
PACKAGE
MOISTURE SENSITIVITY
LEVEL
PEAK BODY
TEMPERATURE
-25 C to +85 C
14-pin SOIC
MSL1
240 C
-25oC to +85oC
14-pin SOIC
(tape and reel)
MSL1
240oC
-25oC to +85oC
14-pin SOIC
(lead free)
MSL2
260oC
-25oC to +85oC
14-pin SOIC
(lead free tape and reel)
MSL2
260oC
Note:
Reel quantity: 3,000
PD Rev 4.1 August 2004
102

__________________________________________________________________________________________________________________
WM8725
Production Data
PIN DESCRIPTION
PIN
NAME
TYPE
DESCRIPTION
LRCIN
Digital input
Sample rate clock input
DIN
Digital input
Serial data input
BCKIN
Digital input
Bit clock input
NC
No connect
No internal connection
CAP
Analogue output
Analogue internal reference
VOUTR
Analogue output
Right channel DAC output
GND
Supply
0V supply
VDD
Supply
Positive supply
VOUTL
Analogue output
Left channel DAC output
10
MUTE
Digital input
Mute control, high = muted. Internal pull-down
11
NC
No connect
No internal connection
12
DEEMPH
Digital input
De-emphasis select, high = de-emphasis ON. Internal pull-up
13
FORMAT
Digital input
Data input format select, low = normal, high = I2S. Internal pull-up
14
SCKI
Digital input
System clock input (256fs or 384fs)
PD Rev 4.1 August 2004
103

LCD Profilo Telra PT1000

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LCD Profilo Telra PT1000

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Available Formats

26-32 LCD-TV

26'' - 32 '' LCD-TV PT1000 Service Manual

EDD1232AAFA (4M wordsx32 bits)

26'' - 32'' LCD-TV PT1000 Service Manual

VCT 49xyl, VCT 48xyl

26'' - 32 '' LCD-TV PT1000 Service Manual

1. Assembling/ Disassembling Procedure

EXPLODED WIEW PART LIST

EXPLODED WIEW PART

FRONT CABINET V01 INSERT

EXPLODED WIEW PART LIST

26'' - 32 '' LCD-TV PT1000 Service Manual

EXPLODED WIEW PART LIST

26'' - 32 '' LCD-TV PT1000 Service Manual

26'' - 32 '' LCD-TV PT1000 Service Manual

2. SAFETY INSTRUCTIONS AND PRECAUTIONS

HANDLING THE MOS CHIP COMPONENTS

26'' - 32 '' LCD-TV PT1000 Service Manual

2.1.1. Mounting Precautions

26'' - 32 '' LCD-TV PT1000 Service Manual

causes metallic foreign material and deal LCM a fatal blow)

2.1.4. Precautions for Strong Light Exposure

2.1.6. Handling Precautions for Protection Film

26'' - 32 '' LCD-TV PT1000 Service Manual

Full HD(1080p) support

26'' - 32 '' LCD-TV PT1000 Service Manual

26'' - 32 '' LCD-TV PT1000 Service Manual

Stand By, Sleep & Suspend

Power Consumption normal

10Wrms + 10Wrms ( 10%)

Frequency Synthesizer System

1) VHF LOW: 46.25~127.25MHz

26'' - 32 '' LCD-TV PT1000 Service Manual

3.3 Supported Resolutions

DTV Mode (Component Video Input: Y/Pb/Pr)

26'' - 32 '' LCD-TV PT1000 Service Manual

YPbPR AUDIO INPUT

DVI-D (Single Link) INPUT

HDMi AUDIO INPUT

SCART AUDIO INPUT

SCART AUDIO OUT

SCART CVBS INPUT

SIDE AV CVBS INPUT

SIDE AV AUDIO INPUT

MAIN SPEAKER L/R

AM0005 BLOCK DIAGRAM

26'' - 32 '' LCD-TV PT1000 Service Manual

POWER BLOCK DIAGRAM

PIP VIDEO DECODER

26'' - 32 '' LCD-TV PT1000 Service Manual

26'' - 32 '' LCD-TV PT1000 Service Manual

I2C BLOCK DIAGRAM

26'' - 32 '' LCD-TV PT1000 Service Manual

1) J916: For IR, LED - Wafer

LED drive for RED Color

5V Power for IR Receiver

2) J917: For Local Key - Wafer

Local Key Value Detection

3) J909: For Debugging - Wafer

3.3V Power for Debugging Tool

4) J912: For Debugging - Wafer

5) J915: For HDCP Writing - Wafer

26'' - 32 '' LCD-TV PT1000 Service Manual