ANALOG AND DIGITAL VLSI DESIGN

Analog Design Assignment (20 marks)

Objective:

To give you an exposure to MOSFET fabrication sequence

To get you over the real world Analog/Mixed signal design.

To develop your intuition for designing.

You should be able to determine how and which of the transistors sizes (W/L) in the
circuit will affect which parameters (specs).

Practical understanding of concepts like feedback, stability, compensation techniques.

Using EDA tools efficiently in system design

General Instructions:
PART1--

Each group is required to design an MOS transistor using SILVACO tool, extract the MOS
parameters. Simulate using those parameters and obtain MOS characteristics.

PART2--

You are given 7 analog subsystems that are mostly used in real life analog design. You can
choose any one of them and follow the design methodology given below.

There has to be TWO students per group at the maximum.

Only 13 (or14) groups (at the maximum) can register for any particular circuit out of 7
projects listed. Projects would be allotted based on first come first register basis.

Please inform IC regarding your chosen circuit by 30 Jan. 2009.

There are two tools to work by: Cadence and Mentor Graphics. You are free to choose any of
them.

For Cadence: you need to design the circuit in 'Virtuoso Schematic Editor' and simulate it with
'Spectre simulator.' For Mentor Graphics: you need to design the circuit in 'Design Architect' and
simulate it with 'Eldo simulator.' Extra reading is required for understanding of these circuits.

Design instructions:

Each of given analog circuit contains an Operational amplifier which is the building
block of all the circuits given. Each team should draw a layout of OPAMP.

We are providing you with broad specifications. You need to decide the values of it. For
reference we are providing the typical values of it and ideal one. As the assignment will
be based on relative grading, the more challenging you make from others the more marks
you will be awarded. Challenging refers that how close are your specs to the ideal one.

From these system specs , you will get the opamp specs.(Refer Razavi : Ex.9.1 and
9.2,pg 292-294)

After getting the opamp specifications, decide the topology of Opamp.(Refer Razavi :
Table 9.1,pg 314)

You can follow the conventional gm/Id method to design an opamp and other circuits.

Characterize your design by tabulating obtained values of all (maximum) parameters

(specs) which you studied in the class.

If you are not able to meet your specs, you can go ahead with system design, but you
need to explain why it has happened at the time of demonstration.

If required, you can change specifications. However you need to give a clear justification

Validate your design for all process corners and temperature Variation. Keep the power
dissipation as small as possible.

Layout is an integral part of the design

You should submit a soft copy of DETAILED report of your assignment to IC.

Your design should meet specification at all process corners with temperature varying
from -40o to 125o C.

Common Specifications:
Technology node

: tsmc 180nm CMOS

VDD

=3V

CL

1 pF

(at the output)

Current Mirror ratios 20

Do not design Current Reference. Instead use ideal current source with the value decided by you.
(Note: As you know 180nm technology refers to your minimum length of the transistor. However
you need to choose the length of the transistor above 0.36 um.)

Circuits:
There are 7 analog circuits given below. Some of the required information with respect to
particular circuit is given to you. Typical values of (specifications) performance parameters is
also listed in a table. Your design may not require all values. Choose intelligently
For most of the circuits given switches are required. Implement Switch by simple NMOS or
PMOS or both (to decrease the ON resistance of it).
1. Switched Capacitor Amplifier:
Here the ON time of switches S1 and S2 are same.S1 and S2 are driven by clk and S3 by clk
so that S3 is non-overlapping with the rest two. You need an external resistor in this case to
continuously bias the negative terminal of opamp.
Specs:
1. Maximum frequency of operation(of input)
2. settling time(for step input)
3. gain error
4. PSRR

Simulations:

Output Drift: There can be drift in the output dc level with time. You will be required to
run a transient simulation to discover the drift.

DC Offset

2. Gm-C Integrator :
This circuit is mainly used for very high speed Gm-filter (large cut off frequency).So it is
needless to say to build this integrator as high speed as possible. Its an open loop configuration.
So, you dont have to bother about the feedback. Gm stage is basically voltage to current
converter. You can use gain boosted opamp as your Gm stage.(Refer Razavi, fig.9.24(c) pg 310)

Specs:
1. DC gain
2. PSRR
3. Cutoff Frequency
4. Input voltage range
Simulations:

Gain (Gm) with frequency

Phase plot (show the phase error, starting pole location)

3. 10-bit DAC:
Maximum frequency signal (pulse) will be given to LSB bit. Each of the bits from MSB to
LSB will be having half the frequency of its next consecutive bit. The value of Resistance (R)
has to be decided by you. It can around 10 k ohm.

Specs:
1. Resolution
2. Dynamic Range
3. Maximum frequency of operation (for LSB bit)
4. Settling time
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Simulations:

Differential nonlinearity (DNL) error: It is the difference between an actual step-height of

the analog output and its ideal value of 1 LSB.

Integral nonlinearity (INL) error: It is the linear deviation of the values of the actual
transfer function from a straight line.

DC Offset(offset error output)

4. 4-bit (changed from 6 bit)Flash ADC:

This is high speed architecture. So your frequency of operation should as large as possible.
You need to choose your opamp topology such that the same comparator can reused. The output
of this will be thermometer code. You also need to add digital gates at the output to get proper 4
bit binary output.
The value of Resistance (R) has to be decided by you. It can around 10 k ohm.

Specs:
1. Maximum frequency of operation
2. Resolution
3. Settling time
4. SNR
Simulations:

Differential nonlinearity (DNL) error: It is the difference between an actual step-width of

the analog input and its ideal value of 1 LSB.

Integral nonlinearity (INL) error: It is the linear deviation of the values of the actual
transfer function from a straight line.

DC Offset(offset error at the output)

5. Sample and Hold Amplifier:

Choose an opamp topology such that you can reuse it.

Specs:
1. Maximum Frequency of Operation
2. Input Voltage Range
3. sample-to-hold transient settling time
4. PSRR
Simulations:

Aperture Time(S to H)

Acquisition Time(H to S)

6. Fully Differential Opamp:

You can choose any opamp to meet your specifications. You are required to design opamp as
ideal as possible.You also need to design the capacitive CMFB circuitry for this opamp.
Opamp specs:
1. DC gain
2. Unity gain Bandwidth
4. Phase margin
5. slew rate

6. SNR (signal to noise ratio)

7. CMRR
8. PSRR
9. Output swing
10.ICMR
Simulations:

CMFB circuitry gain

Input transistor mismatch analysis( for change of W/Ls of input transistors)

Settling time for unity feedback (for 1 volt step input)

DC Offset

7. Design digitally corrected 1.5 bits per stage (at least 30 MSPS) 10 bit pipelined ADC

Reference----

Through simulations, Obtain worst case-----

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OPAMP specs.

INL

DNL

RESOLUTION

TYPICAL SPECIFICATION TABLE

Parameters
Frequency of operation
DC gain
Cut off frequency
Input common mode
Range
Resolution
Dynamic Range
SNR
UGB
Input Offset
Phase margin
Slew Rate
CMRR
PSRR
Output swing
Settling time
Gain Error
Power Dissipation

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Typical values
>10 MHz
>=80 dB
>10 MHz
>=1 V

Ideal values
As high as possible(Infinity)
As high as possible
As high as possible
0 to VDD

4 bit (for ADC)

0.1 V (for DAC)
24 dB
>=40 dB
>=300 MHz
< 5 uV
>=55 degree
>=50 V/usec
>=70 dB
>=70 dB
>2 V
< 25 ns
<2%
< 3 mW

Maximum bits (for ADC)

Lowest voltage (for DAC)
As high as possible
As high as possible
As high as possible
As low as possible
60 degree
As high as possible
As high as possible
As high as possible
0 to VDD
As low as possible
As low as possible
As low as possible

Project Report Format

Abstract
This document will describe approach towards the assignment. (Submit by 1 Feb. 2009 hard
copy)
1. Introduction
Please make a group of only 2 students. What follows this section is a break-up of the pages to be
included in the report.
You will be asked to submit various pages on different dates. This will ensure
that you do not fall behind. You are requested not to share your work with
each other.
Please read all the documents pertaining to this assignment thoroughly before embarking upon your
design.
2. Report body Format
Please adhere strictly to the format that is given to you. You will be penalized by marks in case of
deviation.
Remember that your eventual marks will depend crucially upon the clarity of thought that you
present in the report.
As in case of the last assignment, your report may either be typed or legibly hand written on A4
sheets.
2.1
Page wise Breakup
What follows is a page wise breakup of your report.
2.1.1 Page 0
This will be the cover page and should include the choice of assignment, your name(s) and id
number(s) and your tutorial instructors name. (Submit by 1 Feb. 2009 hard copy)
2.1.2 Page 1
Given circuit diagram and the design specs only. Remember that these design specs are to be
decided by you in accordance with the typical values and will be evaluated competitively. (Submit
by 1 Feb. 2009 hard copy)
2.1.3 Page 2
Mathematical expressions for all the design specs - the schematic components that they depend
upon etc. If possible, then relations between the input and output variables for your chosen
subsystem are to be derived in terms of the components shown on the schematic. (Submit by 5
Feb. 2009 hard copy)
2.1.4 Page 3
Here you will need to derive and explain the relationship between each system
level design spec that you have been given and the opamp specs. For each
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system design spec, list the related opamp spec(s) and quantify mathematically
what the amplifier specs have to be such that the design specs are met.
You may use upto 3 pages maximum for this. Please label them 3.1, 3.2, 3.3 in that case. (Submit by
15 Feb. 2009 hard copy)
2.1.5 Page 4
Transistor level schematic of the operational amplifier. You are encouraged
to use the gm /Id method for this. Note that using trial-and-error as a method
for design will fetch you not more than 25% of the credit allotted to this design
phase.
Each transistor should have mentioned beside it on the schematic the gm /Id
value and the (W/L) ratio. There should be no lookup tables for this and
for every transistor this information should be found clearly marked on the
schematic. (Submit by 20 Feb. 2009 hard copy)
2.1.6 Page 5
Bode plot of the amplifier transfer function - both magnitude and phase. Please label the low
frequency gain and phase margin.
This page should end with a table of the measured (simulated) values of the relevant opamp
specs. (Submit by 20 Feb. 2009 hard copy)
2.1.7 Page 6
Graphical simulation results and tabulation of all the design specs. Name pages as 6.1, 6.2 etc. if
necessary.

3.1 Layout Results

Note that from here onwards you will need to submit all results as extracted from your layout
and not your schematic. This is very important! If you miss this out you will be heavily
penalized. All Post Layout Simulations have to be done on the Opamp alone after Parasitic
Extraction.
3.1.1 Page 5 - Layout
Repetition of Page 5 above but with all results from layout.
3.1.2 Page 7
LVS Results.
3.1.3 Page 8
Any other simulation results that you feel are pertinent to your design.
3.1.4 Page 9
Noise simulation and PVT results.
3.1.5 Page 10
Conclusion of assignment. Mention the meeting of specs or the failure to do so.
Failure to meet any specs should be justified.

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Also mention in this section, the problems that yo u might have encountered
during the course of this assignment.

All for now. This document will be updated regularly...

Final submission-----A soft copy of your report to be submitted to IC ON 25 FEB. 2009)

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