Designing and Implementing a System of

Multiplexing and Demultiplexing on FPGA using

MATLAB/Simulink for the Detection of Acoustic
Signals
M. Abdillahi-Said and C. Park
Universit du Qubec Rimouski
300 Alle des Ursulines
Rimouski, PQ, G5L 3A1, Canada
Mohamed.Abdillahi-Said@uqar.qc.ca
Abstract- In order to locate the source of a sound in the sea, we
can use a series of hydrophones. We can go up to a dozen, more
we have, the better accuracy. But when descending to depths very
significant (1 km), all wiring becomes heavy. Indeed, each
hydrophone requires a pair of wire twisted in addition to other
wires when they are equipped with a preamplification circuit.
Ultimately, the power cable becomes very large and very
cumbersome when it comes to the wind, especially if it is deployed
over several hundred meters. Thus, our mission is to develop a
technique to reduce the diameter of the cable carrying the
information captured by hydrophones, priority or other sensors
plunged into the sea, to a computer to the surface. The proposed
solution is to send each hydrophone signals through an optical
fiber. The challenge is therefore to develop a technique to convert
signals from several hydrophones and multiplex them through an
optical fiber. Then, the signals transmitted are converted into
electrical signals to store in .wav format on the hard disk of a
computer. The use of an optical fiber is justified by the fact that
they can transmit a considerable amount of information thus
reducing the number and size of transmission cables. In this
paper we will explain the general system architecture including
optical fiber transmission system and especially we will show the
implementation of the multiplexer and de-multiplexer system on
FPGA using MATLAB/Simulink with system generator in Xilinx
system.

I.

optical receiver and a hydrophone and one output to transmit

the optical signal to upper CMD module including preamplifier
and FPGA based multiplexing and de-multiplexing system.
On the boat, there is a surface module (Fig.1) that receives the
multiplexed optical signal via optical fiber cable. The
architecture of surface module is shown in
Fig.1. The
advantage of this single fiber optic wire system comparing to
the copper wire system is low cost and very light. The
architecture of our system is built in the following way.

INTRODUCTION

A. Description of the system

The system architecture is described as follows. The system
consists of a main module in the vessel and many
Conversion/Multiplexing/Diffusion module (CMD) (Fig.1)
down to a kilometer depth at sea. From 500 meters deep, the
fiber optic cable is separated into sections of 50 meters with
CMD module including hydrophone. Each hydrophone is
connected to the CMD module which is connected to fiber
optic cable to transmit the optical signal to the upper CMD
module system. This CMD module has two inputs including an

978-1-4244-2620-1/08/$25.00 2008 IEEE

Figure 1. The system architecture and the surface module

However, under this project, we designed a prototype

formed by three modules: two submarines (CMD) modules for
the multiplexing and a surface module for the demultiplexing
operation.

B. Presentation of Conversion/Multiplexing /Diffusion module

The CMD module includes several sub-systems: an
Analog/Digital converter, a multiplexer (made with a FPGA),
optical receiver and an optical transmitter (Fig.2). The A/D
converter is AD977, 16 bits, which can be sampled up to 100
kHz. The FPGA is a Spartan-3 from XilinX Inc. The FPGA
and the A/D converter receive an synchronization signal from
the surface module.
In this paper we will demonstrate our optical fiber based
transmission system at sea to send the collected and
multiplexed acoustic signals to the surface and finally to
demultiplex the incoming signals to the original acoustic
signals. Also we will show a developed methodology for the
hardware implementation of complex real-time DSP
applications on a reconfigurable logic platform using Xilinx
System Generator [1] for MATLAB/ Simulink [2].

several different sources, to form a composite signal

transmitted on a single medium. The demultiplexing is to
restore bits or characters from each source, from multiplexed
signal. In principle, the total received characters on all
channels low speed is less than the speed of the track
composite. So in this project, to simulate the multiplexing
system, we used the Xilinx System Generator tool. We'll see
how we used it in the following sections.
A. System generator
System Generator developed in partnership between Xilinx
and The MathWorks is a component that allows to select the
characteristics of the target material support, to set the clock
speed of the circuit and most importantly, to generate
automatically the Hardware Description Language (HDL) code
from a system representation in Simulink of the application to
implement. From these generated programs, XST (Xilinx
System Tools) can synthesize, compile and make a placement
of components and routing communications between
treatments on the circuit selected. The HDL design can then be
synthesized for implementation in Xilinx FPGAs using Xilinx
ISE (Integrated System Environment) Foundation which is an
implementation tools.
B. Modeling system with the Xilinx TDM and TDD (Time Division
Demultiplexer) blocks
The Xilinx toolbox is a library of IP (Intellectual Property)
software made up of several components of calculation similar
to Simulink, it allows applications that model will be based on
logic (FPGA). In our work, we used the SPARTAN-3 [4].
The system consists to multiplex two sources that can
generate random binary sequences (Fig.3). We will explain in
the following paragraph how these two blocks operate.

Figure 2. Conversion / Multiplexing / Diffusion module (CMD)

II. MODELING AND SIMULATION OF A TIME DIVISION

MULTIPLEXER (TDM) OF TWO SIGNALS WITH SIMULINK USING
SYSTEM GENERATOR

The principle of time divison multiplexer [3] results of the

combination or the interlacing of bits or characters from

The TDM block has two to 32 input ports and one output
port. All input ports must have the same arithmetic type,
precision, and rate. The output port has the same arithmetic
type and precision as the inputs. In our case we used a double
precision. The output rate is n r, where n is the number of
input ports and r is their common rate. In our case, the signals
are sampled at 60 kHz, we set the sampling period to 1/60000
in the two Gateway In blocks. Moreover, as we have two
inputs at the multiplexer, we set the System Generator period
to 1/120000.
Time Division Demultiplexer (TDD) block accepts input
serially and presents it to multiple outputs at a slower rate. The
block has one data input port and a user-configurable number
of data outputs, ranging from 1 to 32. The block has two
possible implementations, single or multiple channels. For
single channel implementation, the time division demultiplexer

block has one data input and output port. For multiple channel
implementations, the time division demultiplexer block has one
data input port and multiple output ports equal to the number
of 1's in the frame sampling pattern. For example, if we have
two signals to demultiplex, we must choose [1 1] to say that we
will use the first two channels or choose [1 0 1] to say that we
will use the first and third channels. In our model, we used the
multiple channel implementations.

Figure 3. TDM of two signals

We have shown in Fig.4, the result with both input signals

and multiplexed output. As expected, we see that the third
signal is the combination of input signals, the principle of time
multiplexing. There is a very slight delay due to time spread
across the bloc multiplexing not seen here.

Figure 4. The two inputs signals and the multiplexed output

At the exit of the TDM block, the two signals are

demultiplexed through TDD block and then we get the
originals signals (Fig.5). The first signal is the first input (E0)
and the second one is the demultiplexed output (S0). In the
same way, the third one is the second input (E1) and the last
one is the second demultiplexed output (S1).

with System Generator that lies on a map (memory) FPGA

connected to the module, we multiplex the two signals. These
are sent at the surface module to be demultiplexed (Fig.7). At
the exit of the optical receiver, the signal passes through a
differential operational amplifier to get the original signals.
Then, through a demultiplexing program that we implemented
on a third FPGA card, the two signals are separated. Each of
them goes through a D/A converter, then by a low pass filter
(cut off frequency of 30KHz) and an operational amplifier to
amplify the signal. In the following sections, we presented the
various tests conducted on components of the prototype.

Figure 5. Comparison between the two inputs signals and the demultiplexed
outputs

III. MATERIALS AND METHODOLOGY FOR IMPLEMENTATION

Figure 6. Prototype

A. Prototype
For experimental trials, we designed a system composed of
three modules. One surface module and two submarines
modules (one bottom module and one middle module), which
are identical in hardware. The three modules are linked by
optical fiber (Fig.6). The operating principle is as follows: We
generate an arbitrary sinusoidal signal of 1.5 KHz and a few
tens of mV to send to the bottom module. The signal is then
amplified. Then, it passes through the A/D converter. At the
exit of the latter, the signal is routed to a second operational
amplifier that allows a differential output to reduce noise.
Indeed, optical transmitter/receiver works with an input and a
differential output. The control of the A/D conversion is done
with the FPGA. Then, once the signal from the bottom
submarine module has come down to the middle submarine
module, the same way as previously, we injected a second
signal in the latter. Through the multiplexing program obtained

B. Tests on the FPGA

We use the FPGA for two reasons, it will generate
multiplexing and demultiplexing and the control of different
parts of the circuit, as the A/D, the optical transmission [5] and
conversion D/A. We will treat each of the functions of the
FPGA in the following paragraphs. The FPGA is programmed
in VHDL with the ISE software.

C. Control of the A/D conversion

The AD977 converter is a serious 16-bit, which can run up
to a rate of 100 kHz. It requires a 5V power. Various

configurations can be used as needed. For examples, it can

operate with an input voltage of +/ - 10V, + /-5 V, +/ - 3.3 V,
0-10V, 0-5V or a 0-4V, while having the possibility to adjust
the gain and "offset". Of course, the value of the least
significant bit will be lower if the margin of input voltage is
less. The converter also offers the possibility to operate with a
external or internal clock. There is a possibility configuration
using the internal clock. Things are becoming more complex,
however, when one wants to use an external clock. Without
describe each of them in detail, we can say that the various
modes are available with discontinue or continue signal clock,
being read during or after the digital conversion, and finally the
option to generate a signal synchronization or not.

E. Implementation tool
The implementation tool that we used is Xilinx ISE. In each
module, we created some control functions such as controlling
the A/D converter and the optical transmission system. We
used to write other functions associated with multiplexing
module to retrieve data from the module at the bottom or to fix
the timing constraint. Indeed, as the signals multiplexer fail at
the same speed in the middle of the module, we had to adapt
the different frequencies of each module.

In terms of performance, the AD977 has a response with

transition maximum of 2 V , a recovery time of the overload
150 ns. These periods in time should be considered, because
they represent a good time compared to the clock. As listed
above, the speed of sampling is to 100 kHz.

D. Control of the optical transmission

As we said previously, the optical transmitter/receiver works
with one differential input and output. So the digital signal
which came from to the output of A/D converter must be
reversed. We have placed a logical inverter in a block diagram.
In that way, we have two signals data reversed each other.

E. Control of the D/A conversion

The AD1851 is a digital-analog converter of 16 bits. Its 16bit resolution gives it a dynamic margin of 96 dB. One of his
qualities is that it requires no external part. Like other
components to be used in the module, the AD1851 must be
supplied to 5V. However, it must also be supplied with
negative which requires an interface to adapt to -5 V. The
converter thus accumulates packets of 16 bits that are
determined using the clock and "Latch." The clock gives an
indication of the duration of each bit and "Latch" gives an
indication beginning of each group of 16 bits, the front
descending Announces bit more significant.
This converter was chosen first to test operation in order to
plug the analog output of the demultiplexed system to a
standard sound card. The operating principle of the AD1851 is
simple and requires no specific configuration as the internal or
external clock operation mode. However, it is important that
the speed of operation is respected and the command signals
are synchronized.

Figure 7. Block Diagram of the multiplexer

We presented in Fig.7, the program loaded into the middle

submarine module that allows both signals to be multiplexed in
the form of block diagram. We recall that the code is written in
VHDL [6]. We can see in Fig.8, the block diagram of the
demultiplexing program, which is on the surface module.

REFERENCES
[1]

Xilinx, System Generator for DSP - User's Guide, Version 9.1.01, March
19, 2007.

[2]

The MathWorks Inc., Simulink, Dynamic System Simulation for

Matlab, Using Simulink , Natick, Mas- sachusetts, 1999.

[3]

Roger L. Freeman, Telecommunication system Engineering, Second

Edition, 1985.

[4]

Xilinx, Spartan-3, Starter Kit Board, User Guide, UG130 (v1.1) May.
13, 2005.

[5] J. E. Midwinter and Y. L. Guo, Optoelectronics and Ligthwave

Technology, Wiley, 1992.
[6] P. Coste, J. O. Klein, and J. Weber, VHDL et la synthse logique, 2007.

Figure 8. Block diagram of the demultiplexer

CONCLUSION
In this paper we demonstrate the FPGA based multilpexing
and demultiplexing system to collect the acoustic signals in
marine application. By using two input signals we showed the
possibility of mutiple signals multiplexing/demultiplexing
capability. We had to develop a technique that would recover
signals from several hydrophone and then to multiplex them
via an optical fiber.
ACKNOWLEDGMENT
The authors would like to acknowledge Sataya Aing and
Samuel Austin at Universit du Qubec Rimouski for the
many insightful discussions.