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Vol. 34, No.

Journal of Semiconductors

February 2013

A fast novel soft-start circuit for peak current-mode DCDC buck converters
Li Jie(), Yang Miao() , Sun Weifeng(), Lu Xiaoxia(),
Xu Shen(), and Lu Shengli()
National ASIC System Engineering Research Center, Southeast University, Nanjing 210096, China

Abstract: A fully integrated soft-start circuit for DCDC buck converters is presented. The proposed high speed
soft-start circuit is made of two sections: an overshoot suppression circuit and an inrush current suppression circuit.
The overshoot suppression circuit is presented to control the input of the error amplifier to make output voltage
limit increase in steps without using an external capacitor. A variable clock signal is adopted in the inrush current
suppression circuit to increase the duty cycle of the system and suppress the inrush current. The DCDC converter
with the proposed soft-start circuit has been fabricated with a standard 0.13 m CMOS process. Experimental
results show that the proposed high speed soft-start circuit has achieved less than 50 s start-up time. The inductor
current and the output voltage increase smoothly over the whole load range.
Key words: current-mode; DCDC converter; soft-start; inrush current; overshoot voltage
DOI: 10.1088/1674-4926/34/2/025006
EEACC: 2570

1. Introduction
In recent years, switching power supplies have been
widely applied in portable electronic systems market due to
their high efficiency, stability, and dynamic characteristics1 .
A typical block diagram of a current-mode DCDC buck converter is depicted in Fig. 1. It works in a control loop converting
the error signal into a variable duty cycle of the driving signal
for the switching element. The problem is that at the beginning
of the start-up transient the error amplifier (EA) is unbalanced,
thus causing the converter to work at 100% duty cycle. This
situation makes the inductor current rise above its equilibrium
value, and produces an inrush current. And it will remain above
its equilibrium value for a little time because the inductor current cannot change instantaneously. This can induce the output
voltage to rise abruptly to exceed its regulated value2 . The
electronic system may be damaged at the start-up period by
the inrush current and overshoot voltage. Therefore a soft-start
circuit is normally adopted to eliminate the inrush current and
reduce the overshoot voltage.
The most conventional method is using an external capacitor named Csoft to make the output voltage rise slowly3 5 .
The output of the EA or the reference voltage Vset rises gradually when Csoft is charged linearly. The soft-start time of the
converter depends on the charge current and the value of Csoft .
The method has an explicit principle and can be used effortlessly, but the capacitor is usually too large to be integrated
on chip. Another method to limit the output voltage is the
clock-based soft-start circuit, which can precisely control the
start-up time6 . These two methods are both devised to control the output voltage. In addition, the method of suppressing
the inrush current is to detect the current of the inductor and
compare the current with a constant current value. Considering that the limited current is usually higher than the maximal

working current, the piecewise limited current value is used in


soft-start phase7 9 . However, many comparators are used to
judge the changing condition, so this method is not suitable for
converters that do not have a current limiting function. A high
speed soft-start control circuit which can achieve a start time of
150 s is proposed in Ref. [10]. However, the switching does
not work at the first period thus causing a prolonged soft-start
time, and the circuit implementation is very complex.
Therefore, in this paper a fast novel circuit with simple
D/A (digital-to-analog) converter and variable minimum duty
cycle is proposed for applications in variable output voltage
without overshoot voltage and inrush current. The proposed
circuit implementation is introduced in Section 2. Simulated
and measurement results are shown in Section 3 and the conclusion is made in Section 4.

Fig. 1. Typical structure of a peak current-mode DCDC buck converter.

* Project supported by the Natural Science Foundation of Jiangsu, China (No. BK2011059), the Program for New Century Excellent Talents
in University (NCET-10-0331), and the Qing Lan Project.
Corresponding author. Email: myron@seu.edu.cn
Received 21 June 2012, revised manuscript received 11 September 2012
2013 Chinese Institute of Electronics

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Fig. 2. Overshoot suppression circuit.

2. Proposed soft-start circuit


Based on the principle of conventional current-mode converters, an improved soft-start scheme is proposed. The scheme
is made of two sections: an overshoot suppression circuit and
an inrush current suppression circuit.
At the beginning of the start-up, the voltage Vset is much
higher than Vo , which makes the EA unbalanced. Then the unbalanced EA may damage the whole system. Considering the
reasons above, we want to attain a ramp voltage instead of a
stable voltage. Obviously, a ramp voltage can be generated by
adding Vset with a ladder voltage, which is shown in Fig. 2.
The ladder voltage can be generated by a digital-to-analog converter (D/A). Moreover, because of the minimum duty cycle
used in the converter, inrush current will be generated in the
initial phase. A variable minimum duty cycle is proposed to
suppress the inrush current in this paper.
2.1. Overshoot suppression circuit
As shown in Fig. 2, the designed overshoot suppression
circuit implemented by the internal circuit mainly contains
three sections: the D/A, the resistance network, and the OPA.
The OPA and resistance network are used to set a variable reference voltage to meet the dynamic voltage scaling performance
of the DCDC converter. The block diagram of the D/A proposed in this paper is shown in Fig. 2. The output of the D/A
can be expressed as:


Q1
Q2
Q3
Q4
Q5
Q6
Q0
VD=A D Va
C
C
C
C
C
C
:
27
26
25
24
23
22
21
(1)
The output voltage of the D/A increases slowly with the
digital signal counting from 7b0 0000000 to 7b0 1000000 by the
clock. When the signal counts from 7b0 0111111 to 7b0 1000000,
MOS transistors M4 and M5 are turned off while the MOS transistors M6 and M7 are turned on to prevent the decrease of the

Fig. 3. Waveform of output voltage and inductor current at the ideal


fastest start-up phase.

output voltage of the D/A. So the output of the D/A will remain
in the voltage of Va . This structure ensures that the D/A output
slowly increases to a stable voltage.
The soft-start time is determined by the clock which controls the D/A. The fastest start-time of the system is when the
system works using maximum duty cycle up to a limited current. And the start-up includes two phases. If the inrush current
is not considered, the system will work using a maximum duty
cycle up to limited current Ilimited and then work using Ilimited
until the output voltage reaches stable value. The work state is
shown in Fig. 3. Therefore the fastest time can be calculated by
the two sections as follows.
(1) The system works using a maximum duty cycle up to
limited current
The time is t1 when the system works using a maximum
duty cycle up to a limited current, as shown in Fig. 3. As the
increment of output voltage is very small, zero is assumed to
represent the output voltage. Then the time t1 can be expressed

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in the following equation


t1 

Ilimited L
:
Vin

(2)

(2) The system works using limited current until the output
voltage reaches stability
As shown in Fig. 3 the time is t2 when the system works
using limited current until output voltage reaches a limited current. The inductor current keeps a stable value. The load and
the capacity are both charged. Therefore the charge process can
be expressed as follows:
ILoad D
IC D IL
IC D C

Vo
;
RL

(3)

ILoad ;

(4)

dVo
:
dt

(5)

The time t2 can be calculated by the differential equations


above:
 


Vo
Ilimited
Ilimited
t2 D RLoad C ln
C
C ln
:
RLoad C
C
C
(6)
Therefore the fastest time is the sum of the two parts:
trise D .Ilinited L/ =Vin RLoad C
 


Vo
Ilimited
Ilimited
 ln
C
C ln
:
RLoad C
C
C

(7)

It is obvious that it takes a longer time at a heavy load condition compared with a light condition. In the proposed circuit,
the rise time of Vset is designed slightly longer than trise to get
the balance of suppression of the overshoot of Vo and the softstart time.
As mentioned above, the 6-bits D/A will supply rising voltage slowly to the gate of transistor M1 in Fig. 2. However, the
gate voltage of transistor M2, which is larger than the gate voltage of M1, has been fixed on Vref , so at the initial phase of softstart, transistor M2 is cut off. And the drain current of M1, M2,
M3 will always meet
IM1 C IM2 D IM3 :

Fig. 4. Waveform of start-up IL and CLK (a) with constant minimum


clock and (b) with 3 times the cycle minimum clock.

(8)

Because of the virtual short characteristics of the operational amplifier, the gate voltage of transistor M3 will increase
with the rising of transistor M1. Moreover, IM1 will decrease
while IM2 increases at this phase to keep the balance of current.
When the gate voltage of transistor M1 rises to a certain value,
transistor M1 will be cut off. At this moment, IM2 D IM3 . The
soft start-up of the setting voltage is completed successfully.
Therefore the Vo will rise following the setting voltage Vset and
avoid the overshoot voltage. And the voltage Vset is set by the
resistance network.
2.2. Inrush current suppression circuit
In order to prevent the power MOSFET from thoroughly
closing and suppress the noise influencing the stability of the
converter between opening and closing the MOSFET, a clock

Fig. 5. Inrush current suppression circuit.

named CLK is used to guarantee the minimum duty cycle in our


DCDC converter. At the time of soft-start, because the output
voltage is very small, the converter will work on the maximum
duty cycle. The inductor current increases to the limited current within m cycles, as shown in Fig. 4(a). When the clock
works on a high level, the modulator-out signal and currentlimited signal will both be shielded, as shown in Fig. 5. On the
other hand, when the clock works on a low level, modulator and
current-limited circuits are working. Then the inductor current
will decrease when the clock signal is low because the current
limited circuit is working. And when the clock signal is high,
the inductor current will still increase, as shown in Fig. 4. The
charge slope of the inductor is Kup_slope D (Vin Vo /=L, while
the discharge slope is Kdown_slope D Vo =L. It is obvious that the
charge slope is much larger than the discharge slope at the incipient stage of Vo rising. As shown in Fig. 4(a) the inductor
current will exceed the limited current value easily after several cycles; then the inrush current is generated. The essential
reason of generating the inrush current is that the charge current is larger than the discharge current. Considering the above
problems, 3 times the cycle minimum clock is adopted in the
proposed soft-start circuit.
As shown in Fig. 5 when Vo is smaller than Vref1 a much
smaller cycle clock called CLK2 generating a smaller duty cy-

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cle is adopted in the initial phase, and then the discharge current
will be larger than that in CLK1. When Vo is larger than Vref1 ,
the system switches to CLK1. As shown in Fig. 4(b), several
clock cycles in CLK1 will be shielded to compose CLK2 and
the cycle of CLK2 is three times as much as the cycle of CLK1.
At the initial phase, the time the system spends rising to the limited value is the same. Then the discharge time of inductor is
longer and the charge time is shorter when the converter works
in CLK2. It is obvious that the inductor current will rise slower
and decrease larger when the converter works in CLK2. The
charge current is smaller than the discharge current, so the inrush current can easily be suppressed. When the voltage Vo is
larger than Vref1 , the system automatically switches to CLK1.
The key of this circuit is to set the voltage Vref1 . The voltage
Vref1 is set complying with the following principles.
(1) When the circuit switches to CLK1, the charge current
must be equal to or smaller than the discharge current. Otherwise, the circuit will generate inrush current after it switches
to CLK1, and the inrush current suppression circuit will lose
its function. (2) The inductor current must be smaller than the
limited current when the circuit switches to the CLK1, so it can
guarantee that the circuit has not generated inrush current.
The above principles can be expressed by the following
formulas:
Vin

Ik D Ik

Vref1
Vref1
Dmin1 T1 6
.1 Dmin1 / T1 ;
L
L
Z mT
Vin Vo .t/
I1 D
t.k D 1/;
L
0

mT C.k 2CDmin2 /T2

mT C.k 2/T2

mT C.k 1/T2

mT C.k 2CDmin2 /T2

Vin

(9)
(10)

Fig. 6. Simulated results of start-up Vset , Vout , IL and CLK (a) with
constant minimum duty cycle and (b) with variable minimum duty
cycle.

Vo .t/
t
L

Vo .t/
t 6 Ilimited .k D 2n/:
L
(11)

Dmin1 is the minimum duty cycle when the converter works


in CLK1 while Dmin2 is the minimum duty cycle in CLK2. T1
is the cycle of CLK1 and T2 is the cycle of CLK2. And the
cycle T1 , T2 meet 3T D 3T1 D T2 . Stable values are used to
replace the changing value of Vo . When I 6 I1 , Vo .t/  0.
When I2 6 I 6 In=3 , Vo .t/  13 Vref1 . When In=3 6 I 6 I2n=3 ,
Vo .t/  23 Vref1 . When I2n=3 6 I 6 In , Vo .t/  Vref1 .
Matlab is applied to calculate the value of Eqs. (10) and
(11) supposing the value of Vref1 is the critical value determined
by Eq. (9). The result shows the critical value of Eq. (9) can
meet Eq. (11). So the value of Vref1 is Vin Dmin1 .
And when Vo is larger than Vref1 , the system automatically
switches to CLK1. At this time, the charge current is equal to
the discharge current until the output voltage rises to the set
value. When the system is stable the current will decrease and
the start-up phase is completed.

3. Simulation and measurement results


The proposed circuits are implemented in a CMOS SMIC
0.13 m process. The simulated contrastive results are shown
in Fig. 6. Figure 6(a) is the simulated result when the constant

Fig. 7. Chip microphotograph of the buck converter with the proposed


soft-start circuit.

minimum duty cycle is adopted. It is obvious that the inrush


current still exists. The inductor current will exceed the limited
current value after several cycles. But in Fig. 6(b) the variable
minimum duty cycle is used in the system, so the inrush current
is effective controlled. The simulated results are presented to
the theoretical analysis.
The DCDC converter with the proposed soft-start circuits
has been fabricated in CMOS SMIC 0.13 m process. The
chip microphotograph is shown in Fig. 7 and the area of the
proposed circuits is only 0.06 mm2 . The input voltage of the

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rent suppression circuit. The overshoot suppression circuit generates a linear ramp voltage which can effectively suppress the
overshoot of the output voltage. The inrush current suppression circuit with a variable minimum duty cycle can suppress
the inrush circuit effectively. The simulation results show that
the proposed high speed soft-start circuit implemented to the
current-mode DCDC converter is well consistent with the theory. Using a standard 0.13 m CMOS process, the test chip has
been fabricated and experimental results are presented to the
theoretical analysis. The test result shows that this technology
can achieve a very fast start-up time of about 43.5 s. Furthermore, because the proposed soft-start circuit is designed with
a CMOS process, it is convenient to be transplanted to other
converters.

References

Fig. 8. Measured output voltage Vout (Channel 1) and inductor current


IL (Channel 2) during the start-up (a) with no load and (b) with load
200 mA.

converter is 3.3 V and the output voltage is 1.5 V.


Figure 8 shows the measured output voltage and inductor current during the soft-start with no load in Fig. 8(a) and
with load in Fig. 8(b). The experimental results match with the
analysis results, which did not induced the overshoot voltage
and inrush current. The soft-start time is only 43.5 s, resulting from the quick start response. This result has been shortened to 1/3 compared with an available high speed converter,
which achieves it in about 150 s in Ref. [10]. Therefore, the
functionality of the proposed soft-start circuit is successfully
verified.

4. Conclusion
This paper presented a fast integrated soft-start circuit consisting of an overshoot suppression circuit and an inrush cur-

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