Verilog code for Half adder

module
halfadder(a,b,sum,carry);
input a,b;
output sum, carry;
wire sum, carry;
assign sum = a^b; // sum bit
assign carry = (a&b) ;
//carry bit
endmodule

Verilog code for Full adder

module fulladder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
wire sum,carry;
assign sum=a^b^c; // sum bit
assign carry=((a&b) | (b&c) | (a&c)); //carry bit
endmodule

Verilog code for Parallel adder:

module parad4(a,c,p,q);
output [3:0]a;
output c;
input [3:0]p,q;
wire c1,c2,c3;
ha u1(a[0],c1,p[0],q[0]);
fa u2(a[1],c2,p[1],q[1],c1);
fa u3(a[2],c3,p[2],q[2],c2);
fa u4(a[3],c,p[3],q[3],c3);
endmodule

Verilog code for CLA(carry look ahead affer)

module cla32( d1,d2,clk,cin,sum,cout); //32 bit CLA using 8 4-bit CLA
adderes
input [31:0] d1;
input [31:0] d2;
input clk;
input cin;
output cout;
output [31:0] sum;
wire c0,c1,c2,c3,c4,c5,c6;
reg [31:0] b;
always@(posedge clk)
begin
if(cin==1)
b<=-d2-1;
else
b<=d2;
end
cla4 n1(d1[3:0],b[3:0],cin,sum[3:0],c0);
cla4 n2(d1[7:4],b[7:4],c0,sum[7:4],c1);
cla4 n3(d1[11:8],b[11:8],c1,sum[11:8],c2);
cla4 n4(d1[15:12],b[15:12],c2,sum[15:12],c3);
cla4 n5(d1[19:16],b[19:16],c3,sum[19:16],c4);
cla4 n6(d1[23:20],b[23:20],c4,sum[23:20],c5);
cla4 n7(d1[27:24],b[27:24],c5,sum[27:24],c6);
cla4 n8(d1[31:28],b[31:28],c6,sum[31:28],cout);
endmodule
//4 Bit CLA code
module cla4(a,b,cin,s,cout);
input[3:0] a,b;
input cin;
output cout;
output[3:0] s;
wire[3:0] g,p;
wire[13:0] z;
xor21 x1 (.a1(a[0]),.a2(b[0]),.z(p[0]));
and21 x2 (.a1(a[0]),.a2(b[0]),.z(g[0]));
xor21 x3 (.a1(a[1]),.a2(b[1]),.z(p[1]));

and21 x4 (.a1(a[1]),.a2(b[1]),.z(g[1]));
xor21 x5 (.a1(a[2]),.a2(b[2]),.z(p[2]));
and21 x6 (.a1(a[2]),.a2(b[2]),.z(g[2]));
xor21 x7 (.a1(a[3]),.a2(b[3]),.z(p[3]));
and21 x8 (.a1(a[3]),.a2(b[3]),.z(g[3]));
xor21 x9 (.a1(cin),.a2(p[0]),.z(s[0]));
and21 x10 (.a1(cin),.a2(p[0]),.z(z[0]));
or21 x11 (.a1(z[0]),.a2(g[0]),.z(z[1]));
xor21 x12 (.a1(z[1]),.a2(p[1]),.z(s[1]));
and31 x13 (.a1(cin),.a2(p[0]),.a3(p[1]),.z(z[2]));
and21 x14 (.a1(g[0]),.a2(p[1]),.z(z[3]));
or31 x15 (.a1(z[2]),.a2(z[3]),.a3(g[1]),.z(z[4]));
xor21 x16 (.a1(z[4]),.a2(p[2]),.z(s[2]));
and41 x17 (.a1(cin),.a2(p[0]),.a3(p[1]),.a4(p[2]),.z(z[5]));
and31 x18 (.a1(g[0]),.a2(p[1]),.a3(p[2]),.z(z[6]));
and21 x19 (.a1(g[1]),.a2(p[2]),.z(z[7]));
or41 x20 (.a1(z[5]),.a2(z[6]),.a3(z[7]),.a4(g[2]),.z(z[8]));
xor21 x21 (.a1(z[8]),.a2(p[3]),.z(s[3]));
and41 x22 (.a1(cin),.a2(p[0]),.a3(p[1]),.a4(p[2]),.z(z[9]));
and31 x23 (.a1(g[0]),.a2(p[1]),.a3(p[2]),.z(z[10]));
and21 x24 (.a1(g[1]),.a2(p[2]),.z(z[11]));
or41 x25 (.a1(z[9]),.a2(z[10]),.a3(z[11]),.a4(g[2]),.z(z[12]));
and21 x26 (.a1(z[12]),.a2(p[3]),.z(z[13]));
or21 x27 (.a1(z[13]),.a2(g[3]),.z(cout));
endmodule

Verilog code for RCA(Ripple carry adder):

module rip(s,cout,a,b,cin);
//main module of 16 bit Ripple carry adder
input [15:0]a;
input [15:0]b;
input cin;
output cout;
output [15:0]s;
wire c4,c8,c12,cout;
rip2 m1(s[3:0],c4,a[3:0],b[3:0],cin);
rip2 m2(s[7:4],c8,a[7:4],b[7:4],c4);
rip2 m3(s[11:8],c12,a[11:8],b[11:8],c8);
rip2 m4(s[15:12],cout,a[15:12],b[15:12],c12);

endmodule
module rip2(s,cout,a,b,cin);
//sub module for 4 bit Ripple carry adder
input [3:0]a;
input [3:0]b;
input cin;
output cout;
output [3:0]s;
wire c2,c3,c4,cout;
fa m1(s[0],c2,a[0],b[0],cin);
fa m2(s[1],c3,a[1],b[1],c2);
fa m3(s[2],c4,a[2],b[2],c3);
fa m4(s[3],cout,a[3],b[3],c4);
endmodule
module fa(s,cout,a,b,cin);
//sub module for Full adder
input a,b,cin;
output s,cout;
wire w1,w2,w3;
ha m1(w1,w2,a,b);
ha m2(s,w3,w1,cin);
or m3(cout,w2,w3);
endmodule
module ha(s,cout,a,b);
//sub module for Half adder
input a,b;
output s,cout;
xor m1(s,a,b);
and m2(cout,a,b);
endmodule

Verilog code for 32 Bit Pipelined Floating Point Adder :

module fpadd(a,b,clk,out);
input[31:0]a,b;

input clk;
output [31:0]out;
wire [7:0]e1,e2,ex,ey,exy,ex1,ey1,ex2,ex3;
wire s1,s2,s,s3,sr,sn,s4,sx1,sy1,sn1,sn2,sn3,sn4,sr1,sr2,sn5,sn6;
wire [23:0]m1,m2,mx,my,mxy,mx1,my1;
wire [24:0]mxy1,mxy2;
assign s1=a[31];
assign s2=b[31];
assign e1=a[30:23];
assign e2=b[30:23];
assign m1[23]=1'b1;
assign m2[23]=1'b1;
assign m1[22:0]=a[22:0];
assign m2[22:0]=b[22:0];
//submodule for compare and shfit
cmpshift
as(e1[7:0],e2[7:0],s1,s2,m1[23:0],m2[23:0],clk,ex,ey,mx,my,s,sx1,sy1);
buffer1 buff1(ex,ey,sx1,sy1,mx,my,s,clk,ex1,ey1,mx1,my1,sn,sn1,sn2);
//sub module for mantissa addition snd subtraction
faddsub as1(mx1,my1,sn1,sn2,sn,ex1,clk,mxy1,ex2,sn3,sn4,s3,sr1);
buffer2 buff2(mxy1,s3,sr1,ex2,sn3,sn4,clk,mxy2,ex3,sn5,sn6,s4,sr2);
//sub module for normalization
normalized as2(mxy2,sr2,sn5,sn6,s4,clk,ex3,sr,exy,mxy);
assign out={sr,exy,mxy[22:0]};
endmodule
module buffer2(mxy1,s3,sr1,ex,sn3,sn4,clk,mxy2,ex3,sn5,sn6,s4,sr2);
input [24:0]mxy1;
input s3,clk,sr1,sn3,sn4;
input [7:0]ex;
output reg[24:0]mxy2;
output reg[7:0]ex3;
output reg s4,sn5,sn6,sr2;
always@(posedge clk)
begin
sr2=sr1;
sn5=sn3;
sn6=sn4;
ex3=ex;
mxy2=mxy1;
s4=s3;
end

endmodule
module buffer1(ex,ey,sx1,sy1,mx,my,s,clk,ex1,ey1,mx1,my1,sn,sn1,sn2);
input [7:0]ex,ey;
input [23:0]mx,my;
input s,clk,sx1,sy1;
output reg [7:0]ex1,ey1;
output reg [23:0]mx1,my1;
output reg sn,sn1,sn2;
always@(posedge clk)
begin
sn1=sx1;
sn2=sy1;
ex1=ex;
ey1=ey;
mx1=mx;
my1=my;
sn=s;
end
endmodule
module normalized(mxy1,s,s1,s2,s3,clk,ex,sr,exy,mxy);
input[24:0]mxy1;
input s,s1,s2,s3,clk;
input[7:0]ex;
output reg sr;
output reg[7:0]exy;
output reg[23:0]mxy;
reg [24:0]mxy2;
always@(posedge clk)
begin
sr=s?s1^(mxy1[24]&s3):s2^(mxy1[24]&s3);
mxy2=(mxy1[24]&s3)?~mxy1+25'b1:mxy1;
mxy=mxy2[24:1];
exy=ex;
repeat(24)
begin
if(mxy[23]==1'b0)
begin
mxy=mxy<<1 b1="" o:p="">
exy=exy-8'b1;
end
end

end
endmodule
module faddsub(a,b,s1,s2,sn,ex1,clk,out,ex2,sn3,sn4,s,sr1); //submodule for
addition or subtraction
input [23:0]a,b;
input[7:0]ex1;
input s1,s2,clk,sn;
output reg [23:0]ex2;
output reg[24:0]out;
output reg s,sn3,sn4,sr1;
always@(posedge clk)
begin
ex2=ex1;
sr1=sn;
sn3=s1;
sn4=s2;
s=s1^s2;
if(s)
begin
out=a-b;
end
else
begin
out=a+b;
end
end
endmodule
module cmpshift(e1,e2,s1,s2,m1,m2,clk,ex,ey,mx,my,s,sx1,sy1); //module for
copare &shift
input [7:0]e1,e2;
input [23:0]m1,m2;
input clk,s1,s2;
output reg[7:0]ex,ey;
output reg[23:0]mx,my;
output reg s,sx1,sy1;
reg [7:0]diff;
always@(posedge clk)
begin
sx1=s1;
sy1=s2;
if(e1==e2)

begin
ex=e1+8'b1;
ey=e2+8'b1;
mx=m1;
my=m2;
s=1'b1;
end
else if(e1>e2)
begin
diff=e1-e2;
ex=e1+8'b1;
ey=e1+8'b1;
mx=m1;
my=m2>>diff;
s=1'b1;
end
else
begin
diff=e2-e1;
ex=e2+8'b1;
ey=e2+8'b1;
mx=m2;
my=m1>>diff;
s=1'b0;
end
end
endmodule

Verilog code for BCD Adder:

module bcdadd(a,b,cin,s,cout); //Main module of one digit BCD adder

input [3:0]a;
input [3:0]b;
input cin;
output[3:0]s;
output cout;
wire [3:0]w;
wire y,c0,c1,c2,c3,c4,c5;

fulladd m1(a[0],b[0],cin,w[0],c0);
fulladd m2(a[1],b[1],c0,w[1],c1);
fulladd m3(a[2],b[2],c1,w[2],c2);
fulladd m4(a[3],b[3],c2,w[3],c3);
assign y=c3|(w[3]&(w[2]|w[1]));
halfadd m5(w[1],y,s[1],c4);
fulladd m6(w[2],y,c4,s[2],c5);
halfadd m7(w[3],c5,s[3],cout);
assign s[0]=w[0];
endmodule
module fulladd(a,b,cin,s,cout); //submodule for fulladder
input a,b;
input cin;
output s;
output cout;
wire w1,w2,w3;
halfadd g1(a,b,w1,w2);
halfadd g2(w1,cin,s,w3);
assign cout=w3|w2;
endmodule
module halfadd(a,b,s,cout); //submodule for halfadder
input a,b;
output s,cout;
assign s=a^b;
assign cout=a&b;
endmodule

Verilog code for Carry Save Adder:

module carrysave(p0,p1,p2,p3,p4,p5,s,c,a,b);
output [5:0]p0,p1,p2,p3,p4,p5;
output [10:0]s;
output [7:0]c;
input [5:0]a,b;
wire
d,d1,d2,d3,d4,d5,d6,d7,d8,d9,d10,d11,d12,d13,d14,d15,d16,d17,e1,e2,e3,e4,e5,e6,e7,e8,e
9,e10,e11,e13,e14,e15,e16,e17;

assign p0=b[0]?a:0;
assign p1=b[1]?a:0;
assign p2=b[2]?a:0;
assign p3=b[3]?a:0;
assign p4=b[4]?a:0;
assign p5=b[5]?a:0;
assign s[0]=p0[0];
HA h1(s[1],d,p0[1],p1[0]);
HA h2(e5,d5,p1[5],p2[4]);
FA m1(e1,d1,p0[2],p1[1],p2[0]);
FA m2(e2,d2,p0[3],p1[2],p2[1]);
FA m3(e3,d3,p0[4],p1[3],p2[2]);
FA m4(e4,d4,p0[5],p1[4],p2[3]);
HA h3(e6,d6,p3[1],p4[0]);
HA h4(e11,d11,p4[5],p5[4]);
FA m5(e7,d7,p3[2],p4[1],p5[0]);
FA m6(e8,d8,p3[3],p4[2],p5[1]);
FA m7(e9,d9,p3[4],p4[3],p5[2]);
FA m8(e10,d10,p3[5],p4[4],p5[3]);
HA h5(s[2],d12,d,e1);
FA m9(e13,d13,d1,e2,p3[0]);
FA m10(e14,d14,d2,e3,e6);
FA m11(e15,d15,d3,e4,e7);
FA m12(e16,d16,d4,e5,e8);
FA m13(e17,d17,d5,e6,p2[5]);
HA h6(s[3],c[0],d12,e13);
HA h7(s[4],c[1],d13,e14);
HA h8(s[9],c[6],d10,e11);
HA h9(s[10],c[7],d11,p5[5]);
FA m14(s[5],c[2],d6,d14,e15);
FA m15(s[6],c[3],d7,d15,e16);
FA m16(s[7],c[4],d8,d16,e17);
FA m17(s[8],c[5],d9,d17,e10);
endmodule

Verilog Code for Carry Select Adder:

module uniformcarryadder(s0,s1,s2,i0,i1,i2,i3,i4,i5);
input [3:0] i0,i1,i2,i3,i4,i5;
output [3:0] s0,s1,s2;
wire[3:0] w0,w1,w2,w3,w4,w5;
wire w6,w7;
adder fa1(s0,s1,c0,c1,i0,i1);
adder fa2(s2,s3,c0,c2,i2,i3);
adder fa3(s4,s5,c4,c5,i4,i5);
mux m1(cc0,ss0,s0,c0,w0,w1);
mux m2(cc1,ss1,s2,c2,w2,w3,w6);
mux m3(cc2,ss2,s4,c4,w4,w5,w7);
endmodule
module adder(vs1,vvs1,vc0,vvc0,a,b);
input [3:0] a,b;
output [3:0] vc0,vs1;
output [3:0]vvc0,vvs1;
assign {vc0,vvs0}=a+b;
assign {vc1,vvs1}=a+b+1;
endmodule
module mux(cp,sum,s0,s1,c0,c1,cin);
input [3:0] s0,s1;
input c0,c1,cin;
output [3:0] cp,sum;
assign {cp,sum}= cin? {c0,s0}:{c1,s1};
endmodule