ME4953

Dual P-Channel 30V (D-S) MOSFET

GENERAL DESCRIPTION

FEATURES

The ME4953 is the Dual P-Channel logic enhancement mode power

RDS(ON)60m@VGS=-10V

field effect transistors are produced using high cell density, DMOS

RDS(ON)90m@VGS=-4.5V

trench technology. This high density process is especially tailored to

Super high density cell design for extremely low RDS(ON)

minimize on-state resistance. These devices are particularly suited

Exceptional on-resistance and maximum DC current

for low voltage application such as cellular phone and notebook

capability

computer power management and low in-line power loss are needed

APPLICATIONS

in a very small outline surface mount package.

Power Management in Note book

Portable Equipment
Battery Powered System
DC/DC Converter
Load Switch
DSC
LCD Display inverter

PIN CONFIGURATION
(SOP-8)
Top View

Absolute Maximum Ratings (TA=25 Unless Otherwise Noted)

Parameter

Symbol

Limit

Unit

Drain-Source Voltage

VDSS

-30

Gate-Source Voltage

VGSS

20

Continuous Drain

TA=25

Current(Tj=150)

TA=70

Pulsed Drain Current

Continuous Source Current (Diode Conduction)
Maximum Power Dissipation

TA=25
TA=70

-5.3

ID

-4.3

IDM

-30

IS

-1.7

2.0

PD

1.3

TJ

-55 to 150

Storage Temperature Range

Tstg

-55 to 150

Thermal Resistance-Junction to Ambient*

RJA

Thermal Resistance-Junction to Case

RJC

Operating Junction Temperature

T10 sec

47

Steady State

75
45

/W
/W

*The device mounted on 1in2 FR4 board with 2 oz copper

Apr,2008-Ver4.0
2007-Ver3.0
July,

01

ME4953
Dual P-Channel 30V (D-S) MOSFET
Electrical Characteristics (TA =25 Unless Otherwise Specified)
Symbol

Parameter

Limit

VGS(th)

Gate Threshold Voltage

VDS=VGS, ID=-250A

IGSS

Gate Leakage Current

Min Typ

Max

Unit

STATIC

IDSS

Zero Gate Voltage Drain Current

-1

-1.4

-3

VDS=0V, VGS=20V

100

nA

VDS=-30V, VGS=0V

-1
A

VDS=-30V, VGS=0V

-25

TJ=55
RDS(ON)
VSD

Drain-Source On-Resistance

VGS=-10V, ID= -5.3A

50

60

VGS=-4.5V, ID= -4.2A

69

90
-1.2

Diode Forward Voltage

IS=-1.7A, VGS=0V

-0.8

Rg

Gate resistance

VDS=0V, VGS=0V, f=1MHz

3.5

Ciss

Input capacitance

Coss

Output Capacitance

Crss

Reverse Transfer Capacitance

Qg

Total Gate Charge

m
V

DYNAMIC

Qgs

Gate-Source Charge

Qgd

Gate-Drain Charge

td(on)

Turn-On Delay Time

tr

Turn-On Rise Time

td(off)

Turn-Off Delay Time

tf

Turn-Off Fall Time

450
VDS=-15V, VGS=0V, f=1.0MHz

490

70

pF

20
14
VDS=-15V, VGS=-10V,
ID=-5.3A

17

nC

3
VDD=-15V, RL =15
ID=-1.0A, VGEN=-10V
RG=6

27

33

11

15

40

52

ns

Notes: a. Pulse test; pulse width 300us, duty cycle 2%

Apr,2008-Ver4.0
2007-Ver3.0
July,

02

ME4953
Dual P-Channel 30V (D-S) MOSFET
Typical Characteristics (TJ =25
Noted)

Apr,2008-Ver4.0
2007-Ver3.0
July,

03

ME4953
Dual P-Channel 30V (D-S) MOSFET
Typical Characteristics (TJ =25
Noted)

Apr,2008-Ver4.0
2007-Ver3.0
July,

04

ME4953
Dual P-Channel 30V (D-S) MOSFET

SOP-8 Package Outline

MILLIMETERS
DIM
MIN

MAX

1.35

1.75

A1

0.10

0.25

0.35

0.49

0.18

0.25

4.80

5.00

3.80

4.00

1.27 BSC

5.80

6.20

0.25

0.50

0.40

1.25

NNote: 1. Refer to JEDEC MS-012AA.

2. Dimension D does not include mold flash, protrusions
or gate burrs . Mold flash, protrusions or gate burrs shall not
exceed 0.15 mm per side.

Apr,2008-Ver4.0
2007-Ver3.0
July,

05