SRI ESHWAR COLLEGE OF ENGINGEERING

Coimbatore 641202
Academic year:
Department: Electronics and Communication Engineering
LESSON PLAN
Programme: B.E. ECE
Class:
Name of the course code/course:
Name of Faculty member: V.ANAND KUMAR
Lecture
Hours

Topics to be Covered

Text /
Reference
Book

Page No

Hours
required
as per
syllabus

Actual
hours
planned

9+3

10+3

9+3

10+3

Unit-I
CLASSIFICATION OF SIGNALS AND
SYSTEMS
Start Date :
End Date:
1
2
3
4
5
6
7
8
9
10
11

Introduction

Review of Fundamentals of CPU,

Memory and IO
Review of Fundamentals of CPU,
Memory and IO
Review of Fundamentals of CPU,
Memory and IO
Trends in technology, power, energy
and cost
Trends in technology, power, energy
and cost
Dependability
Dependability
Performance Evaluation
Performance Evaluation
Revision
Start Date :

12

Introduction

13

ILP concepts
Pipelining overview

14

Own notes

--

O1

O1

O1

4
17
21
33
33
36
36

End Date:
148
148

Date of
Lecture

Initial of
the
faculty
member

Initial
of the
HOD

Initial
of the
Principal

22

Compiler Techniques for Exposing ILP

Dynamic Branch Prediction
Dynamic Scheduling
Multiple instructions Issue
Hardware Based Speculation
Static scheduling - Multi-threading
Limitations of ILP
Case Studies, Revision

23

Unit-3
LINEAR TIME INVARIANTCONTINUOUS TIME SYSTEMS
Start Date :
End Date:
Introduction

15
16
17
18
19
20
21

33

Vector architecture
Vector architecture
Vector architecture
SIMD extensions
SIMD extensions
SIMD extensions
Graphics Processing units
Graphics Processing units
Loop level parallelism
Loop level parallelism , Revision

34

Start Date :
Introduction

24
25
26
27
28
29
30
31
32

35
36
37
38
39
40
41
42
43

148
162
176
197
183
233
213
247

264
264
264
282
282

9+3

10+3

9+3

10+3

282
288
288
315
315

Unit-4
End Date:

Symmetric and Distributed Shared

Memory Architectures
Symmetric and Distributed Shared
Memory Architectures
Performance Issues
Synchronization
Models of Memory Consistency
Models of Memory Consistency
Case studies: Intel i7 Processor
Case studies: SMT
Case studies: CMP Processors

366
366
366
386
392
392
166
412

44

Revision

45

Start Date :
Introduction

Unit-5
End Date:

54

Cache Performance
Reducing Cache Miss Penalty and Miss
Rate
Reducing Hit Time
Main Memory and Performance
Memory Technology. Types of Storage
Devices
Buses
Reliability, Availability and
Dependability
Reliability, Availability and
Dependability
I/O Performance Measures

55

Revision

46
47
48
49
50
51
52
53

Own notes

O1

-277

278
288
291
308

9+3

10+3

314
329
329
318

Content beyond the Syllabus Inverse Z transform (Text book T1 page No. 643)
Teaching aids: Blackboard /LCD / Moodle software /Models
TEXT BOOKS
1. Allan V.Oppenheim, S.Wilsky and S.H.Nawab, Signals and Systems, Pearson, 2007
REFERENCES
1. B. P. Lathi, Principles of Linear Systems and Signals, Second Edition, Oxford, 2009.
2. R.E.Zeimer, W.H.Tranter and R.D.Fannin, Signals & Systems - Continuous and Discrete, Pearson, 2007.
3. John Alan Stuller, An Introduction to Signals and Systems, Thomson, 2007.
4. M.J.Roberts, Signals & Systems Analysis using Transform Methods & MATLAB, Tata McGraw Hill, 2007.
5. A. Nagoor Kani Signals and Systems Tata McGraw Hill, 2010
6. P.Ramesh Babu & R.Anandanatarajan Signals and Systems SCITECH,2010

Faculty

HOD

Form No AC 08:Rev. No. 04:Rev.dt.10-02-2014

Principal