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ESE Online Test Series : 2015

Conventional Paper
E & T : ELECTRONICS & TELECOMMUNICATION ENGG.

TEST - 6 | Digital Electronic Circuits

Date: 01-03-2015 |

Subjectwise Test

Duration: 1 hrs.

Maximum Marks: 100

Read the following instructions carefully

1. Candidate should attempt any FOUR questions out of five. Each question carries 25 marks.
2. Marks carried by each subdivision of a question is indicated at the end of subdivision.
3. Answers must be written only in ENGLISH.
4. Assume suitable data, if necessary, and indicate the same clearly.
5. Neat sketches may be drawn, wherever required.
Copyright : MADE EASY

E & T Engineering Digital Electronic Circuits

Q.1 (a) Consider a digital ramp ADC with clock frequency = 1 MHz. VT = 0.1 mV; DAC has full scale
output = 10.23 V and 10 bit input. Find
(i) The digital equivalent obtained for VA = 3.7281 V
(ii) The conversion time.
[10 marks]
(b) Design a circuit to perform XNOR logic using only NOR gates.
[10 marks]
(c) Prove that the two open collector TTL inverters when connected together produce the NOR gate.
[5 marks]
Q.2 (a) Draw the circuit of an 8 bit D/A converter. Use 741 operational amplifier. If the value of the weighted
resistor corresponding to MSB is 1 k, note down the values of all the other resistors. The reference
voltage is 2.5 volt. The output voltage of the converter corresponding to full scale input is 5.0 volt.
What value of feedback resistor should be used in the operational amplifier? What should be the
tolerance of the resistor corresponding to MSB if the error in the converter output is to remain less than
1% of full scale value?
[15 marks]
(b) Explain the working of 5-stage twisted-ring counter
[10 marks]
Q.3 (a) The waveforms.
Set 1
Clear 1

are applied to the inputs of the latch

Set 1

Clear 1

Draw the waveform at Q and explain.

[15 marks]
(b) X and Y are successive digits in a positional number system. Also XY = (25)10 and YX = (31)10.
Determine the radix value of the system and values of X and Y.
[10 marks]
Q.4 (a) Minimize the following expression using K-map and realise it using NOR gate only.
f (A B C D ) = M (2, 7, 8, 9, 10, 12)
[10 marks]
(b) Design a MOD-10 synchronous counter using J - K flip-flops giving state diagram excitation table,
K-maps and circuit diagram.
[15 marks]

IOTET15

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ESE Online Test Series 2015 : Conventional Paper

Q.5 (a) Draw and explain the working of Half Adder circuit. If the input variables are A and B, then implement
the Half Adder circuit using 2 : 1 MUX.
[10 marks]
(b) Design a mod-6 counter to go through the sequence of states as given in the table below using S - R
flip-flop:
Sequence

Required State

No.

Sequence

Repeat from 0 0 0

Show the state table indicating the present state, the next state for each present state along with the
input requirements of each of the S and R inputs. Show clearly the minimization of logic requirements
using K-maps. Write the logical expressions for each excitation input of all the flip-flops. Draw the logic
diagram of the counter designed by you.
[15 marks]

Delhi

Noida

Bhopal

Hyderabad

Jaipur

Lucknow

Indore

Pune

Bhubaneswar

Kolkata

IOTET15