Introduction to the ECE5745 ASIC Toolflow

ECE5745 Tutorial 0 (Version 606ee8a)

January 30, 2016
Derek Lockhart

Contents
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6
7
8
9
10
11

Introduction . . . . . . . . . . . . . . . . . . . . . . . .
Synopsys VCS . . . . . . . . . . . . . . . . . . . . . . .
Synopsys Design Compiler . . . . . . . . . . . . . . . .
Synopsys IC Compiler . . . . . . . . . . . . . . . . . .
Synopsys PrimeTime PX. . . . . . . . . . . . . . . . .
Synopsys 90nm Educational Libraries and Process .
DesignWare Library . . . . . . . . . . . . . . . . . . . .
Verilog Hardware Description Language . . . . . . .
File Extension Reference . . . . . . . . . . . . . . . . .
Terminology . . . . . . . . . . . . . . . . . . . . . . . .
Acknowledgements . . . . . . . . . . . . . . . . . . . .

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Introduction

In this tutorial you will learn what each VLSI tool used in class is meant to do, how the tools flow together,
and what the file extensions are for the inputs and outputs of each tool.
Figure 1 shows the toolflow you will be using for the labs in class.
1. You will use Synopsys VCS (vcs) to simulate and debug your RTL design. VCS is a commercial tool
similar to the iverilog program you used in ECE4750.
2. After you get your design right, you will use Synopsys Design Compiler (dc_shell-xg-t) to synthesize
the design. Synthesis is the process of transforming an RTL model into a gate-level netlist.
3. Once you have a working gate-level netlist, you will use Synopsys IC Compiler (icc_shell) to place and
route the design. Placement is the process by which each standard cell is positioned on the chip, while
routing involves wiring the cells together using various metal layers. The tools will provide feedback
on the performance and area of your design after both synthesis and place and route. The results from
place and route are more realistic, but require much more time to generate.
4. After place and route, you will perform gate-level simulation as a final test for correctness and to
generate transition counts for every net in the design.
5. Synopsys PrimeTime PX (pt_shell) takes the transition counts generated from gate-level simulation as
input and correlates them with the capacitance values in the final layout to produce estimated power
measurements
The table below highlights the five major subcomponents of our flow, the primary tool utilized in each
subcomponent, and the shorthand we use to refer to that subcomponent in our build system.

(Version 606ee8a), Spring 2013

Verilog
Source
(.v)

Verilog
Testbench
(.v)

Standard
Cell Models
(.v)

Standard Cell
Library
(see below)

Constraints
(.tcl)

TLU+ Files
(.tluplus)

Design
Compiler

iverilog

VCS

RTL
Simulator
(a.out)

RTL
Simulator
(simv)

Delay File
(.sdf)

./a.out

./simv

VCS

Test
Results
(.out)

Waveform
(.vpd or
.vcd)

RTL
Simulator
(simv)

GTKWave

./simv

Test
Results
(.out)

Waveform
(.vcd)

IC
Compiler

Gate Level
Netlist
(.v)

Timing &
Area

Constraints
File
(.sdc)

Design
Vision GUI

IC
Compiler

Parasitics
(sbpf.min,
sbpf.max)

Gate Level
Netlist
(.v)

Delay File
(.sdf)

Floor Plan

Constraints
File
(.sdc)

Timing &
Area

Layout

IC
Compiler
GUI

VCS

Post-P&R
Simulator
(simv)
Standard Cell Library:

RTL Simulation

Technology Library (.db)

Milkyway Reference DB (.fr)
Technology File (.tf)
Mapping File (.map)

./simv

GTKWave

Test
Results
(.out)

Waveform
(.vcd)

Synthesis
Place & Route
Gate-Level Simulation

GTKWave

VCD2SAIF

Power Estimation
(Optional Flow Elements)
Activity File
(.saif)

Figure 1: ECE5745 Toolflow

PrimeTime

Power
Estimates

(Version 606ee8a), Spring 2013

vcs-sim-rtl
dc-syn
icc-par
vcs-sim-gl-par
pt-pwr

Synopsys
Synopsys
Synopsys
Synopsys
Synopsys

3
VCS
Design Compiler
IC Compiler
VCS
PrimeTime PX

RTL simulation
Synthesis; RTL to gate-level netlist
Place and Route; gate-level netlist to layout
Post place and route gate-level simulation
Power analysis

Note that in the diagram there are a few optional paths in the flow:
Instead of using VCS to simulate and debug your design (subflow 1), it is possible to use iverilog as
we did in ECE4750. Note that some Verilog constructs that compile successfully in iverilog are not
supported in VCS, and vice versa. Because of this, we highly recommend doing your designs in VCS
rather than iverilog.
After performing synthesis (subflow 2), it is sometimes useful to perform post-synthesis gate-level
simulation. The results of this simulation arent really used, but it can be useful for debugging and
sanity checking that your synthesized design functionally matches your RTL simulation.
Before performing place and route (subflow 3), a design can optionally be floorplanned. Floorplanning
arranges logical functional blocks on a chip in order to help reduce wire lengths and improve routability
for the place-and-route tools. If we have time, we will talk about this process in more detail later in
the semester.

Synopsys documentation is located on the public course webpage (http://www.csl.cornell.edu/courses/ece5745/syndocs

and can be accessed using the username and password distributed in lecture.

Synopsys VCS

VCS is used to simulate hardware designs, similar to what iverilog was used for in ECE4750. Although VCS
accepts designs expressed in several different Hardware Description Languages (HDLs), we will exclusively
be using Verilog for this class. VCS takes a set of HDL files as input and as an output produces an executable
simulator.
Once we have a simulator for a design, we can use it to determine the designs execution time in cycles, as
well as verify its functionality. VCS will most often be used during the iterative implement/debug process
encountered when writing RTL for new hardware, or when modifying existing hardware. However, it will
also be used later in the flow to simulate gate-level models of our designs. These gate-level simulations are
necessary to obtain switching behavior, which are used to perform power and energy analysis.
The VCS generated simulator can provide us with information about our designs behavior in one of two ways:
either via print statements produced by the simulator via the commandline, or signal transition information
dumped into a separate file. Print statements are most useful for quickly verifying which unit tests a design
is currently passing or failing, or to get the execution time in cycles of the design, while signal transition
information is typically used when debugging a problem.
The standard format for signal transition trace information is a textual file called the Value Change Dump
format (VCD). Unfortunately, these textual trace files can become very large quickly, so Synopsys tools can
also produce a proprietary compressed binary trace format called VCD Plus (VPD). You can view VPD files
using the Synopsys Discover Visual Environment (DVE) waveform viewer. For this class, we will primarily
be using VCD rather than VPD so that we can analyze waveforms using GTKWave.

(Version 606ee8a), Spring 2013

Synopsys Design Compiler

Design Compiler takes an RTL hardware description, timing constraints, and a standard cell library as
input and produces a gate-level netlist as output. Internally, a synthesis tool performs many steps including
high-level RTL optimizations, RTL to unoptimized Boolean logic, technology independent optimizations,
and finally technology mapping to the available standard cells.
One important thing to keep in mind is that a synthesis tool is only as good as the standard cells which
it has at its disposal. The standard cell library we will be using for the course is the Synopsys 90nm
Educational libraries, which are discussed in more detail later in the document. Although these are great
cells for educational purposes, they are not fabrication ready.
After synthesis completes, Design Compiler can generate reports containing area and power estimates, a
resource mapping breakdown, and most importantly the critical path of your synthesized design. You can
also take advantage of the Synopsys Design Vision GUI to visualize critical paths of your synthesis results
and view schematics of the gate-level netlist.

Synopsys IC Compiler

IC Compiler takes as input a gate-level netlist, timing constraints, physical and timing libraries, and as
output generates a layout. IC Compiler performs two important steps when producing a layout: placement
and routing.
Placement first determines how each gate should be placed on the chip. Routing will then wire these gates
gates together, using heuristic algorithms to group together related gates and tweak placement in order to
minimize routing congestion and wire delay. IC Compiler focuses its effort on minimizing the delay through
the critical path, and will resize gates, insert new buffers, and even perform local resynthesis to achieve this
goal.

Synopsys PrimeTime PX

PrimeTime PX is an add-on feature to the PrimeTime Static Timing Analysis tool that accurately analyzes
power dissipation of cell-based designs. PrimeTime PX supports two types of power analysis: averaged mode
and time-based mode. Averaged mode calculates averaged power based on toggle rates. Time-based mode
lets you know the peak power as well as the averaged power using gate-level simulation activity.

Synopsys 90nm Educational Libraries and Process

For the class we will be using the Synopsys 90nm Educational Library, which is a 1P9M (1 poly, 9 metal
layers) 1.2V/2.5V process.
The standard cell library includes multiple drive strength implementations for the typical combinational and
sequential logic cells used in digital design: ANDs, ORs, NANDs, NORs, latches, flip-flops and more. In
addition, the cell library contains miscellaneous cells required for various styles of low-power (multi-voltage,
multi-threshold) design. These cells include isolation cells, level shifters, retention flip-flops, always-on
buffers, and power gating cells.
Although the Synopsys educational library does not come with a memory compiler, this course will (hopefully) make use of an alternative SRAM model compiler that works with the ECE5745 toolflow. More
information about the memory compiler will be made available later in the course.

(Version 606ee8a), Spring 2013

DesignWare Library

The DesignWare Library is a collection of reusable circuit-design building blocks that are tightly integrated
into the Synopsys synthesis environment. These DesignWare components implement many of the built-in
HDL operators provided by Verilog, such as +, , , <, >, <=, >=, and the operations defined by if and
case statements.

Verilog Hardware Description Language

The ECE5745 toolflow supports Verilog. For language specifications consult the following documents.

File Extension Reference

*.v - Verilog source file. Normally a source file you write. Design Compiler, and IC Compiler can use
this format for the gate-level netlist.
*.vg, *.g.v - Sometimes this extension is used to distinguish Verilog gate-level netlists from Verilog
source files.
*.ddc - Synopsys internal database format. This format is recommended by Synopsys to handld
gate-level netlists.
*.vcd - Value Change Dump format. This format is used to save signal transition trace information.
VCD files are text files, and therefore trace files in this format can quickly get very large Tools like
vcd2vpd, vpd2vcd, and vcd2saif can be used to switch back and forth between different formats.
*.vpd - VCD Plus. This is a proprietary, compressed binary trace format from Synopsys. This file
format is used to save signal transition trace information.
*.saif - Switching Activity Interchange Format. This is another format to save signal transition trace
information. SAIF files support signals and ports for monitoring as well as constructs such as generates,
enumerated types, records, array of arrays, and integers.
*.tcl - Tool Command Language (Tcl) scripts. Tcl is used to drive Synopsys tools.
*.sdc - Synopsys Design Constraints. SDC is a Tcl-based format so all commands in an SDC file must
conform to the Tcl syntax rules. SDC files are used to communicate design intent, including timing
and area requirements between EDA tools. An SDC file typically contains the following information:
SDC version, SDC units, design constraints, and comments. Consult dc-application-note-sdc.pdf
for further information.
*.sdf - Standard Delay Format. An SDF file stores the timing data generated by the tools for use
at any stage in the design process. The data in the SDF file is represented in a tool-independent way
and can include delays, timing checks (including setup time, hold time), timing constraints, timing
environment, incremental and absolute delays, conditional and unconditional module path delays and
timing checks, etc.
*.lib - Technology Library source file. Technology libraries contain information about the characteristics and functions of each cell provided in a semiconductor vendors library. Cell characteristics
include information such as cell names, pin names, area, delay arcs, and pin loading. In addition to cell
information, technology libraries also specify design rule constraints, which define the conditions which
must be met for a functional design to operate correctly (for example, the maximum transition time
for nets). The technology file also defines the operating conditions and wire load models specific to the
particular technology. Technology libraries are typically maintained and distributed by semiconductor
vendors, for example, the technology library used in this course is provided by Synopsys.
*.db - Technology Library. This is a compiled version of the *.lib file in Synopsys database format.
*.plib - Physical Library source file. Physical libraries contain process information and physical
layout information about the cells. This information is required for floor planning, RC estimation and
extraction, placement, and routing.

(Version 606ee8a), Spring 2013

*.pdb - Physical Library. This is a compiled version of the *.plib file in Synopsys database format.
*.slib - Symbol Library source file. Symbol libraries contain definitions of the graphic symbols that
represent library cells in the design schematics. Design Compiler uses symbol libraries to generate
the design schematic, which can be viewed in Design Vision. Symbol libraries are maintained and
distributed by Semiconductor vendors.
*.sdb - Symbol Library. This is a compiled version of the *.slib file in Synopsys database format.
*.sldb - DesignWare Library. This file contains information about DesignWare libraries.
*.def - Design Exchange Format. This formats is often used in Cadence tools to represent physical
layout. Synopsys tools normally use Milkyway format to save designs.
*.lef - Library Exchange Format. Standard cells are often saved in this format. Cadence tools also
often uses this format. Synopsys tools normally use Milkyway format for standard cells.
*.rpt - Design reports. These are textual files generated by the Synopsys tools when using the
automated makefiles and scripts.
*.tf - Vendor Technology File. This file contains technology-specific information such as the names
and characteristics (physical and electrical) for each metal layer, as well as the design rules for the
technology. This information is required to route a design.
*.itf - Interconnect Technology File. This file contains a description of the process cross-section and
connectivity section. It also describes the thicknesses and physical attributes of the conductor and
dielectric layers.
*.map - Mapping file. This file aligns names in the vendor technology file with the names in the process
*.itf file.
*.tluplus - TLU+ file. These files are generated from the *.itf files. TLUPlus models are a set of
models containing advanced process effects that can be used by the parasitic extractors in Synopsys
place-and-route tools for modeling.
*.spef - Standard Parasitic Exchange Format. File format to save parasitic information extracted by
the place and route tool.
*.sbpf - Synopsys Binary Parasitic Format. A Synopsys proprietary compressed binary format of the
*.spef file.
Milkyway database
The Milkyway database consists of libraries that contain information about your design. These libraries
contain information about design cells, standard cells, macro cells, physical descriptions (metal, diffusion, and polygon geometries), logical information (functionality and timing characteristics) for every
cell in the library, and technology information required for design and fabrication.
Milkyway provides two types of libraries that you can use: reference libraries and design libraries.
Reference libraries contain standard cells and hard or soft macro cells, which are typically created
by vendors. Reference libraries contain physical information necessary for design implementation.
Physical information includes the routing directions and the placement unit tile dimensions, which is
the width and height of the smallest instance that can be placed.
A design library contains a design cell, which may contain references to multiple reference libraries
(standard cells and macro cells). A design library may also be a reference library for another design
library.
The Milkyway library is stored as a UNIX directory with subdirectories, and every library is managed
by the Milkyway Environment. The top-level directory name corresponds to the name of the Milkyway
library. Library subdirectories are classified into different views containing the appropriate information
relevant to the library cells or the designs.
In a Milkyway library there are different views for each cell, for example, NOR1.CEL and NOR1.FRAM.
This is unlike a .db formatted library where all the cells are in a single binary file. With a .db library,
the entire library has to be read into memory. In the Milkyway Environment, the Synopsys tool loads
the library data relevant to the design as needed, reducing memory usage. The most commonly used
Milkyway views are CEL and FRAM. CEL is the full layout view, and FRAM is the abstract view for place
and route operations.

(Version 606ee8a), Spring 2013

simv - Compiled simulator. This is the output of vcs. In order to simulate, execute the simulator by
running ./simv at the command line.
alib-52 - characterized target technology library. A pseudo library which has mappings from Boolean
functional circuits to actual gates from the target library. This library provides Design Compiler
with greater flexibility and a larger solution space to explore tradeoffs between area and delay during
optimization.

10

Terminology

The Design Compiler User Guide has a good glossary on general VLSI terminology. If you are not familiar
with the following keywords, we encourage look them up in the glossary, as you are likely to see many of
these terms used in the labs and tutorials for the course.

11

annotation
back-annotate
cell
clock
clock gating
clock latency
clock skew
clock source
clock tree
clock uncertainty
core
critical path
datapath
current design
current instance
design constraints
false path
fanin
fanout

fanout load
flatten
forward-annotate
generated clock
hold time
ideal clock
ideal net
input delay
instance
leaf cell
link library
multicycle path
netlist
operating conditions
optimization
output delay
pad cell
path group
pin

propagated clock
real clock
reference
RTL
setup time
slack
structuring
synthesis
symbol library
target library
technology library
timing exception
timing path
transition delay
ungroup
uniquify
virtual clock
wire load model

Acknowledgements

Many people have contributed to versions of this tutorial over the years. The tutorial was originally developed
for CS250 VLSI Systems Design course at University of California at Berkeley by Yunsup Lee. Contributors
include: Krste Asanovi, Christopher Batten, John Lazzaro, and John Wawrzynek. Versions of this tutorial
have been used in the following courses:
CS250 VLSI Systems Design (2009-2011) - University of California at Berkeley
CSE291 Manycore System Design (2009) - University of California at San Diego