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7. Click on Edit New Facet Instance. Choose library Exercise. Select NOR_sch{ic}
from this library. Click on the design window.
Note: Lp, Ln = 0.35m; Wp = 3.2m; Wn = 0.8m
Figure 3-b. Schematic diagram for the transient analysis of a NOR gate.
Note:
loadcap = 100fF
SPICE card for DC DC 3.3
SPICE card for Input A PULSE(0 3.3 0 1n 1n 100n 200n)
SPICE card for Input B PULSE(0 3.3 50n 1n 1n 100n 200n)
SPICE card for Transient Analysis 5p 500n 0 5p
9. Create a SPICE netlist of your circuit. Simulate the circuit using WinSpice. Verify if
the circuit is working properly by referring to the truth table of a NOR gate (Table 3-a).
Va
0
0
1
1
Vb
0
1
0
1
Vout (NOR)
1
0
0
0
Vout (NAND)
1
1
1
0
10. Fill-up the table below. Round off your answers to two decimal places.
WN
0.80m
0.80m
0.80m
WP
3.20m
1.60m
0.80m
PHL
PLH
11. Repeat procedures 3 - 9 for a NAND gate (Figure 3-c and 3-d). Verify if the circuit is
working properly by referring to the truth table of a NAND gate (Table 3-a).
Note: Lp, Ln = 0.35m; Wp = 3.2m; Wn = 1.6m
12. Fill-up the table below. Round off your answers to two decimal places.
WN
1.60
1.60
1.60
WP
3.20
1.60
0.80
PHL
PLH
Note: Refer to Exercise 2 for the determination of the PHL and PLH.
Figure 3-d. Schematic diagram for the transient analysis of a NAND gate.