Professional Documents
Culture Documents
Computer Organization
and Architecture
6th Edition
Chapter 7
Input/Output
7.1
7.2
7.3
7.4
7.5
7.6
7.7
External Devices
I/O Modules
Programmed I/O
Interrupt-Driven I/O
Direct Memory Access
I/O Channels and Processors
The External Interface
Input/Output Module
Input/Output Problems
Wide variety of peripherals
Delivering different amounts of data
At different speeds
In different formats
2 kinds of interface
Interface to the processor and memory via the
system bus
Interface to one or more peripheral devices by
tailored data links
Human readable
Machine readable
Magnetic disks
Monitoring and control (sensor)
Communication
Modem
Network Interface Card (NIC)
Keyboard
Monitor
IRA code characters are transmitted to an external device
from I/O module, and the transducer at the device interprets
this and sends the required electronics to the output device
Disk Drive
Contains electronics for exchanging data, control and status
signal w/ I/O module and electronics for disk read/write
mechanism
Module structure
I/O steps
1. Processor checks the status of attached device
thru I/O module
2. I/O returns the status of device
3. The processor request data transfer to the I/O
module
4. I/O module obtains data from the device
5. The data is transferred from I/O module to the
processor
Processor communication
E.g. I/O module should communicate with the
processor and external device
Command decoding
READ SECTOR for disk drive
Data
between I/O module and processor over bus
Status reporting
Busy / Ready for requested job
Address recognition
Recognize one unique address for each peripheral it controls
Data buffering
Difference rate in the transfer rate between
memory/processor and device
Error detection
Mechanical and electrical error
Parity bit
Programmed I/O
Sensing status
Read/write commands
Transferring data
I/O Commands
Read/Write
Module transfers data via buffer from/to device
I/O Mapping
Isolated I/O
Separate address spaces
Need I/O or memory select lines
Special commands for I/O
Limited set
CPU Viewpoint
Issue read command
Do other work
Check for interrupt at end of each instruction
cycle
If interrupted:Save context (registers)
Process interrupt
Fetch data & store
Design Issues
Software poll
CPU asks each module in turn
TESTI/O command
The processor reads the status register of each I/O module
Slow
Bus Master
Module must claim the bus before it can raise
interrupt
When CPU detects interrupt, it responds on the
interrupt Acknowledge line. Then the requesting
module places its vector on the data line
e.g. PCI & SCSI
DMA Function
DMA Operation
Read/Write
Device address
Starting address of memory block for data
Amount of data to be transferred
DMA Transfer
Cycle Stealing
DMA controller takes over bus for a cycle
Transfer of one word of data
Not an interrupt
CPU does not switch context
Then,
What effect does caching memory have on
DMA?
Hint: how much are the system buses
available?
DMA mechanism can be configured in a variety
of ways
Parallel interface
Serial interface
I/O module to/from peripheral (write op.)
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Point-to-point
Keyboard
Printer
External modem
FireWire Configuration
Daisy chain
Up to 63 devices on single port
Really 64 of which one is the interface itself
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Physical
Transmission medium, electrical and signaling
characteristics
Link
Transmission of data in packets
Transaction
Request-response protocol
Fair arbitration
Urgent arbitration
Asynchronous
Variable amount of data and several bytes of transaction
data transferred as a packet
To explicit address
Acknowledgement returned
Isochronous
Variable amount of data in sequence of fixed size packets at
regular intervals
Simplified addressing
No acknowledgement
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FireWire Subactions
7.7.4 InfiniBand
I/O specification aimed at high end servers
Merger of Future I/O (Cisco, HP, Compaq, IBM) and
Next Generation I/O (Intel)
InfiniBand Architecture
Up to 30Gbps
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InfiniBand Operation
Foreground Reading
Check out Universal Serial Bus (USB)
Compare with other communication standards
e.g. Ethernet
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