EE 227 Non-Volatile Memory HW: U Ganguly: Autumn 2015;

Please submit only in typed pdf for HW only.

1. In a Floating Gate MOSFET, the tunnel oxide is 8nm SiO2, IPD is 12nm of SiO2 with a 3x area
compared to tunnel oxide.
a. Given that channel and control gate are grounded (and assumed to be metallic for
simplicity). When charge (in C/cm2) is stored in the floating gate, model the Flash
memory gate stack as a capacitor network. What is the electron density that needs to be
stored in the floating gate for a 1V potential on it?
b. Plot number of charges per floating gate vs. technology node (i.e. channel length). You
may use MATLAB or other equivalent software.
c. What is the number of charges per floating gate at 25nm node?
d. If we are specified to lose less than 10% charge in 10 years, calculate the maximum
leakage current specification in Amps?

CONTROL GATE

SOURCE

DRAIN
CHANNEL

Tun
Ox

Control
Gate

TOX or TD

Floating
Gate

FG

Channel

CD or IPD

IPD

2. A programming bias of 18V is applied to the control gate of the above device.
a. Draw the band diagram approximately to scale (use x-axis and y-axis grids).
b. Calculate the electric field in the tunnel oxide and IPD when there is no charge on
Floating Gate.
c. When charge (in C/cm2) is stored in the floating gate, using the model in problem 1,
calculate the electric field only due to stored charge when control gate and channel are
assumed metallic and grounded.
d. Can superposition be used to calculate electric field when both control gate has a bias
and floating gate has stored charge? If so calculate the charge at which electric field in
tunnel oxide and IPD is equal. You may solve this graphically by plotting charge vs. Efield in tunnel oxide and IPD by MATLAB or other suitable program. Argue that this is the
maximum charge that can be stored in a floating gate by using triangular barrier (also
known as Fowler Nordheim or FN) tunneling.

3. Explain with band diagrams why a bilayer tunnel oxide has higher non-linearity in J(V) compared
to single layer tunnel oxide. What is high non-linearity in J(V) required in the tunnel oxide. In
comparison what is the requirement of IPD.
4. There are a few differences between NAND and NOR Flash
a. Explain briefly, what is the difference between NAND and NOR Flash device.
b. Argue that NAND Flash, uses lower power to program/erase even though it uses 18V
(i.e. 2x higher bias than NOR); however it is slower than NOR.
c. Argue that NOR has lower device density.
5. A new technology called X-Point was recently (July 2015) announced by Micron Inc based on
RRAM that promises a 100ns program/erase and 10 years retention. It plans to provide a nonvolatile DRAM capability. See http://www.micron.com/about/innovations/3d-xpointtechnology
a. Why is Resistance Random Access Memory (RRAM) more scalable than Flash Memory?
Explain.
b. RRAM requires a selection device. What should be the half-selected current
requirement vs. array size?