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COMPUTER ORGANIZATION

CONTENT

1. CPU ORGANIZATION & DESIGN .

05-24

2. MICROPROGRAMMED CONTROL UNIT.

25-28

3. INPUT OUTPUT ORGANIZATION...

29-43

4. PIPELINING.....

44-56

5. MEMORY ORGANISATION .......

57-78

6. PC-PERSONAL COMPUTER AND THEIR USES

79-101

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COMPUTER ORGANIZATION

CHAPTER-1
CPU ORGANIZATION & DESIGN
CPU (Central Processing Unit) is made up of three major parts:
1. Arithmetic and Logic Unit (ALU)
2. Control Unit (CU) and
3. Processing Registers
ALU is used to perform the required Arithmetical and logical operation under the directions of control unit.
Control Unit supervises the transfer of information among the Registers and instructs the ALU that which
operation has to be perform.
Processing Registers are used to store the data during execution
The Computer instruction set provides the specifications for the design of the CPU.
Control Word: It is a binary word that is generated by the CPU to perform one of the various operations.
Control Register: It is used to store the control word.

If the length of the control word is n bit, total no. of operations that can be used to perform 2n ; ranges
from 00----0 (n) to 1-----1(n) and each combination is used to assign one operation.
Micro operation : It is an operation executed on data stored in registers. Micro operation is a basic register to
register operation.
Instruction is divided into 2 parts:
1. Operation part (most side)
2. Operand part (least side).
For n address b1it CPU total no. of memory location to be accessed is 2n and each memory location is able to
store 1 word.
Length of the word varies from one CPU to other and depends on the no. of data bits that can be transferred
at a time (i.e. word size is equal to the no. of data bits a CPU has)
The total memory is divided in to 2 parts namely
1. User memory
2.Stack memory
User memory is under the control of only user, but stack memory is under the control of both CPU and user.
Different ways for performing the Arithmetical operations:
1. Infix notation (Ex : A+B)
2. Prefix or polish (Ex : +AB)
3. Reverse polish notation (Postfix) (Ex: AB+)
Stack works on postfix.
Conversion of Infix to RPN
Ex: 1 A B C D
= ( AB) CD = AB CD +

Ex: 2 ( A B ) [C ( D E ) F ]
First complete the inner side of small bracket parenthesis and then big bracket parenthesis.
= ( AB )[C ( DE ) F ] =
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COMPUTER ORGANIZATION
= ( AB )[ DE C F ] = AB DE C F

( AB ) (CDE ) F
( AB ) CDE F
AB CDE F
Conversion of RPN to Infix
Ex:1 AB CD
= ( AB) (CD)

= ( A B ) (C D )
= AB CD
Ex: 2 AB DE C F
= ( A B ) [C ( D E ) F ]
RPN is used in some electronic calculators
Before evaluating the operation, the arithmetic expression must be converted into RPN, the operations are
pushed on to stack in the order in which they appear.
Numerical example : for the data (3 4) (5 6) using RPN

34 56
Stack operations :

Compliers generally work on polish notation.

In scientific calculators, some operations are performed with RPN and others with
Polish notation.

The bits of the instructions are divided into 2 fields, called as Operation field and Operand field.

Again operand field is divided in to


1. Address field
2. Mode field.
Operands residing in the memory are specified by their memory address
Operands residing in the processing Registers are specified with a Register address (name)
In any system; if k bits are used to specify the address of the Register, then the same CPU has 2k no. of
registers (max. no.)
The no. of address fields in the instruction format of a computer depends on the internal organization of its
registers.
Instruction Cycle:
It shows the execution sequence of an instruction. It consists of two sub cycles.
1) Fetch cycle
2) Execution cycle

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Instruction fetch operation takes place in the fetch cycle. Process of transferring a binary sequence using program
counter from memory to CPU called as instruction fetch.
At the end of instruction fetch program counter is incremented to next instruction address.
Memory

PC Binary seq. C.P.U


PC PC + step size

After transferring a binary sequence to the CPU execution cycle is trying to process the instruction. To process the
instruction there is a need of identifying the associated operation. Type of operation is identified by OPCODE.
OPCODE information is given by instruction format.
CPU Organization:
Classification is done on the basis of internal storage.
1) Stack organization
2) Accumulator based machine
3) General register organization
1)

Stack organization:
It uses push & POP instructions.

Instruction format - opcode

Push x means, the word at the address of the x is pushed to the top of the stack memory.
In this operation, instruction doesnt use an address field in the stack organized computer, because the
specified operation is performed on the two items that are on the top of the stack.
It is a storage device that stores the information in such a manner that the item stored last is the first
item to retrieve. Means LIFO (Last in first out)
The register that holds the address of the stack is known as stack pointer.
Push and pop are used to access stack memory.
For accessing 2n words stack memory, the length of the (stack pointer) required is n bits.

Always, SP is pointed at top of the stack; it is decremented during push operation and incremented during
pop operation.
In 8085 for pushing pre decrement and for poping post increment
2 no. of flags are used to know the status of the stack: 1. Empty 2. Full
Initially, stack cleared to 0. So EMPTY is set and Full is cleared.
If all memory locations are filled in the stack; then empty flag resets and Full flag sets.
But most computer do not provide hardware for checking over flow (Full stack) or under flow (empty stack);
In this case the stack limits can be checked by using 2 processing Registers.
One to hold the upper limit and other to hold the lower limit address
After PUSH operation; SP is compared with the upper limit Register (SP is stack pointer)
After POP operation SP is compared with the lower limit register

2)

Accumulator based machine: (Advantage: length of the opcode is low, so it can be executed at
rate.)
In this all operations are performed with an implied accumulators
It has only one address field. Instruction format:

opcode

Address

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Ex: ADD x
SUB x
where x is the address of the operand
3)
General Register organization: (Length of the OP code is more)
The instruction format needs 3 Register address fields or 2 Register address fields.
Ex: ADD R1, R2, R3
R1=R2+R3

For data transfer MOV operations, it requires 2 no. Registers.


Ex: MOV R1, R2
For Arithmetical; 3 Register Required
For Data transfer; 2 Register Required
Depending on the length of the operand, instructions are divided as follows:

Instruction based on number of addresses


There are 5 type of instruction based on address:
(i)
(ii)
(iii)
(iv)
(v)

4 address instruction
3 address instruction
2 address instruction
1 address instruction
0 address instruction.

(i)

4 address instruction
In the 4 address instruction, we have to specify 4-address, in which first address that is close to OP code
determines the result and the last address determines the address of the next instruction.

For example: ADD A1 A2 A3 A4


In this we performed the addition of M[A2] and M[A3] and the result is stored in M[A1]. Here A4
contains the address of next instruction.
(ii)

(iii)

3 address instruction
In the 3 address instruction, we have to specify 3 address in which the first address that is close to OP
code determines the result of operation.
Example:
ADD A1, A2 A3
First we performed the M[A2] + M[A3]
Next move the reject to A1.
M[A1] M[A2] + M [A3]
2-address Instruction
In the case of two address instruction, the accumulator is used to store the result.
Example:
ADD X, Y
It represents
AC: X + Y
In the 2 address instruction another position is there without using accumulator for example:
ADD X, Y
It can be performed as:
X: = X + Y
The addition operation stored the result into X.

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(iv)

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1-address instruction
In the one address instruction we use accumulator. The unspecified operands are assumed to be stored
in AC (Accumulator)

For example:
ADD X
It performed as
AC: = AC + X
(v)

0 address instruction
A few computers name teen designed so that most instruction contain no explicit address; they can be
called as zero address machine
All operands used by a zero address instruction are required to be in the top location in the stack.

Example: ADD
That causes the top two operands which should be X and Y, to be removed from the stack and
addressed the resulting sum X + Y is then placed at the top of the stack.
Addressing Modes
It is the way of locating the data in the operand field.
The control unit of a computer is designed to go through the instruction cycle that is divided into 3 major
phases (steps)
1. Fetch the instruction from memory
2. Decode the instruction and Execution
Program counter is used to store the address of the next instruction to be executed, and it is incremented
each time to step size to point the next instruction.
The step-size is depending on the length of instruction.
Decoding done in step 2 determines the operation to be performed and addressing mode of the instruction.
Then computer executes the instruction and returns to the step 1 to fetch the next instruction.
So, to know about the functions of decoding unit, it is compulsory to know about the addressing modes.
Different Addressing Modes (AM)
Implied AM: It has no operand field
Eg: CMA, HLT, NOP, and
All zero address instruction
It is also known as implicit (AM)
Immediate AM: In this operand part is nothing but data. This AM is used to access the constants.
These are useful for initializing Register for constant values
Ex: MOVI AX, 1234H, Add 0 #23 [# and I Denotes Immediate AM].
Register AM: In this operand field must be specified with Register
Ex: 1.MOV AX, BX 2. ADD, CX, DX
Register indirect: In this, the specified register in the CPU whose content gives the address of the operand in the
memory.
Ex: MOV AX, [BX]
ADD AX, [BX]
In this example BX register is used to store the address of the operand i.e. content of the BX register acts as

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Effective Address (EA)


Effective address is an address where data is available.
Direct Addressing mode: In this EA=Address of the instruction (In branch type instruction, the address field
specifies the actual branch address)
Ex: MOV AX [5555H]
JMP 2500H
Indirect Addressing mode: In this, address field of the instruction gives the address where the effective address is
stored in the memory.
Relative Addressing mode: In this, the content of the pc is added to the address part of the instruction in order to
obtain the effective address
Ex: ADD AX,[+25,BX]
EA=BX+25
Indexed Addressing mode: In this mode the content of the Index register is added to the address part of the
instruction to obtain the EA.
Index Register is a special CPU register.
Auto increment or Auto decrement Addressing mode: This is similar to the indirect mode except that the register
is incremented or decremented after its value is used to access memory. This mode is used to Access the Linear
Array Elements.
Base Register Addressing Mode: In this mode the content of a base register is added to that address part of the
instruction to obtain the effective address.
This is similar to the index AM except that the register is now called a base register instead of an Index register.
NOTE: It is same as the register indirect mode except that is incremented to 401 after the instruction execution
but in Auto decrement mode it is decremented prior to the execution.

Classification of Instruction Sets: Instruction set indicate the no of possible operation in the processor.
The processor supports 3-category of operation:
1. Data transfer
2. Data Manipulation
3. Transfer of control (program control
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Data transfer Instructions:


These are used to transfer the data from one place to other place without changing the data content.
LD
Load
ST
Store
MOV
Move
XCH
Exchange
IN
Input
OUT
Output
PUSH
Push
POP
Pop
Data manipulation Instructions: While execution of this instruction one from of data is converted into another
form.
These are used to perform various operations on data
Again these are divided as follows:
a. Arithmetical b. Logical
c. Shift
Arithmetical
INC
Incrementing
DEC
Decrementing
ADD
Addition
SUB

Subtraction

SUBB
MUL
DIV
ADDC

Subtract with borrow


Multiplication
Division
Add with carry

NEG

2s Complement

Logical & Bit Manipulation instructions:


CLR
Clear
CMA
Com or complement Accumulator
CLRC

Clear carry

SETC
COMC
EI

Set Carry
Complement carry
Enable Interrupt

DI

Disable interrupt

XOR

Exclusive OR

Shift Instruction:

There are used to double or half the give data


Shift left = doubles the data (Multiply by 2)
Shift right = Half the data (Divide by 2) with error for odd digits
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There are 3 types of shift
1)
Logical
2)
Arithmetical
3)
Rotate type
Logical
SHR
SHL
LSB or MSB
Is lost if carry flag is not used

COMPUTER ORGANIZATION

Arithmetical
SHRA
ASHL
SHLA

10

Rotate type (circular)


ROR-Rotate right without carry
ROL-Rotate left without carry
RCR-Rotate right with carry
RCL-Rotate left with carry

Parity bit is not modified during the execution of ROR and ROL, but for other; parity flag may be modified.
Program control instructions
These are used to transfer the program execution from current memory location to the required memory
location.
Each time after executing one instruction, PC is automatically incremented to step size.
Branch and jump may be conditional or unconditional
All jump and branch instructions are used to transfer the program execution permanently but call instruction
transfer the program execution temporarily
Different types of jumps :
Branch
BR
Jump
JMP
Skip
SKP
Call
CALL
Return
RET
Compare
CMP
Test
TST

Skip instruction does not need an address field


Call and RET are used in subroutines
CMP and TEST instructions are used to check the status of the flag and Register content is not altered
Flags are also known as conditional code bits

Flag
Flag is a flip-flop. Flip-flop is a bi-state device that is set or reset. Flags are divided into two types:
(i) Conditional Flag
(ii) Control Flag

Conditional Flag:
These flags are set or reset based on the result nature of ALU. They are divided into six types:
(i) Carry Flag: These bit is used to represent the range exceeding conditions on the unsigned arithmetic operations.
The n-bit unsigned range is 0 to (2n 1).

Example: 1. 4-bit unsigned range is 0 to (24 1).

i.e., 0 to 15

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2.

7
3
10

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11

111
0111
0 011
1 01 0

Carry = Reset
Justification: Accumulator : 1 0 1 0
Carry : 0
8
10 0 0
3.
9

1 0 01
17
0 0 01
Carry = Set
Justification: Accumulator : 0 0 1
Carry: 1
(ii) Parity Flag: Is the ALU output contains even no. of 1s
If
True Set (Even parity)
False Reset (odd parity)
(iii) Auxiliary Flag: Is there an extra bit from the lower nibble to higher nibble.
If
True Set (1)
False Reset (0)
(iv) Zero Flag: Is the ALU output is zero
If
True Set (1)
False Reset (0)
(v) Sign Flag: Is the MSB of the ALU output is 1
If
True Set (1)
False Reset (0)
(vi) Overflow Flag: There is a carry into MSB and no carry out of MSB or vice-versa.
If
True Set (1)
False Reset (0)

Control Flag:
Based on the status of these flags the execution sequence will be changed.
These flags are never affected by the ALU output.
These flags are classified into three types
(i) Trap Flag: 1 (Trace) Step by step execution.
0 (go) At a time execution.
(ii) Interrupt Flag: 1 Enable the interrupt
0 Disable the interrupt
(iii) Direction Flag: 1 Auto Decrement
0 Auto Increment
Example: Consider the following 2s compliment no. and perform the arithmetic addition operation. What will be
the status of the overflow, carry and sign flags after the operation?
Numbers:
10101101
10110010
1 01 011 01
Sol.
1 011 0 01 0
01 011111
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Overflow 1,
Carry 1,
Sign 0
Ans. 110 (for overflow, carry and sign flags respectively)
Flag register is also known as program status word
Subroutine call return:
During the execution of call instruction, memory is needed to store the address of the next
instruction followed by the call (for Return address)
If Register is used for storing RET address, it is not possible to maintain when recursive subroutine
is executed, because old address is destroyed and the same Register is updated with the new
address.
So, for that reason stack is used during call execution instead of Register, because stack can save
many no of Return address
Instruction Cycle with Interrupt:
Shows process of handling an interrupt. Consist of three cycles.
1) Fetch cycle
2) Execution cycle
3) Interrupt cycle
Interrupt is a unusual event to disturb the normal flow of execution.
Sequence of steps require to handle interrupt is described in following diagram

Above diagram shows that


(i)
The execution sequence along with interrupt where central processing unit only respond to interrupts after
completion of current instruction execution .Based on the status of interrupt flag the processor is interrupt.
(ii)
If interrupt flag is disable no need of interrupt cycle otherwise after completion of every instruction,
processor checks for interrupts.
(iii)
Processor reads the INTR pin after completion of every instruction. If INTR pin is enabled then interrupt is
present otherwise no interrupt.
(iv)
Suppose the interrupt is present CPU transfer the control from main program to interrupt sub routine to
process the interrupt. Process the interrupt means the control is transfer to interrupt vector table.
(v)
Interrupt vector table is a part of memory which is used to store the interrupt related subroutine.
(vi)
Each subroutine entry point is identify by vector address and exit point is identified with IRET
instruction.
(vii)
Whenever the processor encounter interrupt after completion of current instruction, it push the program
counter value onto stack and then control is transferred to interrupt vector table (PC vector address).
Then processors execute the interrupt service routine.
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13

Whenever it encounters IRET instruction, it invokes the POP operation to restore PC with return address.
After this, CPU fetches the next inst from the memory. This process is k/a interrupt handling.

Example: suppose program sequence. Consist of various inst. I1, I2, I3, I4 I3 has interrupt then I1 is return address
and pushed onto the stack.

Types of Interrupt:
Various types of interrupt
1)
2)
3)
4)
5)
6)

Hardware interrupt: Present at the hardware pins


Software interrupt: It is an instruction used in the program whenever required functionally is needed.
Maskable interrupt: may be enable or disable explicitly.
Non maskable interrupt: Always in enable state cant disable by using explicit condition (Flags)
Vector interrupt: Associated with the static vector address (vector point.)
Non vector interrupt: Associated with dynamic vector add.

In above diagram the INTR pin of processor is connected with interrupt controller i.e. interrupt pin is enable by
interrupt controller.
I.C. is used to provide the communication between various input and output devices to processor.
4 input connected to I.C each device vector address is different INTR pin is enabled by any one of four devices.
Therefore the vector address is generated by source, so there are 4 possible vector address but only one at a
time. Hence INTR is called non vector interrupt.
7) External interrupt: By external devices (input devices)
8) Internal interrupt: By interrupt component of processor (temp, senso power failure, error inst. codes etc)
9) Synchronous interrupt: controlled by the fixed time interval. All the internal interrupt called synchronous
interrupt
10) Asynchronous interrupt: Initiated based on the feedback of previous inst. all external called asynchronous.
11) Level triggered interrupt: This category of interrupt are enable or disable on basis of level 0 or 1
12) Edge triggered interrupt: It enable either raising edge or falling edge transition/
Interrupt Structure:
To understand what are the interrupt employed under different category by an 8085 processor.

Question: In a stack based processor organization, postfix notation is used for evaluating arithmetic expressions.
The postfix expression ABC*/D-EF/+ for A = 6, B = 2, C = 3, D = 3, E = 4 and F = 2 evaluates to
(a) 0

(b) 1

(c) 2

(d) 3

ANS: (a)
EXP: Post fix expression is ABC*/DEF/+

Given: A = 6, B = 2, C = 3, D = 3, E = 4 and F = 2
So, ABC*/DEF/+ = 66/32+ = 13 2+ = 22+ = 0

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*operator encounter
Pop top 2 element 3 and 2
2*3 = 6

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14

Again encounter / operator


pop top two element and find the value
6
1
6

operator encounter
pop top two element and find the value
1 3 = 2

/ operator encounter
pop top two element and find the value
4
2
2

+ operator encounter
pop top two element and find the value
2 + 2 = 0
Value printed 0

Question: For address modification purpose computer uses


(a)Temp register
(b) Index register
(c) Stack pointer

(d) Program counter

ANS: (b)
EXP: An index register in a computers CPU is a processor register used for modifying operand address

during the run of a program

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KEY POINTS

1. CPU has three parts:


1. ALU
2. CU
3. Registers
2. When the memory cell size is 8-bit the corresponding address space is called as byte address.
3. Memory address interpretation mechanism is of two types:
(a) Little-Endian
(b) Bit-Endian
4. Control pins are of three types:
(a) Active low Eg: RD, WR, INTA
(b) Active high Eg: ALE, INTR, HOLD
(c) Time multiplexed Eg: AD0 AD7
5. To provide the efficient communication between the CPU, memory and I/O the system bus contains three
category of lines:
(a) Address lines (Unidirectional)
(b) Data lines (Bi-directional)
(c) Control lines (Bi-directional)
6. Instruction cycle consist of two sub-cycles:
(a) Fetch cycle
(b) Execution cycle
7. Main program is suspended during the execution of subprogram.
8. Bus configuration is of three types:
1. IO processor
2. Isolated IO
3. Memory Mapped IO.
9. The non-maskable interrupt has higher priority than the maskable interrupt.
10. Direct AM is normally used for Global variables.
11. Auto index AM is used for pushing and popping the parameters.
12. Register Indirect AM is used for holding pointers and register direct AM is for holding local variables of
procedures.

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