IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSI: REGULAR PAPERS, VOL. 61, NO.

8, AUGUST 2014

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A Verilog Piecewise-Linear Analog Behavior

Model for Mixed-Signal Validation
Sabrina Liao and Mark Horowitz, Fellow, IEEE

AbstractFull chip mixed-signal validation requires simulating

the entire design through a large number of test vectors, which
makes fast, event-based Verilog models of analog circuits essential.
We describe an extensible approach to creating these models that
maps continuous signals into piecewise linear waveforms by creating analog events which contain a value and slope. By breaking
analog circuits into sub-blocks with mostly unidirectional ports,
we avoid explicit time integration, thus fitting well into an eventdriven digital framework. The result is Verilog analog functional
models that are pin-accurate, fast to simulate, and capture the key
dynamics in analog circuits. A 250 Ms/s open-loop track and hold
circuit, 2.5 V1.8 V buck converter, and 1 GHz PLL models are
demonstrated.
Index TermsAnalog functional modeling, mixed-signal, validation.

I. INTRODUCTION

IXED-signal systems in which digital and analog circuits communicate across a tight interface are commonplace today. With aggressive scaling, the smaller form factor,
flexibility, and better noise sensitivity of digital circuits have
become appealing. Continuous time equalization techniques in
clock and data recovery circuits are supplemented with digital equalization adaptation algorithms [1], while in other cases,
analog equalization techniques are completely replaced with an
analog-to-digital converter (ADC) frontend and extensive digital signal processing [2]. Analog phase-locked loops (PLLs)
have also migrated toward mostly digital PLLs [3], [4]. At the
same time, scaling degrades analog matching. A popular solution is to use digital circuits to improve analog performance as
seen in digitally assisted data converters [5], [6]. The demand
for better power performance has also brought digital power
management on chip. Many digital control techniques such as
digital peak voltage/peak current [7], digital pulsewidth modulation [8], and constant on/off time control [9] have been developed to rival traditional analog control loops in power converters. In all these cases, the trend seems to be more complex
SoCs with increased analog and digital synergy.
This tight coupling compounded with the large complexity of
the system and the large number of test vectors that need to be
run at the system level requires efficient system-level simulation
models. The only practical means of performing this validation
is through an efficient HDL simulator [21]. Thus it is essential
Manuscript received December 24, 2013; revised February 08, 2014;
accepted February 08, 2014. Date of publication July 02, 2014; date of current
version July 24, 2014. This paper was recommended by Associate Editor J. W.
M. Rogers.
The authors are with the Department of Electrical Engineering, Stanford University, Stanford, CA 94305 USA (e-mail: liaos@stanford.edu; horowitz@stanford.edu).
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identifier 10.1109/TCSI.2014.2332265

to have analog functional models that would fit seamlessly into

the digital validation framework.
Given the importance of full system simulation, there has
been considerable work in this area. Section II briefly reviews
this work setting the stage for Section III which describes
the principles that underlie our analog functional models.
Section IV then describes how most functional models can
be created by using/combining one of four different types of
model. To make these ideas more concrete, Section V uses
these principles to create functional models of a 250 Ms/s
track and hold, 2.5 V1.8 V buck switching regulator and 1
GHz PLL, and compares the results of these models against
SPICE-level simulations of the same circuit.
II. MIXED-SIGNAL VALIDATION
The efforts enabling mixed-signal system-level validation are
divided into three streams in this brief review: modified simulators, macromodeling, and behavioral modeling. The SPICE
algorithm for solving KVL and KCL nonlinear differential algebraic equations (DAE) is fundamental to any analog simulator.
The highest accuracy is attained by iteratively bounding the
maximum error of estimates and gradually approaching the final
solution at every instance in time [10]. The traditional digital
simulator, on the other hand, functions under an event-driven
assumption working with abstracted Boolean values instead of
detailed waveforms, and hence is able to handle in practical
time the millions of test vectors needed for digital validation
[11]. When presented with a design that requires the simulation
of analog circuits for every test vector used in the validation
of digital circuits, one approach works on speeding up SPICE
[10] (e.g.., FastSPICE from BDA) or coupling the analog engine
with a digital simulator with proper timing synchronization as
well as translation between analog and digital signals [11] (e.g..,
Cadences AMS simulation environment).
Another large body of research exists in macromodeling
[13], [16], [19], which attempts to create extremely accurate
models to replace SPICE simulation entirely. The idea is to
find an alternative, possibly simpler, version of the full DAE
which will then simulate faster, but preferably retain as much
of the full SPICE model behavior as possible. Well-established
methods include moment matching for linear time-invariant
systems [20], while more recent developments include projection-based methods onto a manifold [12].
A third approach is to further relax the accuracies, but improve drastically in simulation speed, through the writing of behavioral models for analog circuits. The benefit of speed is very
appealing for mixed-signal verification suites that cover a large
number of test vectors [21]. Verilog-AMS-based method is one
example [14]. These behavioral models use differential equations and time integration, and hence require solvers similar to

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Fig. 1. Representations of continuous-time signals. a) Piecewise constant. b)

Piecewise linear.

those found in circuit simulators. Matlab/Simulink [18] is another common route. While these models are faster than the Verilog-AMS models, they are run in Matlabs event-driven simulator and still need to be connected to the digital system being
validated. To avoid the connection problem, analog behavioral
modeling has also been attempted in digital Verilog and these
models are typically constant time-step-based. Werner et al. in
[22] implemented FIR filters and adjustable circuit parameters
such as multiple biases using this method. Park et al. [17] supplements the constant time-step approach with additional data
such as the actual crossing time of a clock transition.

Fig. 2. a) Spectrum of sinusoid

with piecewise constant or linear representation. b) Spurs introduced by piecewise constant versus linear representation (both updated at ).

III. MODELING APPROACH

Our goal is to create analog functional models that would
benefit system-level validation in an event-driven, digital simulator. Therefore, these models must parallel standard digital
models in certain aspects. First, they must be pin-accurate in
order to check for equivalence with their schematics [15]. To
provide confidence in system-level validation, they should
capture salient features of real circuits behavior, but like
digital standard cells, the analog blocks still need to be verified
using SPICE before being abstracted into a functional model.
Lastly, the analog functional models must not slow down digital
simulation.
A. Representing Continuous-Time Signals
The first challenge is representing analog signals in a digital
simulator. Typical real number modeling [18], [22] samples the
continuous-time signals above Nyquist [see Fig. 1(a)]. While
this is a complete representation of the signal if it goes through
a proper reconstruction filter, or is viewed only at the sample
points, problems arise when an event occurs between sample
points. Since V[2] [again in Fig. 1(a)] has not arrived yet, we
cant interpolate the correct sampled value. This type of issue is
critical if we want to model the effect of clock jitter.
To address this issue, instead of a single value at each time
sample, we represent the signal as an initial voltage and a slope.
The signal continues on the same slope until the next event in the
sequence. Knowing the slope of the signal provides information
about the shape of the signal with little increase in model complexity. Pin-accuracy can be maintained by defining an analog
signal as a structure in SystemVerilog [Fig. 1(b)]. Each module
generates events to create a piecewise linear (PWL) model of
the waveform with small error, generally using a spacing proportional to the time constant of the circuit.
It is interesting to take a pure sinusoid signal
as an example and study the difference in the errors introduced by a
piecewise constant representation and a piecewise linear representation. Suppose that the signal samples are updated regularly
at a frequency
(although in our framework, regular updates

are not necessary). The resulting signal in frequency domain

would look similar to Fig. 2(a) with repeated delta functions
at multiples of . In the case of a piecewise constant representation, the samples are reconstructed with a zero-order-hold
and therefore the attenuation in the frequency domain follows
the shape of a sinc function. For piecewise linear representation,
the reconstruction filter is a first-order-hold and hence the attenuation is proportional to
.
Fig. 2(b) plots the difference between the signal tone (desired)
and the largest of the unwanted spurs that occur for both representations. Adding the slope value to a signal significantly reduces the errors for the same sampling rate. Note that we are
only using a regularly sampled sinusoid as the exemplar here.
The rate of update for signal samples could easily be a variable
proportional to different rates of change present in the signal as
time progresses. In addition, these small spurs will be further
suppressed at the output of downstream analog blocks if they
have smaller bandwidth compared to the signal event update
rate .
B. Avoiding Time Integration
To be computationally efficient, we want the analog cells to
generate as few events as possible, and to be quick to evaluate.
These requirements rule out building models based on nodal
differential equations. Our strategy is to partition large analog
circuits into unidirectional blocks so that closed-form equations
can be derived for their outputs given some stimulusthis could
be in some domain other than voltage/current. For example, a
VCO model works in the time/phase domain to determine when
the clock output should transition.
Fig. 3 shows an example of the partitioning needed in the
frontend of a single-slope ADC. Combining the sample-andhold, capacitor, and ramp current source creates a circuit that
can be modeled unidirectionally and analytically. We treat the
combination as nearly linear systems with two modestracking
and rampingcontrolled by the sampling clock. Since these are
nearly linear systems, they have transfer functions which lead to

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Fig. 3. Combining analog blocks to form unidirectional modules allows

models to leverage closed-form design equations for output computation.

Fig. 4. Model output evaluation (solid circle = signal update, hollow circle =
reevaluation point).

closed-form equations that describe the output. For example, the

tracking phase response to a linear input is
Fig. 5. Analog in and out model operation showing signal updates as solid circles, actual output waveform as dotted lines and piecewise linear approximation
sent out on the output as solid lines.

(1)
is the starting voltage of the input; is the slope of the input;
is the initial voltage on the capacitor. This equation is
and
universal to any single pole system. The generalization to more
complex systems can be formulated as the problem of fitting coefficients or state space matrices of nearly linear systems based
on SPICE results.
Circuits where the transfer function can be controlled through
other inputs, like AGC amplifiers, are easily handled by this
framework. Here the output equations become a function of the
controlling input. This approach is valid as long as the bandwidth of the control inputs is much less than the signal bandwidth which is nearly always true.
Weakly nonlinear behavior can be included in a similar way
by partitioning the overall behavior into several linear approximations (using methods in [19] for instance) and the module
simply chooses the correct transfer function to use according to
region of operation.
C. Model Output Evaluation
Given the general concept of PWL representation of analog
signals and the practice of partitioning analog circuits into unidirectional modules, it is straightforward to arrive at the output
waveform of a model. For every input update, we must evaluate
the output according to the time-domain response of a linear
system to a ramp (solid circle to solid circle mapping in Fig. 4).
If the output waveform is not a linear ramp, then an internal
reevaluation is scheduled to produce the next linear segment
(hollow circle to solid circle in Fig. 4).
There are also input events that do not generate output events
because they dont cause significant changes to the output. It is
important to filter these events if the system modeled uses feedback (when events are not filtered, each output event generates
a new input event, and the simulator will hang). Our solution is
to create a standard gatekeeper on each models output that only
allows a new event on the output if it differs significantly from

the old one. This is illustrated in Fig. 4 in which the last hollow
circle on the input does not generate an output event.
IV. MODELING FRAMEWORK
Commonly encountered model components can be grouped
into one of four different variants, depending on whether the
inputs and outputs are analog or digital.
A. Digital In and Out
Circuits with digital inputs and outputs are easily modeled in
standard Verilog. The only caution is that when used in analog
designs, these circuits are often analog in delay/phase (e.g.., in a
PLL), and in these cases one needs to use accurate delay models
for these gates.
B. Analog In and Out
These circuits are filters or linear systems completely described by their poles and zeros. Amplifiers, filters, and sample
and holds all fall into this category. To construct these models
we start with the transfer function of the system from every input
to each output. From this set of transfer functions and the waveform accuracy required, we set T, the delay this model will use
before recalculating the output to determine if a new output segment is needed.
The Verilog model consists of an always block followed by a
gatekeeper. The always block is the main evaluation loop thats
sensitive to input updates and the internal evaluation signal that
indicates the end of T. When triggered, it computes the current
state of the system by projecting from the previous state. The
equation used follows from the transfer function of the system.
Then it calculates the state of the system in T seconds, generating a potential new output event. Lastly it cancels any pending
internal evaluations of this block, since it just evaluated, and
then schedules a new internal evaluation point T seconds in the
future. These operations are illustrated in Fig. 5(a) and (b). The

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dotted lines in the output row are the actual trajectories from
state equations, while the solid lines are the PWL approximations provided to downstream circuits.
The gatekeeper module filters output events as previously described. Its operation is illustrated in Fig. 5(c). The continuation
of the solid line from the previous evaluation cycle is very close
to the actual response (dotted line), hence no new event occurs
on the outputi.e., no solid dot.
C. Digital

Analog

The last two classes of circuit either convert digital signals to

an analog PWL waveform, or vice versa. Both of these models
can be easily constructed by an idealized converter and a filter
module. Digital to analog blocks often occur when digital signals are used to reconstruct an analog signal like in a DAC.
This can be represented by an ideal digital to PWL converter,
driving a filter that represents the dynamics of the circuit. A
simple converter could generate a step input when the digital
input changed. A more complex model could use the risetime
information of the input waveform to set the slope of this step.
The output of this ideal converter would then drive a filter block,
which would create the correct output settling.
Circuits with analog inputs and digital outputs are quantizers,
deciding whether an analog signal is above or below a threshold.
Comparators, and voltage controlled oscillators are examples
of this type of circuit. They can be modeled by a filter, which
captures the dynamics of the sampler, followed by an ideal
slicer. In Verilog the ideal slicer is code that creates an event to
change the digital output when the output of the filter reaches
a certain threshold. This idealized output then needs to drive a
digital gate that models the delay in driving the digital value to
its destination.

Fig. 6. a) 250 Ms/s track and hold block diagram. b) Buck converter block
diagram. c) 1 GHz PLL block diagram.

V. EXAMPLE MODELS
The block diagram of a 250 Ms/s open-loop, bottom-plate
sampling, track and hold is illustrated in Fig. 6(a) along with
the clocking signal timing. The buck converter is a 2.5 V to
1.8 V constant-offtime switching regulator with a synthetic
ripple-based sensing mechanism [see Fig. 6(b)]. The 1 GHz
regulated ring-based PLL block diagram is shown in Fig. 6(c).
A. Track and Hold Model
Three analog in and out modules complete the track and
hold. The samplers use (1) at their core to compute the output
waveforms. The input-dependent on-resistance of the sampling
switch is a major contributor to distortion and is modeled by
fitting the transistor current
as a function of
and
(second-order polynomial is used in this example). During
output computation, variable R in (1) is replaced by the value
of
.
The second analog in and out module models the set of
switches p2 and p1e. An assumption is made here that these
switches are sized properly to allow the signal to fully settle.
Therefore, this module is simply an all-pass filter that copies
the input to the output with a common mode shift from 0.7 V
to 0.35 V.
The source follower buffer constitutes the last analog in and
out module. A single-pole model is used here; however, the

Fig. 7. Polynomial fit of source follower nonlinear gain.

input-dependent gain of the buffer also adds to distortion and

therefore (1) is modified to

(2)
where is the DC gain of the source follower as a function of
its input amplitude (this function is again extracted as a polynomial from SPICE results; see Fig. 7 for example). Lastly, the
total integrated noise voltage at the output of the track and hold
is simulated in SPICE to be 136.3 uVrms. Since the noisy samples are uncorrelated, this value is used directly as the standard
deviation of a Gaussian random variable that is added to the
buffers output.
B. Buck Converter Model
For unidirectionality purposes, the power MOS and inductor/capacitor network are combined to form a single digital
input, analog output module. The transfer function of this

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TABLE I
VERILOG MODEL AND SPECTRE SIMULATION SPEEDS

module is one that describes a second-order system due to

the L and C. Two versions of this function is selected by the
digital gating signals on the power MOS. The load resistance is
modeled as a variable in the system so that load response can be
measured. The sense circuit, by design, has minimal impact on
the operation of the output LC network, and therefore is treated
as a separate analog in/out module describing simple Rs and
Cs. The controller is mostly digital gates which need accurate
delay descriptions, and a clocked comparator modeled as a filter
followed by a slicer and ideal delay (i.e., an analog-to-digital
block).

Fig. 8. Track and hold output spectrum.

TABLE II
OUTPUT TONES OF TRACK AND HOLD

C. PLL Model
The phase frequency detector, VCO buffer and divider are
regular digital logic, with added features of delay as a function
of the supply, and jitter.
The regulator is a block with analog input and output. SPICE
simulations showed that the input to output transfer function
is not affected very much when the supply is varied between
10%. Therefore, we treat Vdd as just another input and model
the output as the sum of two transfer functions: one from the
input and the other from Vdd. If the two transfer functions affected each other, the model template can be easily changed to
select between versions of one transfer function according to
the parameter that affects it. Noise performance is also extracted
from SPICE and modeled.
The charge pump and the low pass filter must be grouped
together to create a unidirectional model (a digital to analog
block). The charge pump section is the converter that converts
digital up/dn signals into PWL current pulses. We include effects such as supply dependent delay, up and down path mismatch, charge injection, as well as supply and drain voltage dependent current output. The low pass filter is similar to the regulator model with its output being a sum of two transfer functions: the filter impedance and the noise transfer function of the
resistor noise source.
The VCO is an analog-to-digital block that operates nearly
linearly in the phase domain. The filter portion of the VCO
model is an integrator with phase as its state variable and
(3)
as the equation that governs the evolution of this state variable.
The slicer determines when the phase crosses and schedules
the output to be toggled at that time. We include substrate noise
by fitting the VCO frequency as a function of control voltage
and substrate voltage. We also include jitter by adding the phase
noise accrued since the last evaluation point to the incremental
phase resulting from the state equation alone.

D. Experimental Results
The models written here are pin-accurate once proper partitioning is done. Table I lists sample simulation speeds on a
Dual-Core AMD Opteron Processor 2216. Because the buck
converter control loop contains a great deal of digital logic, a
fast SPICE simulator (BDA) is used to achieve fairer comparison in speed.
The performance of the track and hold is illustrated in Fig. 8.
An input sinusoid of frequency
(where
is
250 MHz) is supplied to the track and hold, and the final output
spectrum is plotted using a 4096-point FFT. From Spectre simulation, the SFDR is 61.7 dB, while measured from the Verilog
model, it is 62.8 dB. The magnitudes of the signal tone as well
as that of the third, fifth, and seventh harmonics are listed in
Table II. The even order harmonics are suppressed due to the
differential nature of the track and hold. In addition, the Verilog
model output spectrum includes simulated noise and summing
up all the noise bins results in 135.4
of total noise voltage
(compared to 136.3
from Spectre).
Fig. 9 shows the startup behavior of the buck converter with
a load of 20 , and Fig. 10 compares the model and Spectre
responses to a load change at 1.5 s from 20 to 10 . The
startup behavior is a good match, and the load change causes
both the Verilog model and SPICE simulation to exhibit a maximum change of about 20 mV on the regulated output.
The locking behavior of the PLL is compared in Fig. 11.
A static offset of 33 ps is measured in Verilog and 34.5 ps in
Spectre.
is the output voltage of the charge pump and low
pass filter going into the regulator. The slight discrepancy near
the beginning of the locking process is due to the regulator being
offline for
less than 0.2 V, and this behavior was not included in the model. Next, we turn on the noise/jitter properties
of the PLL sub-blocks and list their contributions to output jitter
in Table III. Adding all these yields an expected total jitter of

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Fig. 12. PLL output jitter histogram (Verilog simulation).

Fig. 9. Buck converter startup behavior.

Fig. 10. Buck converter load response (20 to 10

).

Fig. 13. PLL output phase noise (Verilog simulation).

Fig. 11. PLL locking behavior.

TABLE III
SUB-BLOCK NOISE CONTRIBUTION TO PLL OUTPUT JITTER
Fig. 14. PLL output phase response to supply disturbances.

7.9 ps. Then, with all the noise sources turned on in the model,
we arrive at the jitter histogram shown in Fig. 12 using 8000
clock edges. The 8 ps of total rms jitter achieved matches well
with the expected value from Table III (jitter calculated from
Spectre phase noise simulation is 7.78 ps). We also compute
the phase noise plot (Fig. 13) using 430 k output edges and
Welchs method with an FFT size of 2048 and overlap of 1024.
As expected, we see that it peaks around the PLL bandwidth of
13 MHz. To verify supply effects, voltage steps are applied to
the PLL supply and the transient output clock edge offset from
the reference versus time is plotted in Fig. 14.
E. CPU Time Distribution
The processing time of a single-pole system is profiled according to the type of computation performed and the result is

Fig. 15. Single-pole system model CPU time distribution.

shown in Fig. 15. The scheduling of events consumes a quarter

of the total simulation time, while the rest is consumed by some
form of arithmetic calculation. The calculations are further divided into 32% spent on the computation of output waveform
and 18% on deciding whether to update the output (output filtering). The remaining 25% is spent on DPI calls which use external C functions to perform the computation of special functions such as absolute value, sine/cosine and exponentials. This
25% is distributed between the output computation and output
filtering operations.
Given the above distribution, one possible way to speed up
the simulation of these models is to avoid DPI calls. Custom
functions or look up tables have been written and the simulation
time needed for 10 k calls to each of these functions is listed in

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TABLE IV
SIMULATION TIME OF DPI VERSUS CUSTOM FUNCTION CALLS

Table IV and compared with DPI call times. The custom functions are roughly 5 faster.
VI. CONCLUSION
Creating pin-accurate, fast functional Verilog models of
analog circuits has become essential for mixed-signal validation. To generate these models, we use a piecewise linear
representation of the analog signals, which is compatible with
event-driven simulation. Next we partition the circuits into
unidirectional blocks and transform the inputs and outputs to a
domain where the circuit is nearly linear, allowing us to create
closed-form solutions in response to PWL inputs. The result
is a general approach for creating analog functional models.
We demonstrated the utility of this approach by applying these
techniques to a track and hold circuit, a buck converter and
1 GHz PLL. The resulting models have sufficient speed to
be used in system-level validation, and sufficient fidelity to
correctly model real circuit behavior. The underlying principles
are general, so we expect these same techniques will be useful
in modeling most mixed signal systems.
REFERENCES
[1] S. Parikh et al., A 32 Gb/s wireline receiver with a low-frequency
equalizer, CTLE and 2-tap DFE in 28 nm CMOS, in ISSCC Dig. Tech.
Papers, 2013, pp. 2829.
[2] O. Tyshchenko et al., A 5 Gb/s ADC-based feed-forward CDR
in 65 nm CMOS, IEEE J. Solid-State Circuits, vol. 45, no. 6, pp.
10911098, Jun. 2010.
[3] R. B. Staszewski, All-digital PLL and transmitter for mobile phones,
IEEE J. Solid-State Circuits, vol. 40, no. 12, pp. 24692482, Dec. 2005.
5.3 mW 32- to 2000 MHz digital
[4] T. K. Jang et al., A 0.062
fractional-N phase locked-loop using a phase-interpolating phase-todigital converter, in ISSCC Dig. Tech. Papers, 2013, pp. 254255.
[5] M. El-Chammas and B. Murmann, A 12-Gs/s 81-mW 5-bit time-interleaved flash ADC with background timing skew calibration, IEEE
J. Solid-State Circuits, vol. 46, no. 4, pp. 838847, Apr. 2011.
[6] E. Janssen et al., An 11 b 3.6 GS/s time-interleaved SAR ADC in 65
nm CMOS, in ISSCC Dig. Tech. Papers, 2013, pp. 464465.
[7] G. H. Zhou, J. P. Xu, J. P. Wang, and Y. Y. Jin, Comparison study on
digital peak current, digital peak voltage, digital peak voltage/peak current controlled buck converter, in Proc. IEEE. Conf. Industrial Electron. Applications, 2009, pp. 799804.
[8] C. A. Yeh and Y. S. Lai, Digital pulsewidth modulation technique for
a synchronous buck DC/DC converter to reduce switching frequency,
IEEE Trans. Ind. Electron., vol. 59, no. 1, pp. 550561, Jan. 2012.
[9] R. Redl and J. Sun, Ripple-based control of switching regulatorsAn overview, IEEE Trans. Power Electron., vol. 24, no. 12,
pp. 26692680, Dec. 2009.
[10] M. Rewienski, A perspective on fast-SPICE simulation technology,
in Simulation and Verification of Electronic and Biological Systems,
P. Li, L. M. Silveira, and P. Feldmann, Eds. Dordrecht, The Netherlands: Springer, 2011, pp. 2342.
[11] M. Zwolinski, K. G. Nichols, A. D. Brown, and M. Awan, A mixedmode circuit simulator, in Proc. U.K. IT Conf., 1990, pp. 390393.
[12] C. J. Gu, Algorithmic nonlinear macromodeling: Challenges, solutions and application sin analog/mixed-signal validation, in Proc.
CICC, 2013, pp. 18.
[13] W. Daems, G. Gielen, and W. Sansen, Simulation-based automatic
generation of signomial and posynomial performance models for
analog integrated circuit sizing, in Proce. ICCAD, 2001, pp. 7074.

2235

[14] K. S. Kundert, Predicting the phase noise and jitter of PLL-based

frequency synthesizers, in Phase-Locking in High-Performance Systems: From Devices to Architectures. Piscataway, NJ, USA: IEEE
Press, 2003.
[15] B. C. Lim, J. Kim, and M. Horowitz, An efficient test vector generation for checking analog/mixed-signal functional models, in Proc.
DAC, Jun. 2010, pp. 767772.
[16] H. Liu, A. Singhee, R. Rutenbar, and L. Carley, Remembrance of
circuits past: Macromodeling by data mining in large analog design
spaces, in Proc. DAC, 2002, pp. 437442.
[17] M.-J. Park, H. Kim, M. Lee, and J. Kim, Fast and accurate eventdriven simulation of mixed-signal systems with data supplementation,
in Proc. CICC, Sept. 2011, pp. 14.
[18] M. Van Ierssel, H. Yamaguchi, and A. Sheikholeslami, Event-driven
modeling of CDR jitter induced by power supply noise, finite decisioncircuit bandwidth and channel ISI, IEEE Trans. Circuits Syst. I: Reg.
Papers, vol. 55, no. 5, pp. 13061315, May 2008.
[19] J. Wang, X. Li, and L. Pileggi, Parameterized macromodeling for
analog system-level design exploration, in Proc. DAC, 2007, pp.
940943.
[20] L. T. Pileggi and R. A. Rohrer, Asymptotic waveform evaluation for
timing analysis, IEEE Trans. Comput.-Aided Des. Integrated Circuits
Syst., vol. 9, no. 4, pp. 352366, 1990.
[21] C.-J. R. Shi, Mixed-signal system-on-chip verification using a Recursively-Verifying-Modeling (RVM) methodology, in Proc. ISCAS,
2010, pp. 14321435.
[22] C. Werner et al., Modeling, simulation and design of a multi-mode
210 Gb/sec fully adaptive serial link system, in Proc. CICC, Sep.
2005, pp. 709716.
Sabrina Liao received the B.A.Sc. degree with distinction in engineering science from the University
of Toronto, Toronto, ON, Canada, in 2008, and the
M.S. degree in electrical engineering from Stanford
University, Stanford, CA, USA, in 2009, where she
is currently pursuing her doctoral degree.
She designed GHz signal conditioning circuits
for THz applications at Kilby Labs of Texas Instruments, Dallas, TX, USA, modeled clock and
data recovery circuits for the SERDES Technology
Group of Xilinx, San Jose, CA, USA, and designed
a calibrated DAC at the Central Engineering Division of Broadcom, San Jose,
during the summers of 2010, 2011, and 2013, respectively.
Ms. Liao received the University of Toronto Shaw Scholarship for
20042008, a Stanford Graduate Fellowship for 20082011, and Natural Sciences and Engineering Council of Canada (NSERC) Postgraduate Scholarships
for 20082010 and 20112013.

Mark Horowitz (F00) received the B.S. and M.S.

degrees in electrical engineering from the Massachusetts Institute of Technology, Cambridge, MA, USA,
in 1978, and the Ph.D. degree from Stanford University, Stanford, CA, USA, in 1984.
He is the Yahoo! Founders Professor at Stanford
University and was Chair of the Electrical Engineering Department from 2008 to 2012. His research
interests are quite broad and span using electrical
engineering and computer science analysis methods
to problems in molecular biology to creating new
design methodologies for analog and digital VLSI circuits. He has worked
on many processor designs, from early RISC chips to creating some of the
first distributed shared-memory multiprocessors, and is currently working on
creating very power efficient systems using specialized accelerators. Recently
he has worked on a number of problems in computational photography. In
1990, he took leave from Stanford to help start Rambus Inc, a company
designing high-bandwidth memory interface technology, and his work at both
Rambus and Stanford drove high-speed I/O for over a decade. His current
research includes updating both analog and digital design methods, low-energy
multiprocessor designs, computational photography, and applying engineering
to biology.
Dr. Horowitz has received many awards, including a 1985 Presidential Young
Investigator Award, the 1993 ISSCC Best Paper Award, the ISCA 2004 Most
Influential Paper of 1989, the 2006 Don Pederson IEEE Technical Field Award,
and the 2011 SIA Faculty Researcher Award. He is a Fellow of the IEEE and
the Association for Computing Machinery and is a member of the National
Academy of Engineering and the American Academy of Arts and Science.