Rr720203 Vlsi Design

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Code No: RR420203 Set No. 1

IV B.Tech II Semester Supplimentary Examinations, May 2008
VLSI DESIGN
(Electrical & Electronic Engineering)
Time: 3 hours Max Marks: 80
Answer any FIVE Questions
All Questions carry equal marks
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1. (a) Find gm and rds for an n-channel transistor with
VGS = 1.2V; Vtn = 0.8V; W/L = 10; µnCox = 92 µA/V2 and VDS = Veff +
0.5V
The out put impedance constant. λ = 95.3 × 10−3 V−1
(b) Explain the term Figure of merit of a MOS Transistor. [10+6]
2. (a) With neat sketches explain how resistors and capacitors are fabricated in p-
well process.
(b) With neat sketches explain how resistors and capacitors are fabricated in n-
well process. [8+8]
3. Design a stick diagram for the PMOS logic shown below [16]
Y = (A + B).C
4. Design a layout diagram for the CMOS logic shown below [16]
Y = (A + B + C)
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 104 Ω per square. [16]
Figure 5
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6. With neat sketch explain clearly the architecture of the PROM. [16]
7. With respect to synthesis process explain the following terms.
(a) Flattening
(b) Factoring.
(c) Mapping. [6+5+5]
8. Mention different growth technologies of the thin oxides and explain about any one
technique. [16]
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VLSI DESIGN
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1. (a) Explain with neat sketches the Drain and Transfer characteristics of n-channel
enhancement MOSFET.
(b) With neat sketches explain the transfer characteristics of a CMOS inverter.
2. (a) Compare between CMOS and bipolar technologies.

(b) With neat sketches explain nMOS fabrication process.
3. Design a stick diagram for the NMOS logic shown below

[10+6]
[8+8]
[16]
Y = (A + B + C)
4. Design a layout diagram for nMOS inverter. [16]
5. Calculate the gate capacitance value of 5µm technology minimum sized transistor
with gate to channel capacitance value is 4 × 10−4 pF/µm2 . [16]
6. (a) What are the advantages and disadvantages of the reconfiguration.
(b) Mention different advantages of Anti fuse Technology. [8+8]
7. (a) What is the goal of VHDL synthesis step in design flow?

(b) Explain how register transfer level description provides optimized synthesis
netlist. [8+8]
8. Clearly explain the wire bonding technology of the die bonding. [16]
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VLSI DESIGN
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1. (a) With neat sketches explain the formation of the inversion layer in P-channel
Enhancement MOSFET.
(b) An NMOS Transistor is operated in the triode region with the following pa-
rameters VGS = 4V ; Vtn = 1V ; VDS = 2V ; W/L = 100; µnCox = 90 µA/V 2 .
Find its drain current and drain source resistance.
2. With neat sketches explain BICMOS fabrication in an p-well process.
3. Design a stick diagram for the CMOS logic shown below

[8+8]
[16]
[16]
Y = (AB + CD)
4. Design a layout diagram for two input CMOS NOR gate. [16]
5. Calculate the gate capacitance value of 5µm technology minimum sized transistor
with gate to channel capacitance value is 4 × 10−4 pF/µm2 . [16]
6. With neat sketch explain clearly the architecture of the PROM. [16]
7. Mention about various types of simulators used in ASIC design flow and clearly
discuss about the significance of each simulator. [16]
8. Explain clearly the molecular beam epitaxy method. [16]
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VLSI DESIGN
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1. (a) With neat sketches explain the Drain characteristics of p-channel Enhance-
ment MOSFET.
(b) An p-MOS Transistor is operated in the Active region with the following
parameters VGS = −4.5V ; Vtp = −1V ; W/L = 95; µnCox = 95 µA/V 2 .
Find its drain current and drain source resistance.
3. Design a stick diagram for two input CMOS NAND and NOR gates.
[8+8]
2. With neat sketches explain how Diodes and Resistors are fabricated in Bipolar
process. [16]
[16]
4. Design a layout diagram for the PMOS logic shown below [16]
Y = (AB) + (CD)
5. Calculate ON resistance from VDD to GND for the given inverter circuit shown in
Figure 5, If n-channel sheet resistance is 104 Ω per square. [16]
Figure 5
6. Implement 2-bit comparator using PROM. [16]
7. What is need for RTL simulation? Clearly explain RTL simulation flow in the
ASIC design flow and also mention few leading simulation tools. [16]
8. Explain about the following packaging design considerations.

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(a) Electrical considerations.
(b) Mechanical design consideration. [8+8]
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www.andhracolleges.

com The Complete Information About Colleges in Andhra Pradesh

Code No: RR420203 Set No. 1

www.andhracolleges.com Engineering-MBA-MCA-Medical-Pharmacy-B.Ed-Law Colleges Information

Code No: RR420203 Set No. 1

7. With respect to synthesis process explain the following terms.

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Code No: RR420203 Set No. 2

2. (a) Compare between CMOS and bipolar technologies.

3. Design a stick diagram for the NMOS logic shown below

4. Design a layout diagram for nMOS inverter. [16]

7. (a) What is the goal of VHDL synthesis step in design flow?

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Code No: RR420203 Set No. 3

2. With neat sketches explain BICMOS fabrication in an p-well process.

3. Design a stick diagram for the CMOS logic shown below

8. Explain clearly the molecular beam epitaxy method. [16]

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Code No: RR420203 Set No. 4

8. Explain about the following packaging design considerations.

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Code No: RR420203 Set No. 4

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