B.T.

L Institute of Technology & Management

Bangalore
A. Programme: B.E ECE
Course Code

: 10EC751

Course Name

: DSP ALGORITHMS & ARCHITECTURE

Semester

: 7TH

Course Type

: Theory

Contact Hours

: 52 Hrs

I.A Marks

: 25

University Exam Marks : 100

B. Course Prerequisite
Code

10EC52

Course Name

Description

Semester

Digital signal
processing

Frequency
representation
using DFT & FFT
IIR & FIR filters

5th

C. Course Objectives
1. To impart the knowledge of basic DSP filters and number systems
to be used
2.. To study the architectural features of DSP TMS320C54XX processor
3. Programming the DSP TMS320C54XX PROCESSOR and implementation of
Decimation, interpolation filters, adaptive filters.
4. To gain concepts of digital signal processing techniques, implementation of DSP &
FFT algorithms
5.. Learn about interfacing of serial & parallel communication devices to the
processor

D. Mode of Content Delivery

M1: Lecture with chalk and talk
M2: PPT
M3: Tutorials
M4: Assignment
M1 & M4..

E . DSP ALGORITHMS AND ARCHITECTURE

Subject Code : 10EC751 IA Marks : 25
No. of Lecture Hrs/Week : 04 Exam Hours : 03
Total no. of Lecture Hrs. : 52 Exam Marks : 100
UNIT - 1
INTRODUCTION TO DIGITAL SIGNAL PROCESSING: Introduction,
A Digital Signal-Processing System, The Sampling Process, Discrete Time
Sequences, Discrete Fourier Transform (DFT) and Fast Fourier Transform
(FFT), Linear Time-Invariant Systems, Digital Filters, Decimation and
Interpolation.
6 Hrs
UNIT - 2
ARCHITECTURES FOR PROGRAMMABLE DIGITAL SIGNALPROCESSORS:
Introduction, Basic Architectural Features, DSP
Computational Building Blocks, Bus Architecture and Memory, Data
Addressing Capabilities, Address Generation Unit, Programmability and
Program Execution, Features for External Interfacing.
7 Hrs
UNIT - 3
PROGRAMMABLE DIGITAL SIGNAL PROCESSORS: Introduction,
Commercial Digital Signal-processing Devices, Data Addressing Modes of
TMS32OC54xx., Memory Space of TMS32OC54xx Processors, Program
Control.
6 Hrs
UNIT - 4
Detail Study of TMS320C54X & 54xx Instructions and Programming, OnChip peripherals, Interrupts of TMS32OC54XX Processors, Pipeline
Operation of TMS32OC54xx Processor.
7 Hrs
UNIT - 5
IMPLEMENTATION OF BASIC DSP ALGORITHMS: Introduction,
The Q-notation, FIR Filters, IIR Filters, Interpolation and Decimation Filters
(one example in each case).
7 Hrs
UNIT - 6
IMPLEMENTATION OF FFT ALGORITHMS: Introduction, An FFT
Algorithm for DFT Computation, Overflow and Scaling, Bit-Reversed Index
Generation & Implementation on the TMS32OC54xx.
6 Hrs
UNIT - 7
INTERFACING MEMORY AND PARALLEL I/O PERIPHERALS TO
DSP DEVICES: Introduction, Memory Space Organization, External Bus
Interfacing Signals. Memory Interface, Parallel I/O Interface, Programmed
I/O, Interrupts and I / O Direct Memory Access (DMA)
. 6 Hrs
UNIT - 8

INTERFACING AND APPLICATIONS OF DSP PROCESSOR:

Introduction, Synchronous Serial Interface, A CODEC Interface Circuit. DSP
Based Bio-telemetry Receiver, A Speech Processing System, An Image
Processing System.
7 Hrs
TEXT BOOK:
4. Digital Signal Processing, Avatar Singh and S. Srinivasan,
Thomson Learning, 2004.
REFERENCE BOOKS:
1. Digital Signal Processing: A practical approach, Ifeachor E. C.,
Jervis B. W Pearson-Education, PHI/ 2002
2. Digital Signal Processors, B Venkataramani and M Bhaskar
TMH, 2nd, 2010
3. Architectures for Digital Signal Processing, Peter Pirsch John
Weily, 2008

F. Course Outcomes
CO-1 A COMPREHENSIVE UNDERSTANDING OF DIGITAL SIGNAL
PROCESSING
SYSTEMS
FILTERS, FREQENCY DOMAIN
REPRESENTATION OF DISCRETE TIME SYSTEMS.
CO-2 ABILITY TO UNDERSTAND THE BASIC ARCHITECTURAL
FEATURES &
COMPUTATIONAL BUILDING BLOCKS OF
DIGITAL SIGNAL PROCESSORS.
CO-3
ABILITY TO UNDERSTAND
ADDRESSING MODES,

ARCHITECTURE

, DATA

INSTRUCTION SET OF TMS32054XX PROCESSOR.

CO-4 STUDY OF IMPLEMENTATION OF BASIC DSP ALGORITHMS &
FFT ALGORITHM ON TMS32054XX PROCESSOR.
CO-5 STUDY OF MEMORY & PARALLEL INTERFACING
PROCESSOR & ITS APPLICATION.

OF DSP

G. Program Outcomes Addressed to the above

Course Outcomes

CO1:A
COMPREH
ENSIVE
UNDERSTA
NDING OF
DIGITAL

PO1

PO2

PO3

PO4

PO5

SIGNAL
PROCESSI
NG
SYSTEMS
FILTERS,
FREQENCY
DOMAIN
REPRESEN
TATION OF
DISCRETE
TIME
SYSTEMS.

CO2: ABILITY
TO
UNDERSTA
ND
THE
BASIC
ARCHITEC
TURAL
FEATURES
&
COMPUTAT
IONAL
BUILDING
BLOCKS
OF
DIGITAL
SIGNAL
PROCESSO
RS.

CO3: ABILITY
TO
UNDERSTA
ND
ARCHITEC
TURE
,
DATA
ADDRESSI
NG
MODES,

INS
TRUCTION
SET
OF
TMS32054
XX
PROCESSO
R.

.
CO4:

STUDY

OF
IMPLEMEN
TATION OF
BASIC DSP
ALGORITH
MS & FFT
ALGORITH
M
ON
TMS32054
XX
PROCESSO
R.

CO-5

STUDY
OF
MEMORY
&
PARALLEL
INTERFACI
NG
OF
DSP
PROCESSO
R & ITS
APPLICATI
ON.

H. Gaps in the Syllabus

Assembly language programmes to interface stereo audio codec

chip ,Dip switches, LEDs

I. Topics beyond Syllabus

J. Assessment Methodologies
Sl.No

Description

Type

Student Assignment

Direct

Internal Assessment Test

Direct

University Examination

Direct

Student Feedback

Indirect

Alumni Feedback

Indirect

Employers Feedback

Indirect

K. Course Plan
Week

Chapter

Topics to be Covered

Topics Covered

Unit 1

Introduction, A Digital SignalProcessing

System,
The
Sampling Process, Discrete
Time Sequences,
Discrete Fourier Transform
(DFT) and Fast Fourier
Transform (FFT),

Introduction, A Digital SignalProcessing

System,
The
Sampling Process, Discrete
Time Sequences,
Discrete Fourier Transform
(DFT) and Fast Fourier
Transform (FFT),

Unit 1

Linear,Time-Invariant
Linear,Time-Invariant Systems,
Systems,
Digital
Filters, Digital Filters, Decimation and
Decimation and Interpolation
Interpolation

Unit 2

Introduction,Basic
Architectural Features, DSP
Computational
Building
Blocks, Bus Architecture and
Memory,
Data Addressing Capabilities,
Address Generation Unit,

3
4

Unit 2

Introduction,Basic Architectural
Features, DSP Computational
Building
Blocks,
Bus
Architecture and Memory,
Data Addressing Capabilities,
Address
Generation
Unit,

Programmability and Program Programmability and Program

Execution,
Execution,
Features
for
External
Features
for
External
Interfacing.
Interfacing

Unit 3

Introduction,
Commercial
Digital
Signal-processing
Devices,
Data Addressing Modes of
TMS32OC54xx.

Introduction,
Commercial
Digital
Signal-processing
Devices,
Data Addressing Modes of
TMS32OC54xx.

Unit 3

Memory
Space
of Memory
Space
of
TMS32OC54xx
Processors, TMS32OC54xx
Processors,
Program,Control.
Program,Control

Unit 4

Detail Study of TMS320C54X Detail Study of TMS320C54X

& 54xx Instructions and & 54xx Instructions and
Programming,
Programming,
On-Chip peripherals,
On-Chip peripherals,

Unit 4

Interrupts of TMS32OC54XX , Interrupts of TMS32OC54XX

Processors, Pipeline Operation Processors, Pipeline Operation
of TMS32OC54xx Processor
of TMS32OC54xx Processor.

Unit 5

10

Unit 5

Introduction, The Q-notation,

implementation of FIR Filters
IIR Filters, Interpolation and
Decimation Filters

11

Unit 6

Introduction,
Introduction,
Synchronous
Serial
Synchronous
Serial
Interface, A CODEC
Interface, A CODEC
Interface Circuit
Interface Circuit.

12

Unit 6

DSP Based Bio-telemetry DSP Based Bio-telemetry

Receiver,A
Speech
Receiver, A Speech
Processing
System,
Processing System, An
An Image Processing
Image
Processing
System.
System.

Introduction, The Q-notation,

FIR Filters,
IIR Filters, Interpolation and
Decimation Filters

L. Sample Questions
1. Explain decimation & interpolation process with an example & equations
2. Explain how saturation logic is used to prevent overflow & underflow in Mac operation.
3.With neat diagram explain the architecture of TMS320C54XX Processor
4.Write an ALP to implement Decimation filter for TMS320C54XX Processor
5.

Faculty Name & Signature

HOD Signature