Suraj Kamya: CAD Lab Exp-02

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Suraj Kamya
kamyasuraj@yahoo.com +91-9871989941
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EXPERIMENT 02

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CAD Lab Exp-02

2015 (2)
PCB Lab
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Publications

Objective
a.) Transient Analysis of CMOS Inverter using step input.
b.) Transient Analysis of CMOS Inverter using pulse input.
c.) DC Analysis (VTC) of CMOS Inverter.
Software used QUCS (Quite Universal Circuit Simulator)

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Theory

About Me:
Assistant Professor
IIMT Group of Colleges,
Greater Noida.
July,2014 - Current
MATLAB Consultant
DUCAT, Noida
June, 2013 - July 2014
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CMOS inverters (Complementary NOSFET Inverters) are some of the most widely used and
adaptable MOSFET inverters used in chip design. They operate with very little power loss and at
relatively high speed.
A CMOS inverter contains a PMOS and a NMOS transistor connected at the drain and gate
terminals, a supply voltage VDD at the PMOS source terminal, and a ground connected at the NMOS
source terminal, were VIN is connected to the gate terminals and VOUT is connected to the drain
terminals.(See diagram)

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The circuit below is the simplest CMOS logic gate.

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When a low voltage (0 V) is applied at the input, the top transistor (P-type) is conducting
(switch closed) while the bottom transistor behaves like an open circuit.
Therefore, the supply voltage (5 V) appears at the output.
Conversely, when a high voltage (5 V) is applied at the input, the bottom transistor (N-type)
is conducting (switch closed) while the top transistor behaves like an open circuit.

Hence, the output voltage is low (0 V).

The function of this gate can be summarized by the following table:

Input Output
High Low
Low High

The output is the opposite of the input - this gate inverts the input.
Notice that always one of the transistors will be an open circuit and no current flows from
the supply voltage to ground.

Transistor Switch Model

The switch model of the MOSFET transistor is defined as follows:

MOSFET Condition MOSFET State of
MOSFET
NMOS

Vgs<Vtn

OFF

NMOS

Vgs>Vtn

ON

PMOS

Vsg<Vtp

OFF

PMOS

Vsg>Vtp

ON

When VIN is low, the NMOS is "off", while the PMOS stays "on": instantly charging VOUT to logic

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Suraj Kamya: CAD Lab Exp-02

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high. When Vin is high, the NMOS is "on and the PMOS is "on: draining the voltage at VOUT to logic
low.

1.
2.
3.
4.
5.

Procedure
Select the components from the library & connect the circuit as shown in figure.
Set simulation parameters for DC & Transient simulation; set parameters as shown wherever required. (Enter timing
values)
Start the Simulation.
Insert the Cartesian Coordinate & Tabular entities to analyse results.
Select the output parameters to display on visual entities.

Circuit diagrams & Output waveforms

Figure a) DC analysis, VTC characteristics of CMOS inverter.

Figure b) Output Waveform DC analysis, VTC characteristics of CMOS inverter.

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Figure c) Transient analysis of CMOS Inverter using Rectangular Pulse.

Figure d) Output Waveform of Transient analysis of CMOS Inverter using Rectangular Pulse.

Figure e) Transient analysis of CMOS Inverter using Step Pulse.

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Figure f) Output Waveform of Transient analysis of CMOS Inverter using Step Pulse.
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