Professional Documents
Culture Documents
V53C16125H
HIGH PERFORMANCE
128K X 16 BIT FAST PAGE MODE
CMOS DYNAMIC RAM
MOSEL VITELIC
HIGH PERFORMANCE
40
45
50
60
40 ns
45 ns
50 ns
60 ns
20 ns
22 ns
24 ns
30 ns
23 ns
25 ns
28 ns
40 ns
75 ns
80 ns
90 ns
110 ns
Features
Description
Package Outline
K
Power
45
50
60
Std.
Temperature
Mark
Blank
V53C16125H
MOSEL VITELIC
V
16
FAMILY
Description
Pkg.
Pin Count
SOJ
40
TSOP-II
40/44L
40
39
38
37
36
35
34
33
32
10
31
11
30
12
29
13
28
14
27
15
26
16
25
17
24
18
23
19
22
20
21
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
16125H-02
PKG. SPEED
( t RAC)
DEVICE
TEMP.
PWR.
K (SOJ)
T (TSOP-II)
40
45
50
60
(40 ns)
(45 ns)
(50 ns)
(60 ns)
16125H-01
NC
NC
WE
RAS
NC
A0
A1
A2
A3
Vcc
44
43
42
41
40
39
38
37
36
10
35
13
32
14
31
15
30
16
29
17
28
18
27
19
26
20
25
21
24
22
23
Vss
I/O16
I/O15
I/O14
I/O13
Vss
I/O12
I/O11
I/O10
I/O9
NC
LCAS
UCAS
OE
A8
A7
A6
A5
A4
Vss
Pin Names
A0A8
Address Inputs
RAS
UCAS
Column Address
Strobe/Upper Byte
Control
LCAS
Column Address
Strobe/Lower Byte
Control
WE
Write Enable
OE
Output Enable
I/O1I/O16
VCC
+5V Supply
VSS
0V Supply
NC
No Connect
16125H-03
Capacitance*
TA = 25C, VCC = 5 V 10%, VSS = 0 V
Ambient Temperature
Under Bias ................................ 10C to +80C
Storage Temperature (plastic) ..... 55C to +125C
Voltage Relative to VSS .................1.0 V to +7.0 V
Data Output Current ..................................... 50 mA
Power Dissipation .......................................... 1.0 W
Parameter
Typ.
Max.
CIN1
Address Input
pF
CIN2
pF
COUT
Data Input/Output
pF
Symbol
Unit
V53C16125H
MOSEL VITELIC
Block Diagram
128K x 16
OE
WE
UCAS
LCAS
RAS
RAS CLOCK
GENERATOR
CAS CLOCK
GENERATOR
WE CLOCK
GENERATOR
OE CLOCK
GENERATOR
VCC
VSS
I/O 1
I/O2
I/O3
COLUMN DECODERS
I/O4
I/O 5
Y0Y8
SENSE AMPLIFIERS
I/O6
REFRESH
COUNTER
I/O7
512 x 16
A1
A7
A8
I/O8
I/O 9
I/O10
I/O11
X0X7
ROW
DECODERS
A0
ADDRESS BUFFERS
AND PREDECODERS
I/O
BUFFER
256
MEMORY
ARRAY
I/O12
I/O 13
I/O14
I/O15
I/O16
256 x 512 x 16
16125H-04
V53C16125H
MOSEL VITELIC
DC and Operating Characteristics (1-2)
TA = 0C to 70C, VCC = 5 V 10%, VSS = 0 V, unless otherwise specified.
Symbol
Parameter
Access
Time
V53C16125H
Min.
Typ.
Max.
Unit
Test Conditions
Notes
ILI
10
10
mA
ILO
10
10
mA
ICC1
40
180
mA
45
170
50
160
60
150
2
mA
40
180
mA
45
170
50
160
60
150
40
170
mA
Minimum Cycle
1, 2
45
160
50
150
60
140
ICC2
ICC3
ICC4
1, 2
ICC5
mA
ICC6
mA
VCC
Supply Voltage
4.5
5.5
VIL
0.8
VIH
2.4
VCC + 1
VOL
0.4
IOL = 4.2 mA
VOH
2.4
IOH = 5 mA
5.0
2.4
V53C16125H
MOSEL VITELIC
AC Characteristics
TA = 0C to 70C, VDD = 5 V 10%, VSS = 0V unless otherwise noted
AC Test conditions, input pulse levels 0 to 3V15
40
#
Symbol
Parameter
tRAS
45
50
60
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
40
75K
45
75K
50
75K
60
75K
ns
tRC
75
80
90
110
ns
tRP
25
25
30
40
ns
tCSH
40
45
50
60
ns
tCAS
12
13
14
15
ns
tRCD
17
tRCS
ns
tASR
ns
tRAH
10
ns
10
tASC
ns
11
tCAH
10
ns
12
tRSH (R)
12
13
14
15
ns
13
tCRP
ns
14
tRCH
ns
15
tRRH
ns
16
tROH
10
10
ns
17
tOAC
12
13
14
15
ns
18
tCAC
12
13
14
15
ns
6, 7
19
tRAC
40
45
50
60
ns
6, 8, 9
20
tCAA
20
22
24
30
ns
6, 7, 10
21
tLZ
ns
16
22
tHZ
ns
16
23
tAR
30
24
tRAD
12
25
tRSH (W)
12
13
14
15
ns
26
tCWL
12
13
14
15
ns
27
tWCS
ns
28
tWCH
10
ns
28
18
32
0
6
13
36
0
7
35
20
19
14
45
0
8
40
23
20
10
50
26
15
Notes
ns
4
ns
30
ns
11
12, 13
V53C16125H
MOSEL VITELIC
AC Characteristics (Contd)
40
Max.
Min.
50
Symbol
Parameter
29
tWP
10
ns
30
tWCR
30
35
40
50
ns
31
tRWL
12
13
14
15
ns
32
tDS
ns
14
33
tDH
10
ns
14
34
tWOH
10
ns
14
35
tOED
10
ns
14
36
tRWC
110
115
130
170
ns
37
tRRW
Read-Modify-Write Cycle
RAS Pulse Width
75
80
87
105
ns
38
tCWD
CAS to WE Delay
30
32
34
40
ns
12
39
tRWD
58
62
68
85
ns
12
40
tCRW
48
50
52
65
ns
41
tAWD
38
41
42
58
ns
42
tPC
23
25
28
35
ns
43
tCP
10
ns
44
tCAR
20
22
24
30
ns
45
tCAP
46
tDHR
30
35
40
50
ns
47
tCSR
10
10
10
10
ns
48
tRPC
ns
49
tCHR
10
12
15
ns
50
tPCM
60
65
70
85
ns
51
tT
52
tREF
22
50
8
Max.
Min.
60
Min.
45
24
50
8
Max.
Min.
27
50
8
Max.
34
Unit
ns
Notes
12
50
ns
15
ms
17
V53C16125H
MOSEL VITELIC
Notes
1. ICC is dependent on output loading when the device output is selected. Specified ICC (max.) is measured with the
output open.
2. ICC is dependent upon the number of address transitions. Specified ICC (max.) is measured with a maximum of two
transitions per address cycle in Fast Page Mode.
3. Specified VIL (min.) is steady state operating. During transitions, VIL (min.) may undershoot to 1.0 V for a period
not to exceed 20 ns. All AC parameters are measured with VIL (min.) VSS and VIH (max.) VCC.
4. tRCD (max.) is specified for reference only. Operation within tRCD (max.) limits insures that tRAC (max.) and tCAA
(max.) can be met. If tRCD is greater than the specified tRCD (max.), the access time is controlled by tCAA and tCAC.
5. Either tRRH or tRCH must be satisified for a Read Cycle to occur.
6. Measured with a load equivalent to two TTL inputs and 50 pF.
7. Access time is determined by the longest of tCAA, tCAC and tCAP.
8. Assumes that tRAD tRAD (max.). If tRAD is greater than tRAD (max.), tRAC will increase by the amount that tRAD
exceeds tRAD (max.).
9. Assumes that tRCD tRCD (max.). If tRCD is greater than tRCD (max.), tRAC will increase by the amount that tRCD
exceeds tRCD (max.).
10. Assumes that tRAD tRAD (max.).
11. Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference
point only. If tRAD is greater than the specified tRAD (max.) limit, the access time is controlled by tCAA and tCAC.
12. tWCS, tRWD, tAWD and tCWD are not restrictive operating parameters.
13. tWCS (min.) must be satisfied in an Early Write Cycle.
14. tDS and tDH are referenced to the latter occurrence of CAS or WE.
15. tT is measured between VIH (min.) and VIL (max.). AC-measurements assume tT = 3 ns.
16. Assumes a three-state test load (5 pF and a 380 Ohm Thevenin equivalent).
17. An initial 200 ms pause and 8 RAS-containing cycles are required when exiting an extended period of bias without
clocks. An extended period of time without clocks is defined as one that exceeds the specified Refresh Interval.
V53C16125H
MOSEL VITELIC
Truth Table
RAS
LCAS
UCAS
WE
OE
Standby
Read: Word
ROW/COL
Data Out
ROW/COL
Function
ADDRESS
I/O
Notes
High-Z
ROW/COL
ROW/COL
Data-In
ROW/COL
ROW/COL
Read-Write
HL
LH
ROW/COL
Page-Mode Read
HL
HL
COL
Data-Out
Page-Mode Write
HL
HL
COL
Data-In
Page-Mode Read-Write
HL
HL
HL
LH
COL
Data-Out, Data-In
LHL
ROW/COL
ROW
High-Z
HL
High-Z
Notes:
1. Byte Write cycles LCAS or UCAS active.
2. Byte Read cycles LCAS or UCAS active.
3. Only one of the two CAS must be active (LCAS or UCAS).
Data-Out, Data-In
Data-Out
1,2
1,2
2
V53C16125H
MOSEL VITELIC
Waveforms of Read Cycle
t RC (2)
t RAS (1)
RAS
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
UCAS, LCAS
t RCD (6)
VIL
t CRP (13)
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RSH (R)(12)
t CAS (5)
VIH
VIH
ROW ADDRESS
VIL
t CAH (11)
t ASC (10)
COLUMN ADDRESS
t RCH (14)
t CAR (44)
t RCS (7)
WE
t RRH (15)
VIH
VIL
t ROH (16)
t CAA (20)
OE
t OAC (17)
VIH
VIL
t CAC (18)
t RAC (19)
I/O
t HZ (22)
t HZ (22)
VOH
VALID DATA-OUT
VOL
t LZ (21)
16125H-05
t RP (3)
t AR (23)
V IH
V IL
t CSH (4)
t CRP (13)
UCAS, LCAS
t RCD (6)
t RSH (W)(25)
t CAS (5)
V IH
V IL
t CAR (44)
t CAH (11)
t RAH (9)
t ASR (8)
ADDRESS
t CRP (13)
V IH
V IL
t ASC (10)
ROW ADDRESS
COLUMN ADDRESS
t RAD (24)
t WCH (28)
t CWL (26)
WE
t WP (29)
t WCS (27)
V IH
V IL
t WCR (30)
t RWL (31)
OE
V IH
V IL
t DHR (46)
t DS (32)
I/O
V IH
V IL
t DH (33)
VALID DATA-IN
HIGH-Z
16125H-06
V53C16125H
MOSEL VITELIC
Waveforms of OE-Controlled Write Cycle
t RC (2)
t RAS (1)
RAS
V IL
t CSH (4)
t CRP (13)
t RCD (6)
t RSH (W)(12)
t CAS (5)
V IH
UCAS, LCAS
t CRP (13)
V IL
t RAD (24)
t RAH (9)
t ASR (8)
ADDRESS
t RP (3)
t AR (23)
VIH
V IH
t ASC (10)
ROW ADDRESS
V IL
t CAR (44)
t CAH (11)
COLUMN ADDRESS
t CWL (26)
t RWL (31)
t WP (29)
WE
V IH
V IL
t WOH (34)
OE
V IH
V IL
t OED (35)
I/O
t DH (33)
t DS (32)
V IH
VALID DATA-IN
V IL
16125H-07
t RP (3)
t AR (23)
VIH
VIL
t CSH (4)
t CRP (13)
t RCD (6)
t RSH (W)(25)
t CRW (40)
VIH
UCAS, LCAS
VIL
t
t RAH (9)
VIH
ROW
ADDRESS
VIL
COLUMN
ADDRESS
t RAD (24)
t RWD (39)
WE
OE
CAH (11)
t ASC (10)
t ASR (8)
ADDRESS
t CRP (13)
t AWD (41)
t CWD (38)
t RWL (31)
t WP (29)
VIH
VIL
t CAA (20)
t OAC (17)
VIH
VIL
t OED (35)
t CAC (18)
t RAC (19)
I/O
t CWL (26)
VIH
VOH
VIL
VOL
t DS (32)
VALID
DATA-OUT
t LZ (21)
t DH (33)
t HZ (22)
VALID
DATA-IN
16125H-08
10
V53C16125H
MOSEL VITELIC
Waveforms of Fast Page Mode Read Cycle
RAS
t PC (42)
t CP (43)
t CSH (4)
t RAH (9)
t ASC (10)
V IH
ROW
ADDRESS
t CAR (44)
t ASC (10)
t CAH (11)
t CAH (11)
COLUMN
ADDRESS
COLUMN
ADDRESS
t RCH (14)
t CAH (11)
t RCS (7)
COLUMN
ADDRESS
t RCS (7)
t RCS (7)
V IL
t CAA (20)
t CAA (20)
t CAP (45)
t OAC (17)
t RRH (15)
t OAC (17)
V IH
V IL
t HZ (22)
t RAC (19)
t CAC (18)
t LZ (21)
t CAC (18)
t CAC (18)
t LZ (21)
t HZ (22)
V OH
VALID
DATA OUT
V OL
t HZ (22)
t HZ (22)
t HZ (22)
t HZ (22)
t LZ (21)
I/O
t RCH (14)
V IH
t OAC (17)
OE
t CRP (13)
t CAS (5)
t CAS (5)
V IL
V IL
WE
t RSH (R)(12)
t CAS (5)
V IH
t ASR (8)
ADDRESS
RP (3)
V IL
t RCD (6)
t CRP (13)
UCAS, LCAS
t RASP (37)
t AR (23)
V IH
VALID
DATA OUT
VALID
DATA OUT
16125H-09
t AR (23)
RAS
t RASP (37)
V IH
V IL
t CRP (13)
t RCD (6)
UCAS, LCAS
t PC (42)
t CP (43)
t CAS (5)
V IH
t CSH (4)
t ASC (10)
t ASR (8)
V IH
ROW
ADD
V IL
t ASC (10)
t CAH (11)
t CRP (13)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t CAR (44)
t CAH (11)
COLUMN
ADDRESS
t RAD (24)
t WCS (27)
t WCH (28)
t CAH (11)
COLUMN
ADDRESS
t CWL (26)
t WCS (27)
t CWL (26)
t WCH (28)
t RWL (31)
t WCH (28)
t WP (29)
t WP (29)
t WP (29)
WE
t CAS (5)
t CAS (5)
V IL
t RAH (9)
ADDRESS
t RSH (W)(25)
V IH
V IL
OE
VIH
V IL
I/O
V IH
V IL
t DS (32)
t DH (33)
t DS (32)
t DH (33)
t DS (32)
VALID
DATA IN
VALID
DATA IN
OPEN
t DH (33)
VALID
DATA IN
OPEN
16125H-10
11
V53C16125H
MOSEL VITELIC
Waveforms of Fast Page Mode Read-Write Cycle
RAS
t RASP (37)
VIH
V
IL
t CSH (4)
t RCD (6)
t PCM (50)
IH
t RSH (W)(25)
t CRP (13)
t CAS (5)
t CP (43)
t CAS (5)
V
UCAS, LCAS
t RP (3)
t CAS (5)
t RAD (24)
IL
t RAH (9)
t ASC (10)
t ASR (8)
V
ADDRESS
IH
IL
t CAH (11)
COLUMN
ADDRESS
t CAH (11)
COLUMN
ADDRESS
t RWD (39)
t RCS (7)
t CAR (44)
t ASC (10)
t CAH (11)
ROW
ADD
t ASC (10)
t CWL (26)
t CWD (38)
COLUMN
ADDRESS
t CWD (38)
t CWD (38)
t RWL (31)
t CWL (26)
t CWL (26)
V
WE
IH
IL
t CAA (20)
t OAC (17)
t AWD (41)
t AWD (41)
t AWD (41)
t WP (29)
t WP (29)
t WP (29)
t OAC (17)
t OAC (17)
V
OE
IH
IL
t CAA (20)
t OED (35)
t CAC (18)
t RAC (19)
t CAP (43)
t CAP (43)
t CAA (20)
t OED (35)
t CAC (18)
t HZ (22)
t HZ (22)
t DH (33)
t DH (33)
t DS (32)
t DS (32)
I/O
V I/OH
OUT
V I/OL
OUT
IN
t LZ (21)
t LZ (21)
t OED (35)
t CAC (18)
t HZ (22)
t DH (33)
t DS (32)
OUT
IN
t LZ (21)
IN
16125H-11
RAS
t RAS (1)
V IH
t RP (3)
V IL
t CRP (13)
UCAS, LCAS
V IH
V IL
t ASR (8)
ADDRESS
V IH
t RAH (9)
ROW ADDR
V IL
16125H-12
NOTE:
12
V53C16125H
MOSEL VITELIC
Waveforms of CAS-before-RAS Refresh Counter Test Cycle
t RAS (1)
RAS
t RP (3)
V IH
V IL
t CSR (47)
UCAS, LCAS
t CHR (49)
t RSH (W)(25)
t CAS (5)
t CP (43)
V IH
V IL
ADDRESS
V IH
V IL
READ CYCLE
WE
t RRH (15)
t RCH (14)
t RCS (7)
V IH
V IL
t ROH (16)
t OAC (17)
OE
V IH
V IL
t HZ (22)
t HZ (22)
t LZ (21)
I/O
V IH
D OUT
V IL
t RWL (31)
t CWL (26)
WRITE CYCLE
WE
t WCH (28)
t WCS (27)
V IH
V IL
OE
V IH
V IL
t
I/O
t DH (33)
DS (32)
V IH
D IN
V IL
16125H-13
t RAS (1)
t RP (3)
VIH
VIL
t RPC (48)
t CP (43)
t CHR (49)
t CSR (47)
UCAS, LCAS
VIH
V IL
t HZ (22)
I/O
VOH
VOL
16125H-14
13
V53C16125H
MOSEL VITELIC
Waveforms of Hidden Refresh Cycle (Read)
t RC (2)
RAS
t RC (2)
tRP (3)
t RAS (1)
t AR (23)
V IH
t RP (3)
t RAS (1)
V IL
t RCD (6)
t CRP (13)
UCAS, LCAS
t CRP (13)
V IL
V IH
t RAD (24)
t ASC (10)
t CAH (11)
COLUMN
ADDRESS
ROW
ADD
V IL
t RCS (7)
WE
t CHR (49)
V IH
t ASR (8)
t RAH (9)
ADDRESS
t RSH (R)(12)
t RRH (15)
V IH
V IL
t CAA (20)
t OAC (17)
OE
V IH
V IL
t CAC (18)
t LZ (21)
t RAC (19)
t HZ (22)
t HZ (22)
V OH
I/O
VALID DATA
V OL
16125H-15
t RAS (1)
t RP (3)
V IL
t RCD (6)
t CRP (13)
UCAS, LCAS
t RC (2)
t RP (3)
t RAS (1)
t AR (23)
t RSH (12)
t CHR (49)
t CRP (13)
V IH
V IL
t RAD (24)
t ASC (10)
t ASR (8)
t RAH (9)
ADDRESS
V IH
V IL
t CAH (11)
ROW
ADD
COLUMN
ADDRESS
t WCH (28)
t WCS (27)
WE
V IH
V IL
V IH
OE
V IL
t DS (32)
V IH
I/O
V IL
t DH (33)
VALID DATA-IN
t DHR (46)
16125H-16
14
V53C16125H
MOSEL VITELIC
Functional Description
Write Cycle
Memory Cycle
A memory cycle is initiated by bringing RAS low.
Any memory cycle, once initiated, must not be
ended or aborted before the minimum tRAS time
has expired. This ensures proper device operation
and data integrity. A new cycle must not be initiated
until the minimum precharge time tRP /t CP has
elapsed.
Refresh Cycle
To retain data, 256 Refresh Cycles are required
in each 8 ms period. There are two ways to refresh
the memory:
1. By clocking each of the 512 row addresses (A0
through A8) with RAS at least once every 8 ms.
Any Read, Write, Read-Modify-Write or RASonly cycle refreshes the addressed row.
2. Using a CAS-before-RAS Refresh Cycle. If CAS
makes a transition from low to high to low after
the previous cycle and before RAS falls, CASb e f o r e -R A S r e f r e s h i s a c t i v a t e d . T h e
V53C16125H uses the output of an internal 9bit counter as the source of row addresses and
ignore external address inputs.
Read Cycle
A Read cycle is performed by holding the Write
Enable (WE) signal High during a RAS/CAS
operation. The column address must be held for a
minimum specified by tAR. Data Out becomes valid
only when tOAC , t RAC , t CAA and t CAC are all
satisifed. As a result, the access time is dependent
on the timing relationships between these
parameters. For example, the access time is limited
by tCAA when tRAC, tCAC and tOAC are all satisfied.
15
V53C16125H
MOSEL VITELIC
Fast Page Mode Operation
Power-On
After application of the VCC supply, an initial
pause of 200 ms is required followed by a minimum
of 8 initialization cycles (any combination of cycles
containing a RAS clock). Eight initialization cycles
are required after extended periods of bias without
clocks (greater than the Refresh Interval).
During Power-On, the VCC current requirement
of the V53C16125H is dependent on the input
levels of RAS and CAS. If RAS is low during
Power-On, the device will go into an active cycle
and ID D will exhibit current transients. It is
recommended that RAS and CAS track with VCC or
be held at a valid VIH during Power-On to avoid
current surges.
512
Data Rate = ---------------------------------------t RC + 511 t PC
16
Cycle Type
I/O State
Read Cycles
High-Z
OE Controlled.
High OE = High-Z I/Os
Read-Modify-Write Cycles
High-Z
RAS-only Refresh
High-Z
Data remains as in
previous cycle
CAS-only Cycles
High-Z
V53C16125H
MOSEL VITELIC
Package Outlines
40-Pin Plastic SOJ
20
0.026 MIN
[0.660 MIN]
+0.004
0.025 0.002
+0.102
0.635 0.051
0.368 0.010
[9.35 0.254]
0.010
0.144 MAX
[3.66 MAX]
21
0.400 0.005
[10.16 0.127]
40
0.440 0.005
[11.18 0.127]
+ 0.004
0.002
+0.102
0.254 0.051
0.04 [0.1]
0.050 0.006
[1.27 0.152]
0.018
+0.004
0.002
+0.102
0.457 0.051
40/44L-Pin TSOP-II
40
21
20
05
0.0315 BSC
[.8001 BSC]
0.012 0.016
[0.305 0.406]
0.039 0.047
[0.991 1.193]
0.002 0.008
[0.051 0.203]
BASE PLANE
SEATING PLANE
0.721 0.729
[18.31 18.52]
17
0.017 0.023
[0.432 0.584]
0.396 0.404
[10.06 10.26]
0.462 0.470
[11.73 11.94]
0.0047 0.0083
[0.119 .211]
MOSEL VITELIC
WORLDWIDE OFFICES
V53C16125H
U.S.A.
TAIWAN
JAPAN
HONG KONG
19 DAI FU STREET
TAIPO INDUSTRIAL ESTATE
TAIPO, NT, HONG KONG
PHONE: 011-852-665-4883
FAX: 011-852-664-7535
1 CREATION ROAD I
SCIENCE BASED IND. PARK
HSIN CHU, TAIWAN, R.O.C.
PHONE: 011-886-35-783344
FAX: 011-886-35-792838
NORTHWESTERN
SOUTHWESTERN
SUITE 200
5150 E. PACIFIC COAST HWY.
LONG BEACH, CA 90804
PHONE: 562-498-3314
FAX: 562-597-2174
NORTHEASTERN
SUITE 436
20 TRAFALGAR SQUARE
NASHUA, NH 03063
PHONE: 603-889-4393
FAX: 603-889-9347
MOSEL VITELIC
9/98
Printed in U.S.A.
3910 N. First Street, San Jose, CA 95134-1501 Ph: (408) 433-6000 Fax: (408) 433-0952 Tlx: 371-9461