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1.
2.
The output voltage of a particular Op-amp increases 8 V in 12 s in response to a step voltage on the input. The slew rate is
(a) 0.667 V/s
(b) 0.75 V/s
(c) 1.5 V/s
(d) 96 V/s
3.
4.
5.
6.
7.
(d) variable
(d) RC-coupled
(c) zero R0
(b) infinite Ri
8.
9.
10. When an input voltage of 1 V is applied to an Op-amp having Av = 106 and bias supply of + 15 V, the output voltage available is
(a) 15106 V
(b) 106V
(c) 15V
(d) 15V
11. An inverting amplifier has Rf=2 M and R1 = 2 k, Its scale factor is
(a) 1000
(b) -1000
(c) 10-3
(d) -10-3
12. In an inverting amplifier, the two input terminals of an ideal Op-amp are the same potential because
(a) the two input terminals are directly shorted internally
(b) the input impedance of the Op-amp is in finity
(c) common-mode rejection ratio is infinity
(d) the open-loop gain of the Op-amp is infinity
13. The open-loop gain of an operational amplifier is 10 5. An input signal of 1 mV is applied to the inverting input with the noninverting input with the non-inverting input connected to the ground. The supply voltages are 10V. The output of the amplifier
will be
(a) +100 V
(b) -100 V
(c) +10 V (approximately)
(d) -10 V (approximately)
14. An ideal Op-amp has
(a) infinite input and output impedance
(c) low input and infinite output impedance
15. For an ideal difference amplifier, the common mode Rejection Radio (CMRR) should be:
(a) As high as possible
(b) As low as possible
(c) Constant
(d) unity
16. The input stage of an Op-Amp is usually a
(a) differential amplifier
(c) CE amplifier
(c) 102Hz
(d) 10 Hz
(c) very
(d) very
19. In a 741 Op-amp, There is 20 dB/decade fall-off starting at a relatively low frequency. This is due to:
(a) applied load
(b) internal compensation
(c) impedance of the source
(d) power dissipation in the chip.
20. The input differential stage of Op-amp 741 is biased at about 10 A current. Such a low current of the input stage gives
(a) high CMRR
(b) high differential gain
(c) low CMRR
(d) high input impedance.
21. A differential amplifier is invariably used in the input stage of all Op-amp. This is done basically to provide the Op-amp with a
very high
(a) CMRR
(b) bandwidth
(c) slew-rate
(d) open-loop gain
22. The slew rate of an Op-amp is 0.5 Vs The maximum frequency of a sinusoidal input of 2 Vrms that can be handled without
excessive distortion is
(a) 3kHz
(b) 30kHz
(c) 200kHz
(d) 2MHz
23. In a circuit if the open loop gain is 106 and output voltage is 10 V, the differential voltage should be
(a) 10V
(b) 0.1 V
(c) 100V
(d) 1V.
24. An Op-amp has a common-mode gain of 0.01 and a differential mode gain of 10 5. Its common mode rejection ratio would be:
(a)10-7
(b) 10 -3
(c)103
(d) 107
25. When in a negative scalar, both R1 and Rf are reduced to zero, the circuit functions as
(a) integrator
(b) subtractor
(c) comparator
(d) unity follower
26. The two terminals of an Op-amp are known as
(a) positive and negative
(b) differential and non-differential
(c) inverting and non- inverting
(d) high and low
27. The purpose of a comparator is to
(a) amplify an input voltage
(b) detect the occurrence of a changing input voltage
(c) maintain a constant output when the d.c. input voltage changes
(d) produce a change in output when an input voltage equals the reference voltage
28. The Op-amp comparator circuit uses
(a) positive feedback
(b) negative feedback
(c) regenerative feedback
(d) no feedback
29. The feedback path in an Op-amp differentiator consists of
(a) a resistor
(b) a capacitor
(c) a resistor and a capacitor in series
(d) a resistor and a capacitor in parallel
30. The feedback path in an Op-amp integrator consists of
(a) a resistor
(b) a capacitor
(c) a resistor and a capacitor in series
(d) a resistor and a capacitor in parallel
31. For the high-pass circuit to act as a differentiator, the time constant must be
(a) small
(b) very small in comparison to the time period of the input signal
(c) very high in comparison to the time period of the input signal
(d) of moderate value
32. The effect of a finite gain of an operational amplifier used in an integrator is that
(a) it would not integrate
(b) the slope of output will vary with time
(c) the final values of the output will vary with time
(d) there will be instability in the circuit
33. In an PLL, lock occurs when the
(a) input frequency and the VCO frequency are the same
(b) phase error is 180
(c) VCO frequency is double the input frequency
(d) phase error is 90
34. The essential blocks of a phase-locked loop (PLL)are phase detector, amplifier,
(a) high-pass filter and crystal controlled oscillator
(b) low-pass filter and crystal controlled oscillator
(c) high-pass filter and voltage controlled oscillator
(d) low-pass filter and voltage controlled oscillator
35. A second-order band-pass active filter can be obtained by cascading a low-pass second-order section having cut-off frequency, f OH
with a high-pass second-order having cut-off frequency, fOL, provided
(a) fOH > fOL
(d) fOH
1
fOL
2
(c) impedance
(d) opposite to
42. The output voltage of a step-down type switching voltage regulator depends on
(a) input voltage
(b) duty cycle
(c) transistor on time
43. As compared to voltage regulators made up of discrete components, IC regulators have the inherent advantages of
(a) self protection against over-temperature
(b) remote control
(c) current limiting
(d) all of the above
44. A three terminal monolithic IC regulator can be used as
(a) an adjustable output voltage regulator alone
(c) a current regulator and a power switch
45. In a switched-mode power supply (SMPS), after conversion of a.c. supply to a highly filtered d.c. voltage, a switching transistor is
switched ON and OFF at a very high speed by a pulse width modulator (PWM) which generates very high frequency square
pulses. The frequency of the pulses is typically in the range of
(a) 100 Hz 200 Hz
(b) 500 Hz 1Hz
(c) 2 kHz 5kHz
(d) 20 kHz 50 kHz
46. In a zero-level detector, the output changes state when the input
(a) is positive
(b) is negative
(c) crosses zero
(d) has a zero rate of change
47. Noise on the input of a comparator can cause the output to
(a) hang up in one state
(b) go to zero (c) change back and forth erratically
between two states
(d) produce the amplified noise signal
48. The effects of noise can be reduced by
(a) lowering the supply voltage
(b) using positive feedback (c) using negative
feedback
(d) using hysteresis (e) answers (b) & (c)
49. If the voltage gain for each input of a summing amplifier with a 4.7 K feedback resistance is unity, the
input resistance must have a value of
(a) 4.7K
(b) 4.7K divided by the no. of inputs
(c) 4.7K times the no. of
inputs.
50. An average amplifier has five inputs. The ratio Rf/Ri must be
(a) 5
(b) 0.2
(c) 1
51. In an integrator, the feedback element is a
(a) resistor
(b) capacitor (c) zener diode
(d) voltage divider
52. For a step input, the output of an integrator is a
(a) pulse
(b) triangular waveform
(c) spike
(d) ramp
53. The rate of change of integrators output voltage in response to a step input is set by the
(a) RC time constant (b) amplitude of step input (c) current through the capacitor
(d) all of these
54. In a differentiator, the feedback element is a
(a) resistor
(b) capacitor (c) zener diode
(d) voltage divider
68. With reference to astable mode of operation of timer 555, one of the following statements is true
(a) Trigger terminal is always shorted to threshold terminal
(b) Reset terminal is always grounded
(c) Reset terminal is always at +VCC
(d) Trigger terminal is left open
69. One of the following is an adjustable positive voltage IC regulator
(a) A 79G
(b) A78G
(c) LM 323
(d) LM 340
70. A phase locked loop consists of the following principal components
(a) The phase comparator, the VCO and the Error Amplifier
(b) The phase comparator, VCO and LPF
(c) The Phase comparator, the LPF and the Error Amplifier
(d) none of these
71. A higher bandwidth low pass filter in a PLL signifies
(a) Greater capture range and lesser lock up time
(b) Greater capture range and Greater lock up time
(c) Lesser capture range and lesser lock up time
(d) Smaller capture range and lesser lock up range.
72. When a PLL is being used as a frequency synthesizer, the output is taken from
(a) the LPF output
(b) The VCO output
(c) The output of phase comparator
(d) None of these
73. When a PLL is used as a phase modulator, the modulating signal is injected
(a) at the input of LPF
(b) at the input of VCO
(c) at the input of phase comparator
(d) from the output of LPF.
74. The tracking range of a PLL
(a) is same as its lock range
(b) is same as capture range
(c) using an high gain error amplifier
(d) reducing the gain of error amplifier.
75. A phase locked loop works on the principle of feedback that is ______ in nature.
(a) Regenerative
(b) Degenerative
(c) Either a or b
(d) Does not work on the principle of feedback.
76. The phase comparator conversion gain is measured in
(a) Volts per radian
(b) Radians per volt
(c) Radians
(d) It is a dimension less quantity
77. The capture range does not depend on one of the following factors
(a) Band edge of LPF
(b) VCO characteristics
(c) Closed loop gain of PLL
(d) None of these
78. One of the following is a monolithic IC used in TV vision IF system
(a) CA 3065
(b) CA 920
123.
124.
125.
126.
127.
128.
129.
When a low-pass and a high-pass filter are cascaded to get a band-pass filter, the critical frequency of the
low-pass filter must be
(a) equal to the critical frequency of the high-pass filter
(b) less than the critical frequency of the high-pass filter
(c) greater than the critical frequency of the high-pass filter
130.
131.
(a)
(b)
(c)
(d)
(a)
(b)
(c)
(d)
132.
133.
134.
(d) Colpitts
135.
136.
137.
(a)
(b)
(c)
(d)
138.
139.
140.
An OTA is basically a
(a) voltage-to-current amplifier
(c) current-to-current amplifier
141.
142.
143.
(a) elnx
106.
107.
108.
109.
110.
111.
112.
113.
Common-mode gain is
(a) very high
(b) very low
(c) 80 dB
(d) unpredictable
(d) answers (b) and (c)
114.
Of the values listed, the most realistic value for open-loop gain of an op-amp is
(a) 1
(b) 2000
(c) 80 dB
(d) 100,000
115.
A certain op-amp has bias currents of 50A and 49.3A. The input offset current is
(a) 700 nA
(b) 99.3A
(c) 49.7A
(d) none of these
116.
117.
118.
A certain non-inverting amplifier has a Ri of 1.0 k and an Rf 100 k. The closed-loop gain is
(a) 100,000
(b) 1000
(c) 101
(d) 100
119.
A certain inverting amplifier has a closed-loop gain of 25. The op-amp has an open-loop gain of 100,000. If
another op-amp with an open-loop gain of 200,000 is substituted in the configuration, the closed-loop gain
(a) doubles
(b) drops to 12.5
(c) remains at 25
(d) increases slightly
120.
121.
A voltage-follower
(a) has a gain of 1
(b) is non-inverting
124. If a certain op-amp has a midrange open-loop gain of 200,000 and a unity-gain frequency of 5 MHz, the gainbandwidth product is
(a) 200,000 Hz
(c) 1 X 1012 Hz
(b) 5,000,000 Hz
(d) not determinable from the information
144.
In a zero-level detector, the output changes state when the input
(a) is positive
(b) is negative
(c) crosses zero
(d) has a zero rate of change
145.
Noise on the input of a comparator can cause the output to
(a) hang up in one state
(b) go to zero
(c) change back and forth erratically between two states
(d) produce the amplified noise signal
146.
The effects of noise can be reduced by
(a) lowering the supply voltage
(c) using negative feedback
(d) using hysteresis
147.
A comparator with hysteresis
(a) has one trigger point
(b) has two trigger points
a variable trigger point
(d) is like a magnetic circuit
(c) has
148.
(a) 5
149.
(a) resistor
150.
(a) a pulse
(d) a ramp
151.
The rate of change of an integrator's output voltage in response to a step input is set by
(a) the RC time constant
(b) the amplitude of the step input
(c) the current through the capacitor
(d) all of these
152.
(a) resistor
153.
The output of a differentiator is proportional to
(a) the RC time constant
(b) the rate at which the input is changing
(c) the amplitude of the input
(d) answers (a) and (b)
154.
When you apply a triangular waveform to the input of a differentiator, the output is
(a) a dc level
(b) an inverted triangular waveform
(c) a square waveform
(d) the first harmonic of the triangular waveform
155.
Typically. an instrumentation amplifier has an external resistor used for
(a) establishing the input impedance
(b) setting the voltage gain
(c) setting the current gain
(d) interfacing with an instrument
156.
In an OTA, the transconductance is controlled by
(a) the dc supply voltage
(b) the input signal voltage
(c) the manufacturing process
(d) a bias current
108.
109.
A certain op-amp has an open loop gain of 80,000. The maximum output levels of this particular
device are 12V when the dc supply voltages are 15V. If a differential voltage of 0.15 Vrms is applied
between the inputs, what is the peak-to-peak value of the output?
110.
Determine the output level (max. positive or max. negative) for each comparator
shown below.
U 2
U 1
1V
Vo
2V
uA741
uA741
111.
5V dc
Determine the output level (max. positive or max. negative) for each comparator shown below.
U 2
U 1
1V
+
uA741
Vo
2V
U 3
7V
Vo
+
uA741
7V
Vo
uA741
5V dc
Vo
112.
Determine the output level (max. positive or max. negative) for each comparator shown
below.
U 2
Vo
2V
U 3
7V
Vo
uA741
uA741
113.
Vo
5V dc
Calculate VUT for the Schmitt trigger circuit shown below, if VO(max) = 10V.
R
Vi
U 4
Vo
R 1
47k
uA741
R 2
18k
114.
Calculate VLT for the Schmitt trigger circuit shown below, if VO(max) = 10V.
R
Vi
U 4
Vo
R 1
47k
uA741
R 2
18k
115.
Calculate VH for the Schmitt trigger circuit shown below, if VO(max) = 10V.
R
Vi
U 4
Vo
R 1
47k
uA741
R 2
18k
116.
adder.
Find the output voltage when the input voltages shown in figure below are applied to the scaling
+2V
10k
10k
U 6
+3V
33k
+3V
Vo
+
91k
uA741
+6V
180k
117.
A certain OTA with a transconductance of 5000S has a load resistance of 10K. If the input
voltage is 100mV, what is the output current?
118.
A certain OTA with a transconductance of 5000S has a load resistance of 10K. If the input
voltage is 100mV, what is the output current? What is the output voltage?
119.
Determine the output voltage for the log amplifier shown below. Assume IS = 60nA.
1.5V
47k
0.225V
10k
U 8
U 7
Vo
uA741
120.
5V
uA741
Determine the output voltage for the anti-log amplifier shown below. Assume IS = 60nA.
47k
0.225V
10k
U 8
U 7
Vo
+
uA741
+
uA741
Vo