IMPLEMENTATION OF RADIX-2 PIPELINED

FFT/IFFT PROCESSOR FOR OFDM

APPLICATIONS
SYNOPSIS
Fast Fourier Transform (FFT) processors are today one of the most
important blocks in wireless communication systems. The most
common use of the Fast Fourier Transform (FFT) is to transform time
domain signal into a frequency domain. Fast Fourier Transform was
developed to efficiently speed up its computation time and reduce
hardware cost. FFT analyzes an input signal sequence by using a
Decimation-in-Frequency

(DIF)

or

Decimation-in-Time

(DIT)

decomposition to construct an computational signal-flow graph (SFG).

Here I have used a decimation-in-frequency decomposition as it
manipulates the single-path delay pipeline facility as it is my proposed
architecture.
Frequency

In

Division

the

implementation

Multiplexing

of

(OFDM)

wideband
systems,

Orthogonal
Fast

Fourier

Transform (FFT) processors are one of the key-component. In this

project, I present a pipelined implementation of a radix-2 Fast Fourier
Transform (FFT) processor which results in low hardware cost and low
power consumption. My design adopts a single-path delay feedback
(SDF) as hardware architecture. In further improvement of Fast Fourier
Transform (FFT) processor Read-Only-Memories (ROMs) used to store
twiddle factors are greatly replaced by the reconfigurable complex
multiplier and bit-parallel multipliers to achieve a ROM-less FFT
processor. The proposed architecture is functionally verified in Xilinx
ISE simulator and also synthesis of the intermediate blocks is done by
the RTL compiler of cadence. The obtained results are compared with
various methods to verify it achieves low power consumption when
compared to other ones.