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AD630
Data Sheet
FEATURES
RINA
CM OFF
ADJ
DIFF OFF
ADJ
DIFF OFF
ADJ
BIAS
2.5k
AMP A
CH A+
COMP
CH A
RINB
+VS
2.5k
AMP B
10k
V
10k
5k
+VS
VOUT
CH B+
CH B
APPLICATIONS
RB
RF
RA
CHANNEL
STATUS
B/A
COMP
SEL B
VS
00784-001
SEL A
Figure 1.
GENERAL DESCRIPTION
The AD630 is a high precision balanced modulator/demodulator
that combines a flexible commutating architecture with the
accuracy and temperature stability afforded by laser wafer trimmed
thin film resistors. A network of on-board applications resistors
provides precision closed-loop gains of 1 and 2 with 0.05%
accuracy (AD630B). These resistors may also be used to accurately
configure multiplexer gains of 1, 2, 3, or 4. External feedback
enables high gain or complex switched feedback topologies.
The AD630 can be thought of as a precision op amp with two
independent differential input stages and a precision comparator that is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion.
The AD630 is used in precision signal processing and instrumentation applications that require wide dynamic range. When
used as a synchronous demodulator in a lock-in amplifier
configuration, the AD630 can recover a small signal from
100 dB of interfering noise (see the Lock-In Amplifier
Applications section). Although optimized for operation up to
1 kHz, the circuit is useful at frequencies up to several hundred
kilohertz.
Rev. F
CM OFF
ADJ
Other features of the AD630 include pin programmable frequency compensation; optional input bias current compensation
resistors, common-mode and differential-offset voltage adjustment, and a channel status output that indicates which of the
two differential inputs is active.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Document Feedback
AD630
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Specifications..................................................................................... 3
AC Bridge .................................................................................... 17
REVISION HISTORY
7/15Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Features Section, General Description Section,
Product Highlights Section, and Figure 1 ..................................... 1
Added Applications Section ............................................................ 1
Changes to Table 3 ............................................................................ 4
Added Table 4; Renumbered Sequentially .................................... 5
Added Figure 4; Renumbered Sequentially and Table 5 ............. 6
Added Figure 5 and Table 6............................................................. 7
Added Table 7.................................................................................... 8
Changes to Figure 7, Figure 8, and Figure 9.................................. 9
Changes to Figure 13, Figure 14, and Figure 15 ......................... 10
Added Test Circuits Section and Figure 16 to Figure 19 ........... 11
Added Theory of Operation Section............................................ 12
Change to Figure 24 ....................................................................... 13
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/04Rev. D to Rev. E
Changes to Ordering Guide .............................................................3
Replaced Figure 12 ............................................................................9
Changes to AC Bridge Section.........................................................9
Replaced Figure 13 ......................................................................... 10
Changes to Lock-In Amplifier Applications ............................... 10
Updated Outline Dimensions ....................................................... 11
6/01Rev. C to Rev. D
Changes to Specification Table ........................................................2
Changes to Thermal Characteristics ...............................................3
Changes to Ordering Guide .............................................................3
Changes to Pin Configurations .......................................................3
Changes to Outline Dimensions .................................................. 11
Rev. F | Page 2 of 20
Data Sheet
AD630
SPECIFICATIONS
At 25C and VS = 15 V, unless otherwise noted.
Table 1.
Parameter
GAIN
Open-Loop Gain
1, 2 Closed-Loop Gain Error
Closed-Loop Gain Match
Closed-Loop Gain Drift
CHANNEL INPUTS
VIN Operational Limit1
Input Offset Voltage
TMIN to TMAX
Input Bias Current
Input Offset Current
Channel Separation at 10 kHz
COMPARATOR
VIN Operational Limit1
Switching Window
TMIN to TMAX
Input Bias Current
Response Time (5 mV to +5 mV Step)
Channel Status
ISINK at VOL = VS + 0.4 V2
Pull-Up Voltage
DYNAMIC PERFORMANCE
Unity Gain Bandwidth
Slew Rate3
Settling Time to 0.1% (20 V Step)
OPERATING CHARACTERISTICS
Common-Mode Rejection
Power Supply Rejection
Supply Voltage Range
Supply Current
OUTPUT VOLTAGE, AT RL = 2 k
TMIN to TMAX
Output Short-Circuit Current
TEMPERATURE RANGES
N Package
D Package
Min
90
AD630J/AD630A
Typ Max
110
0.1
0.1
2
Min
AD630K/AD630B
Typ Max
100
120
Min
90
0.05
0.05
2
AD630S
Typ Max
Unit
110
0.1
0.1
2
dB
%
%
ppm/C
(VS + 4) to (+VS 1)
500
800
100 300
10
50
100
(VS + 4) to (+VS 1)
100
160
100 300
10
50
100
(VS + 4) to (+VS 1)
500
1000
100 300
10
50
100
V
V
V
nA
nA
dB
V
mV
mV
nA
ns
1.6
1.6
1.6
(VS + 33)
(VS + 33)
2
45
3
85
90
5
2
45
3
105
110
4
16.5
5
10
90
90
5
110
110
4
16.5
5
10
25
0
25
(VS + 33)
90
90
5
70
+85
0
25
2
45
3
MHz
V/s
s
110
110
dB
dB
V
mA
16.5
5
10
25
V
mA
25
70
+85
55
+125
If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
ISINK at VOL = (VS + 1 V) is typically 4 mA.
3
Pin 12 open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/s.
1
2
Rev. F | Page 3 of 20
mA
V
C
C
AD630
Data Sheet
Table 2.
Rating
18 V
600 mW
Indefinite
18 17
65C to +150C
55C to +125C
300C
150C
0.99
(2.515)
15
19
14
20
13
1
2
0.089
(2.260)
12
11
10
9
3
4
THERMAL RESISTANCE
16
JC
24
35
35
38
JA
61
120
120
75
Unit
C/W
C/W
C/W
C/W
ESD CAUTION
Rev. F | Page 4 of 20
00784-002
Parameter
Supply Voltage
Internal Power Dissipation
Output Short-Circuit to Ground
Storage Temperature
Ceramic Package
Plastic Package
Lead Temperature Range (Soldering, 10 sec)
Maximum Junction Temperature
Data Sheet
AD630
20 CH A
CH A+ 2
19 CH B
18 CH B+
AD630
17 RINB
CM OFF ADJ 6
TOP VIEW
16 RA
(Not to Scale)
15 RF
14 RB
CM OFF ADJ 5
VS 8
13 VOUT
SEL B 9
12 COMP
SEL A 10
11 +VS
00784-030
Mnemonic
RINA
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/A
VS
SEL B
SEL A
+VS
COMP
VOUT
RB
RF
RA
RINB
CH B+
CH B
CH A
Description
2.5 k Resistor to Noninverting Input of Op Amp A
Noninverting Input of Op Amp A
Differential Offset Adjustment
Differential Offset Adjustment
Common-Mode Offset Adjustment
Common-Mode Offset Adjustment
B or A Channel Status
Negative Supply
B Channel Comparator Input
A Channel Comparator Input
Positive Supply
Pin to Connect Internal Compensation Capacitor
Output Voltage
10 k Gain Setting Resistor
10 k Feedback Resistor
5 k Feedback Resistor
2.5 k Resistor to Noninverting Input of Op Amp B
Noninverting Input of Op Amp B
Inverting Input of Op Amp B
Inverting Input of Op Amp A
Rev. F | Page 5 of 20
AD630
Data Sheet
RINA 1
20 CH A
CH A+ 2
19
CH B
18
CH B+
RINB
CM OFF ADJ 5
CM OFF ADJ 6
AD630
17
TOP VIEW
16 RA
(Not to Scale)
15 RF
14
RB
13
VOUT
SEL B 9
12
SEL A 10
11
COMP
+VS
00784-031
Mnemonic
RINA
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/A
VS
SEL B
SEL A
+VS
COMP
VOUT
RB
RF
RA
RINB
CH B+
CH B
CH A
Description
2.5 k Resistor to Noninverting Input of Op Amp A
Noninverting Input of Op Amp A
Differential Offset Adjustment
Differential Offset Adjustment
Common-Mode Offset Adjustment
Common-Mode Offset Adjustment
B or A Channel Status
Negative Supply
B Channel Comparator Input
A Channel Comparator Input
Positive Supply
Pin to Connect Internal Compensation Capacitor
Output Voltage
10 k Gain Setting Resistor
10 k Feedback Resistor
5 k Feedback Resistor
2.5 k Resistor to Noninverting Input of Op Amp B
Noninverting Input of Op Amp B
Inverting Input of Op Amp B
Inverting Input of Op Amp A
Rev. F | Page 6 of 20
Data Sheet
AD630
RINA 1
20 CH A
CH A+ 2
19 CH B
18 CH B+
17 RINB
AD630
16 RA
TOP VIEW
CM OFF ADJ 6 (Not to Scale) 15 RF
14 RB
CHANNEL STATUS B/A 7
13 VOUT
12 COMP
SEL A 10
11 +VS
00784-003
VS 8
SEL B 9
Mnemonic
RINA
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/A
VS
SEL B
SEL A
+VS
COMP
VOUT
RB
RF
RA
RINB
CH B+
CH B
CH A
Description
2.5 k Resistor to Noninverting Input of Op Amp A
Noninverting Input of Op Amp A
Differential Offset Adjustment
Differential Offset Adjustment
Common-Mode Offset Adjustment
Common-Mode Offset Adjustment
B or A Channel Status
Negative Supply
B Channel Comparator Input
A Channel Comparator Input
Positive Supply
Pin to Connect Internal Compensation Capacitor
Output Voltage
10 k Gain Setting Resistor
10 k Feedback Resistor
5 k Feedback Resistor
2.5 k Resistor to Noninverting Input of Op Amp B
Noninverting Input of Op Amp B
Inverting Input of Op Amp B
Inverting Input of Op Amp A
Rev. F | Page 7 of 20
CH B
CH A+
RIN A
CH A
Data Sheet
DIFF
OFF ADJ
AD630
20 19
18
CH B+
CM OFF ADJ 5
AD630
17
RINB
CM OFF ADJ 6
TOP VIEW
(Not to Scale)
16
RA
15
RF
14
RB
10 11 12 13
SEL A
+VS
COMP
VOUT
SEL B
VS 8
00784-004
Mnemonic
RINA
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
CM OFF ADJ
CM OFF ADJ
CHANNEL STATUS B/A
VS
SEL B
SEL A
+VS
COMP
VOUT
RB
RF
RA
RINB
CH B+
CH B
CH A
Description
2.5 k Resistor to Noninverting Input of Op Amp A
Noninverting Input of Op Amp A
Differential Offset Adjustment
Differential Offset Adjustment
Common-Mode Offset Adjustment
Common-Mode Offset Adjustment
B or A Channel Status
Negative Supply
B Channel Comparator Input
A Channel Comparator Input
Positive Supply
Pin to Connect Internal Compensation Capacitor
Output Voltage
10 k Gain Setting Resistor
10 k Feedback Resistor
5 k Feedback Resistor
2.5 k Resistor to Noninverting Input of Op Amp B
Noninverting Input of Op Amp B
Inverting Input of Op Amp B
Inverting Input of Op Amp A
Rev. F | Page 8 of 20
Data Sheet
AD630
10
1k
10k
100k
1M
FREQUENCY (Hz)
100
80
60
40
20
10
100
1k
10k
00784-008
RL = 2k
CL = 100pF
00784-005
15
100k
FREQUENCY (Hz)
15
CL = 100pF
f = 1kHz
UNCOMPENSATED
20
(V/s)
10
COMPENSATED
0
dt
dVO
40
20
60
5
10
100
1k
10k
100k
RESISTIVE LOAD ()
00784-006
1M
Figure 11.
18
dVO
vs. Input Voltage
dt
120
f = 1kHz
CL = 100pF
15
10
45
80
60
90
COMPENSATED
40
135
100
UNCOMPENSATED
00784-009
40
10
15
20
00784-007
10
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 9. Output Voltage Swing vs. Supply Voltage (See Figure 16)
Rev. F | Page 9 of 20
180
10M
00784-010
20
AD630
Data Sheet
20mV
10V
100
10V 20kHz
(Vi)
90
20mV/DIV
(Vo)
1mV
5s
100
90
1mV/DIV
(B)
10V/DIV
(Vo)
10
0%
500ns
TOP TRACE: Vo
BOTTOM TRACE: Vi
10V
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (B)
BOTTOM TRACE: Vo
50mV
50mV/DIV
(Vi)
Figure 15. Large Signal Inverting Step Response (See Figure 19)
1mV
100
90
1mV/DIV
(A)
10
0%
100mV
500ns
TOP TRACE: Vi
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: Vo
00784-013
100mV/DIV
(Vo)
10
0%
00784-012
20mV
00784-011
20mV/DIV
(Vi)
Figure 14. Small Signal Noninverting Step Response (See Figure 18)
Rev. F | Page 10 of 20
Data Sheet
AD630
TEST CIRCUITS
10k
5k
5k
Vi
TOP
TRACE
100pF
00784-105
VO
2k
1k
13
10k
MIDDLE
TRACE
(A)
30pF
VO
BOTTOM
TRACE
10k
TEKTRONIX
7A13
Figure 16. Test Circuit for Output Voltage vs. Frequecy, Resistive Load,
and Supply Voltage (See Figure 7, Figure 8, and Figure 9)
Figure 18. Test Circuit for Small Signal Noninverting Step Response
(See Figure 14)
15
5k
10k
2
20
13
19
18
10k
Vi
TOP
TRACE
CH A
CH B
VO
12
10k
15
20
2 CH A
12
13
10k
10k
HP5082-2811
9
10
00784-111
14
14
10k
VO
BOTTOM
TRACE
(B)
MIDDLE
TRACE
00784-112
16
Vi
2 CH A
12
00784-113
Vi
14 10k 15 20
Figure 19. Test Circuit for Large Signal Noninverting Step Response
(See Figure 15)
Rev. F | Page 11 of 20
AD630
Data Sheet
THEORY OF OPERATION
TWO WAYS TO LOOK AT THE AD630
The functional block diagram of the AD630 (see Figure 1)
shows the pin connections of the internal functions. An
alternative architectural diagram is shown in Figure 20. In this
diagram, the individual A and B channel preamps, the switch,
and the integrator output amplifier are combined in a single op
amp. This amplifier has two differential input channels, only
one of which is active at a time.
+VS
11
14
RA 5k
RB
10k
1
2
2.5k
A
20
RF
10k
13
19
18
17
B
12
2.5k
SEL B 9
00784-014
SEL A 10
8
VS
2
20
19
RB
10k
18
13
VO
14
9
10
Vi
RB
10k
VO =
RF
RA
Rev. F | Page 12 of 20
Vi
RB
10k
VO = (1+
RF
RB
RF
10k
RF
10k
00784-015
Vi
RA
5k 15
RF 10k
RA
5k
00784-016
16
) Vi
00784-017
15
Data Sheet
AD630
CIRCUIT DESCRIPTION
CH A+ CH B
2
20
CH B+
18
19
+VS 11
Q33
Q35
Q34
Q36
i73
i55
Q44
SEL A
10
Q52
Q53
Q62
Q65
Q67
Q70
13
VOUT
Q74
SEL B
C121
Q30
12
Q31
Q28
C122
Q29
Q24
Q3
Q4
i22
COMP
Q32
Q25
i23
DIFF
OFF ADJ
DIFF
OFF ADJ
CM
OFF ADJ
CM
OFF ADJ
Rev. F | Page 13 of 20
00784-018
VS 8
AD630
Data Sheet
FREQUENCY COMPENSATION
2k
10k
100k
2
20
13
VO
19
11.11k
18
12
7
SEL B
SEL A
CHANNEL
STATUS
B/A
9
10
8
V S
00784-019
Vi
2k
Rev. F | Page 14 of 20
Data Sheet
AD630
+5V
100k
100k
10
8
100
15V
00784-020
+5V
+15V
6.8k
AD630
Rev. F | Page 15 of 20
100k
7
22k
IN914s
2N2222
TTL INPUT
8
15V
00784-021
AD630
Data Sheet
APPLICATIONS INFORMATION
BALANCED MODULATOR
5V
MODULATION
INPUT
10k
CM
OFF ADJ
DIFF
OFF ADJ
4
2.5k
AMP A
12
11
20
2.5k
B
AMP B
17
10k
10k
18
19
AD630
CARRIER
INPUT
+VS
13
5k
14
MODULATED
OUTPUT
SIGNAL
15
16
COMP
9
10
00784-022
VS
MODULATION
INPUT
2.5k
10k
CM
OFF ADJ
6
DIFF
OFF ADJ
4
AMP A
11
20
2.5k
17
10k
18
19
CARRIER
INPUT
10k
AD630
COMP
5k
14
MODULATED
OUTPUT
SIGNAL
15
16
7
CARRIER
INPUT
OUTPUT
SIGNAL
10V
BALANCED DEMODULATOR
The balanced modulator topology described in the Balanced
Modulator section also acts as a balanced demodulator if a
double sideband suppressed carrier waveform is applied to
the signal input and the carrier signal is applied to the reference
input. The output under these circumstances is the baseband
modulation signal. Higher order carrier components that can
be removed with a low-pass filter are also present. Other names
for this function are synchronous demodulation and phasesensitive detection.
+VS
13
B
AMP B
MODULATION
INPUT
12
20s
00784-024
5V
10
00784-023
VS
Rev. F | Page 16 of 20
Data Sheet
AD630
AC BRIDGE
E1000
AD544
SCHAEVITZ
FOLLOWER
A LVDT
16 B 5k
1 2.5k
2.5kHz
2V p-p
SINUSOIDAL
EXCITATION
AD630
2 DEMODULATOR
20
14
10k
10k
15
A
19
B
17
13 100k
12
D
1F
2.5k
9
00784-025
PHASE
SHIFTER
10
]
500s/DIV
B. 200mV/DIV
C. 200mV/DIV
00784-027
A. 200mV/DIV
+15V
1V
400Hz
350
350
350
+IN
A
49.9
AD8221
REF
11
SEL B
+VS
16
RA
17
RINB
19
CH B
IN
AD630AR
VOUT 13
4.99k
4.99k
4.99k
2F
2F
2F
COMP 12
20
CH A
15
RF RINA SEL A VS RB
1
10
15V
Rev. F | Page 17 of 20
14
00784-026
350
AD630
Data Sheet
The test signal is produced by modulating a 400 Hz carrier
with a 0.1 Hz sine wave. The signals produced, for example,
by chopped radiation (that is, IR, optical) detectors may have
similar low frequency components. A sinusoidal modulation
is used for clarity of illustration. This signal is produced by a
circuit similar to Figure 28 and is shown in the upper trace of
Figure 34. It is attenuated 100,000 times normalized to the
output, B, of the summing amplifier. A noise signal that might
represent, for example, background and detector noise in the
chopped radiation case, is added to the modulated signal by the
summing amplifier. This signal is simply band limited, clipped
white noise. Figure 34 shows the sum of attenuated signal plus
noise in the center trace. This combined signal is demodulated
synchronously using phase information derived from the
modulator, and the result is low-pass filtered using a 2-pole
simple filter which also provides a gain of 100 to the output.
This recovered signal is the lower trace of Figure 34.
5V
5s
MODULATED SIGNAL (A)
(UNATTENUATED)
100
90
ATTENUATED SIGNAL
PLUS NOISE (B)
10
00784-029
OUTPUT
0%
5mV
CLIPPED
BAND LIMITED
WHITE NOISE
C
B 16
AD542
5k
15
20
19
100R
10k
1 2.5k
17 2.5k
100dB
ATTENUATION
AD630
13
AD542
B
100R
14 10k
C
OUTPUT
10
0.1Hz
9
MODULATED
CARRIER
400Hz
PHASE
CARRIER
REFERENCE
00784-028
LOW-PASS
FILTER
Rev. F | Page 18 of 20
Data Sheet
AD630
OUTLINE DIMENSIONS
0.080 (2.03) MAX
11
20
PIN 1
10
0.300 (7.62)
0.280 (7.11)
1.060 (28.92)
0.990 (25.15)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.320 (8.13)
0.300 (7.62)
0.150
(3.81)
MIN
0.100
(2.54)
BSC
0.015 (0.38)
0.008 (0.20)
11
10
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.100 (2.54)
BSC
0.060 (1.52)
MAX
0.210 (5.33)
MAX
0.015
(0.38)
MIN
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
SEATING
PLANE
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.430 (10.92)
MAX
Rev. F | Page 19 of 20
070706-A
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
AD630
Data Sheet
0.200 (5.08)
REF
0.100 (2.54) REF
0.015 (0.38)
MIN
0.075 (1.91)
REF
0.095 (2.41)
0.075 (1.90)
19
18
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.011 (0.28)
0.007 (0.18)
R TYP
0.075 (1.91)
REF
0.088 (2.24)
0.054 (1.37)
3
20
0.028 (0.71)
0.022 (0.56)
BOTTOM
VIEW
0.050 (1.27)
BSC
14
13
45 TYP
0.055 (1.40)
0.045 (1.14)
0.150 (3.81)
BSC
022106-A
0.100 (2.54)
0.064 (1.63)
11
20
7.60 (0.2992)
7.40 (0.2913)
10
10.65 (0.4193)
10.00 (0.3937)
2.65 (0.1043)
2.35 (0.0925)
0.30 (0.0118)
0.10 (0.0039)
COPLANARITY
0.10
1.27
(0.0500)
BSC
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
0.75 (0.0295)
45
0.25 (0.0098)
8
0
0.33 (0.0130)
0.20 (0.0079)
1.27 (0.0500)
0.40 (0.0157)
06-07-2006-A
ORDERING GUIDE
Model1
AD630JNZ
AD630KNZ
AD630ARZ
AD630ARZ-RL
AD630ADZ
AD630BDZ
AD630SD
AD630SD/883B
5962-8980701RA
AD630SE/883B
5962-89807012A
AD630SCHIPS
1
Temperature Range
0C to 70C
0C to 70C
25C to +85C
25C to +85C
25C to +85C
25C to +85C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
55C to +125C
Package Description
20-Lead Plastic Dual In-Line Package [PDIP]
20-Lead Plastic Dual In-Line Package [PDIP]
20-Lead Standard Small Outline Package [SOIC_W]
20-Lead Standard Small Outline Package [SOIC_W], 13" Tape and Reel
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
20-Terminal Ceramic Leadless Chip Carrier [LCC]
20-Terminal Ceramic Leadless Chip Carrier [LCC]
Chip
Rev. F | Page 20 of 20
Package Option
N-20
N-20
RW-20
RW-20
D-20
D-20
D-20
D-20
D-20
E-20-1
E-20-1