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doi: 10.14355/ijes.2014.0403.02
www.ijesci.org
jackchen@nuu.edu.tw
Introduction
Vertical-diffused MOS (VDMOS) ICs are quite
interesting in terms of high driving capability and
switching speed, and then are widely used in many
electronic systems such as power supply switch,
power rectifier, voltage regulator, motor driver, and
automatic electronics. This power MOSFETs have
been attractive because they have inherent advantages
of the fast switching response, excellent thermal
77
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Source
Gate
(A)
Source
Oxide
Poly Gate
Source
Epi-Layer
Substrate
Drain
(B)
FIG. 1 (A) TOP VIEW, (B) CELL CROSS-SECTIONAL VIEW AND
NORMAL CURRENT FLOW OF A VDMOS IC
Sample no.
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10
78
VESD (kV)
+1.50
+2.00
+2.00
+2.00
+2.50
+1.50
+2.00
+2.00
+2.00
+2.00
Failure condition
Leakage over 30%
Leakage over 30%
Leakage over 30%
Short to ground
Short to ground
Leakage over 30%
Leakage over 30%
Leakage over 30%
Leakage over 30%
Leakage over 30%
Sample no.
VESD (kV)
Failure condition
#1
-1.50
#2
-2.00
#3
-2.00
#4
-2.00
#5
-2.00
#6
-1.50
Short to ground
#7
-2.00
Short to ground
#8
-2.00
#9
-2.00
#10
-2.50
Sample no.
VESD (kV)
Failure condition
#1
+0.80
#2
+1.00
Short to ground
#3
+1.00
Short to ground
#4
+1.00
#5
+1.20
Short to ground
#6
+0.70
#7
+0.80
Short to ground
#8
+0.80
Short to ground
#9
+1.20
Short to ground
#10
+1.20
Sample no.
VESD (kV)
Failure condition
#1
-0.60
#2
-0.70
Short to ground
#3
-0.80
#4
-0.80
Short to ground
#5
-0.90
#6
-0.70
#7
-0.70
#8
-0.90
Short to ground
#9
-0.90
#10
-0.90
Short to ground
Sample no.
VESD (kV)
Failure condition
#1
+0.35
Short to ground
#2
+0.40
Short to ground
#3
+0.30
Short to ground
#4
+0.20
Short to ground
#5
+0.30
#6
+0.30
#7
+0.40
#8
+0.40
#9
+0.30
#10
+0.30
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Sample no.
VESD (kV)
Failure condition
#1
-0.35
Short to ground
#2
-0.30
Short to ground
#3
-0.35
Short to ground
#4
-0.20
Short to ground
#5
-0.30
#6
-0.30
#7
-0.30
Short to ground
#8
-0.30
#9
-0.20
#10
-0.30
(A)
(B)
FIG. 3 ESD FAILURE SITES ARE ANALYZED BY THE EMMI AS
(A) MM ZAPPING +, (B) MM ZAPPING
(A)
(B)
(A)
(B)
FIG. 2 ESD FAILURE SITES ARE ANALYZED BY THE EMMI AS
(A) HBM ZAPPING +, (B) HBM ZAPPING
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80
VESD
Zapping +
Zapping
HBM
1.95 kV
-1.95 kV
MM
0.97 kV
-0.79 kV
CDM
0.325 kV
-0.29 kV
Source
Source
Gate
Drain
(A)
Source
Gate
Source
Drain
(B)
FIG. 5 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER MM ESD STRESSED
(MAGNIFICATION 4000)
Source
Gate
Drain
(A)
Source
Gate
Drain
(B)
FIG. 6 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER HBM ESD STRESSED
(MAGNIFICATION 4000)
Source
Gate
Drain
(A)
Source
Gate
Drain
(B)
FIG. 7 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER CDM ESD STRESSED
(MAGNIFICATION 4000)
L
R
Gate Pad
Bonding
R
R
L
L
Bonding Pad
(Gate)
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R
L
Zener
clamp-diode
rings
Gate Pad
FIG. 9 THE TWO-DIMENSIONAL RLC EQUIVALENT CIRCUITS
FOR A VDMOS IC
(A)
Drain
Gate
Z1
(B)
Z2
Source
FIG. 10 (A) TOP VIEW IMAGE (NEAR THE GATE PAD), (B)
EQUIVALENT CIRCUIT OF A VDMOS WITH THE TYPE-1 ESD
PROTECTION STRUCTURE
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(A)
Gate
Source
N+
P+
N+
P+
N+
Poly
Zener
Diodes
Oxide
N- Epi-Layer
n+ Substrate
metal
(B)
Drain
FIG. 11 (A)SAMPLE STAINED, AND (B) SCHEMATIC CROSSSECTION VIEW OF A VDMOS WITH THE TYPE-1 ESD
PROTECTION STRUCTURE IN FIG. 10(A)
Zener
clamp-diode
rings
Gate Pad
A. Fiel, T. Wu. "MOSFET failure modes in the zero-voltageswitched full- bridge switching mode power supply
applications." Sixteenth Annual IEEE Applied Power
Gate-triggered
diode
(A)
Drain
Z1
Gate
Z2
(B)
Source
Conclusion
The ESD post-zapped failure and how to protect of
power VDMOS ICs due to HBM, MM, and CDM
stresses are systematically examined in this work.
These devices that experience ESD stress are analyzed
by the photo emission microscope image, cross-section
SEM, and I-V characteristic curves. The ESD failure
mode in these power MOSFETs were caused by a gate
oxide breakdown near n+ region in the source end as
an ESD zapping. It can be found that VESD(HBM) >
VESD(MM) > VESD(CDM) relation is obtained. The
ESD failure sites will be more closed to the gate
bonding pad as with a positive zap and higher dV/dt
pulse such as in CDM testing. These destroyed-site
82
Shui-Ming
Cheng,
Ming-Hsiang
Song.
power
technology."
34th
Electrical
Thermal
Consideration."
IEEE
International
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diode
in
silicon
nanowire
technology."
13.
rectifiers
for
silicon-controlled
28th
triggering
MOSFET
for
High
Frequency
Switching
467.
2234.
MIL-STD-883J
Method
3015.9.
"Electrostatic
discharge
of
power-MOSFET
to
large
capacity
converter."
1170-1175.
S.J.C.H.
Theeuwen,
H.F.F.
Jos.
"High-
(2004): 273-280.
Seventh
(2014): 1136-1145.
Annual
IEEE
Applied
Power
Electronics
Yali Xiong, Shan Sun, Hongwei Jia, P. Shea, Z.J. Shen. "New
83
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Toyoda,
Hideaki
Katakura,
Takatoshi
Ooe,
trench
MOSFET."
25th
International
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