International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

doi: 10.14355/ijes.2014.0403.02

www.ijesci.org

EMMI Failure-Distributed Analysis of ESD

Zapping and Protection Designs in Power
VDMOS ICs
Shen-Li Chen*, Wen-Ming Lee, Chi-Ling Chu
Dept. of Electronic Engineering, National United University
1, Lien-Da Road, MiaoLi City 36003, Taiwan
*

jackchen@nuu.edu.tw

Received 9 February 2014; Accepted 28 February 2014; Published 16 April 2014

2014 Science and Engineering Publishing Company
Abstract
This paper deals with a detailed study of ESD failure modes,
failures distribution and how to strengthen of the VDMOS
ICs used for power applications. The ESD post-zapped
failure of power VDMOS ICs due to HBM, MM, and CDM
stresses are examined in this work. Through standard failure
analysis techniques by using EMMI and SEM were applied
to identify the failure locations. It is found that the ESD
robustness is VESD(HBM) > VESD(MM) > VESD(CDM) for these
non-ESD protected DUTs. Meanwhile, the ESD failure sites
will be closed to the gate bonding pad as with a positive
zapping and higher dV/dt pulse such as in CDM testing.
And, the failure mappings have been studied to establish the
difference in damaged features of HBM, MM, and CDM.
Furthermore, the ESD protection designs of power VDMOS
ICs are also addressed in this work. The first ESD
incorporated design is Zener diodes back-to-back clamping
the gate-to-source pad, and on the other hand, another one
excellent design contains two Zener diodes clamping the
gate-to-source and gate-to-drain terminals of a VDMOS,
respectively.
Keywords
Bipolar-Cmos-Dmos (BCD); Charged-Device Model (CDM);
Electrostatic Discharge (ESD); Emission Microscope (EMMI);
Fowler-Nordhein (FN) Tunnelling; Human-Body Model (HBM);
Machine Model (MM); Vertical-Diffused Mos (VDMOS)

Introduction
Vertical-diffused MOS (VDMOS) ICs are quite
interesting in terms of high driving capability and
switching speed, and then are widely used in many
electronic systems such as power supply switch,
power rectifier, voltage regulator, motor driver, and
automatic electronics. This power MOSFETs have
been attractive because they have inherent advantages
of the fast switching response, excellent thermal

stability, high input impedance, and the absence of the

classical second breakdown, which makes their
application in the high frequency switching power
supply. Nevertheless, the VDMOS is a most popular
vertical MOSFET device. This device structure can be
evolved from the MOSFET and bipolar technologies.
ESD events affect the reliability of electronic
components appeared to be increasingly serious and
may result in a low yield of electronic products which
causes huge losses. According to the statistic
investigation, more than 50% failures in silicon
semiconductor integrated circuit are due to ESD/EOS
damages. Therefore, the ESD immunity is considered
as the major reliability requirement issue in the
electronic system design. However, a VDMOS is
commonly used in high voltage applications,
therefore, the issue of ESD damage, or device
degradation and ESD protection should be
considerable attention as well. Unfortunately, many
ESD protection studies and efforts are well focused on
the modern low-voltage VLSI era; seldom literatures
are reported about this VDMOS topic.
Experimental Details
Here, the VDMOS DUTs are with a vertical epi-layer
fabricated in a power technology for power
applications. This VDMOS IC is built up from many
basic vertical MOSFET cells in parallel. The top view
and cell cross-sectional view of a VDMOS IC is shown
in Fig. 1. A unit cell has two source regions, one gate
electrode and a bottom drain electrode. Normally, two
conductive channels will be formed and flowed, and
the operation of this VDMOS relies upon the
formation of conduction layer at the surface of the
device.

77

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International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

TABLE 2 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS HBM ZAPPING

Source

Gate

(A)
Source

Oxide

Poly Gate

Source

Epi-Layer

Substrate
Drain
(B)
FIG. 1 (A) TOP VIEW, (B) CELL CROSS-SECTIONAL VIEW AND
NORMAL CURRENT FLOW OF A VDMOS IC

In the ESD immunity level measurement, we used a

KeyTek ESD test machine. ATE machine model is
KeyTek 7/4 ZAPMASTER, the test waveforms are
confirmed the EOS/ESD test standards. The ESD test
models were Human-Body Model (HBM), Machine
Model (MM), and Socketed Charged-Device Model
(CDM), respectively. For HBM, the minimum stressing
voltage was set to be 500 V, every stressing step was
kept to 500 V, and the maximum stress voltage was
up to 8000 V. The minimum stress voltage was set to
be 100 V, every stressing step was kept to 100 V, and
the maximum stress voltage was up to 2000 V for
MM. As for CDM, the minimum stress voltage was set
to be 100 V, every stressing step was kept to 50 V,
and the maximum stress voltage was up to 1000 V.
As for every stress model, the experiments presented
here were grouped into two classes, i.e., DUTs will be
zapped a positive or negative polarity voltage relative
to source end when the source and drain ends were
common grounded. The failure criterion was set to be
I= 1 A as the voltage variance over 30% (Vgate Vsource & drain). For each test model and stressing
voltage polarity, ten DUT samples were taken,
therefore, total sixty DUTs were used in these ESD
testing. And, the testing results and failure conditions
of these non-ESD protected DUTs are shown in Tables
1~ 6.
TABLE 1 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS HBM ZAPPING +

Sample no.
#1
#2
#3
#4
#5
#6
#7
#8
#9
#10

78

VESD (kV)
+1.50
+2.00
+2.00
+2.00
+2.50
+1.50
+2.00
+2.00
+2.00
+2.00

Failure condition
Leakage over 30%
Leakage over 30%
Leakage over 30%
Short to ground
Short to ground
Leakage over 30%
Leakage over 30%
Leakage over 30%
Leakage over 30%
Leakage over 30%

Sample no.

VESD (kV)

Failure condition

#1

-1.50

Leakage over 30%

#2

-2.00

Leakage over 30%

#3

-2.00

Leakage over 30%

#4

-2.00

Leakage over 30%

#5

-2.00

Leakage over 30%

#6

-1.50

Short to ground

#7

-2.00

Short to ground

#8

-2.00

Leakage over 30%

#9

-2.00

Leakage over 30%

#10

-2.50

Leakage over 30%

TABLE 3 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS MM ZAPPING +

Sample no.

VESD (kV)

Failure condition

#1

+0.80

Leakage over 30%

#2

+1.00

Short to ground

#3

+1.00

Short to ground

#4

+1.00

Leakage over 30%

#5

+1.20

Short to ground

#6

+0.70

Leakage over 30%

#7

+0.80

Short to ground

#8

+0.80

Short to ground

#9

+1.20

Short to ground

#10

+1.20

Leakage over 30%

TABLE 4 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS MM ZAPPING

Sample no.

VESD (kV)

Failure condition

#1

-0.60

Leakage over 30%

#2

-0.70

Short to ground

#3

-0.80

Leakage over 30%

#4

-0.80

Short to ground

#5

-0.90

Leakage over 30%

#6

-0.70

Leakage over 30%

#7

-0.70

Leakage over 30%

#8

-0.90

Short to ground

#9

-0.90

Leakage over 30%

#10

-0.90

Short to ground

TABLE 5 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS CDM ZAPPING +

Sample no.

VESD (kV)

Failure condition

#1

+0.35

Short to ground

#2

+0.40

Short to ground

#3

+0.30

Short to ground

#4

+0.20

Short to ground

#5

+0.30

Leakage over 30%

#6

+0.30

Leakage over 30%

#7

+0.40

Leakage over 30%

#8

+0.40

Leakage over 30%

#9

+0.30

Leakage over 30%

#10

+0.30

Leakage over 30%

International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

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TABLE 6 ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS AS CDM ZAPPING

Sample no.

VESD (kV)

Failure condition

#1

-0.35

Short to ground

#2

-0.30

Short to ground

#3

-0.35

Short to ground

#4

-0.20

Short to ground

#5

-0.30

Leakage over 30%

#6

-0.30

Leakage over 30%

#7

-0.30

Short to ground

#8

-0.30

Leakage over 30%

#9

-0.20

Leakage over 30%

#10

-0.30

Leakage over 30%

(A)

EMMI Inspection and SEM Sample

Preparation
All of these non-ESD protected VDMOS devices will
be destroyed after several ESD zapping pulses. In
order to find out the failure sites, a bias between gate
and source-drain electrodes was applied by a
Tektronix 576 curve tracer, the leakage points will be
detected by a Hamamatsu PHEMOS-200 photon
emission microscope (EMMI). Every emission image
was stored in the computer and then a statistical
evaluation of the failure sites distribution for HBM,
MM, and CDM stressing were shown in Figs 2~ 4,
respectively.
In order to realize the ESD failure location, we
removed the ESD destroyed die from the lead frame
after an EMMI inspection. For more convenience, we
placed the die in a limpid resin. After thirty minutes
baking about 50C, this die can be fixed within the
resin. Before the lapping polish, we must realize
clearly where the failure site is. Finally, cross-sectional
view of an ESD destroyed cell was also inspected by
the SEM.

(B)
FIG. 3 ESD FAILURE SITES ARE ANALYZED BY THE EMMI AS
(A) MM ZAPPING +, (B) MM ZAPPING

(A)

(B)

FIG. 4 ESD FAILURE SITES ARE ANALYZED BY THE

EMMI AS (A) CDM ZAPPING +, (B) CDM ZAPPING

Experiment Results and Discussion

(A)

(B)
FIG. 2 ESD FAILURE SITES ARE ANALYZED BY THE EMMI AS
(A) HBM ZAPPING +, (B) HBM ZAPPING

From Tables 1~ 6, the average ESD immunity levels of

HBM, MM, and CDM stressing in the VDMOS ICs
were shown in Table 7. From these measurement data,
it is found that the ESD testing results of separated ten
DUTs are almost similar for positive or for negative
polarity stress. And, VESD(HBM)> VESD(MM)>
VESD(CDM) relation is obtained for these non-ESD
protected DUTs, which was caused by the rising and
falling time of a stress pulse, therefore, the transient
displacement current varied inversion accordingly.
Obviously, these non-ESD protected VDMOS DUTs
do not meet the basic reliability requirement of ESD
immunity commercially.
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International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

In general, the Fowler-Nordhein (FN) tunnelling will

be occurred when a positively (negatively) high
voltage zaps to the gate electrode, meanwhile, the
source/drain ends were common grounded. Due to a
high electric field, the MM failure mode in this power
VDMOS was caused by the gate oxide breakdown
localized near n+ region in the source end as an ESD
zapping, for example as MM 200-V, which were
shown in Fig. 5. Furthermore, the ESD failure damages
under an HBM 2-kV and CDM 1-kV stresses were
caused by the gate material molten near the gate pad
and tunnelled through the oxide layer into silicon
epitaxial layer shown in Figs 6 and 7.
According to the SEM photographs of Figs 5~ 7, the
MM destruction manner revealed the FowlerNordhein (FN) tunnelling effect. When the source and
drain ends are grounded, and a high positive voltage
applied at the gate electrode, due to the electron
concentration of source n+ region is extremely highest
moreover the equivalent resistance to be smallest,
therefore, a extremely high electric current (to source
end) will penetrate the oxide layer shown in Fig. 5(b).
The Fig. 6(b) is sampled from an HBM destruction
area; a melting phenomenon of poly-gate material
nearby the gate electrode with the silicon epitaxial
layer is occurred. High current transiently induced a
local thermal hot-spot from an HBM ESD pulse was
easy to produce this poly-gate material moltenly
penetrated into dielectric oxide layer and melted
mutually with the epi-layer silicon. Then, the
composition profile will appear considerably rough.
Meanwhile, the CDM damage is quite similar to the
HBM destruction level which was shown in Fig. 7(b).
The device electrical characterizations before/after
zapping were also measured by an HP4145B
semiconductor parameter analyzer. After a -0.5 kV
HBM pulse zapping, due to the holes injection the
threshold voltage of a device is changed. And, the
drain-to-source saturated current is increased too as
shown in Fig. 8. The FN tunnelling may be as the
charge injection mechanism near n+ region in the
source end as an ESD zapping. The gate electrode was
connected to gate bonding pad by the poly-silicon gate
and aluminum layer. As a result of the resistance R
and inductance L of gate connector, together with the
capacitance C of cell gate structure, cells of a VDMOS
form a parallel two dimensional low-pass filters (see
Fig. 9). In the case of positive ESD stress, see Figs 2(a),
3(a), and 4(a), the ESD failure sites will be more closed
to the gate bonding pad as with a positive zap and

80

higher dV/dt pulse such as in the CDM testing, which

were resulted from the low pass behaviour of the gate
structure controlled the failure sites distribution.
TABLE 7 AVERAGE ESD IMMUNITY LEVELS (VESD) OF VDMOS ICS

VESD

Zapping +

Zapping

HBM

1.95 kV

-1.95 kV

MM

0.97 kV

-0.79 kV

CDM

0.325 kV

-0.29 kV

Source

Source
Gate

Drain

(A)

Source

Gate

Source

Drain

(B)
FIG. 5 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER MM ESD STRESSED
(MAGNIFICATION 4000)

Source
Gate

Drain

(A)

Source
Gate

Drain

(B)
FIG. 6 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER HBM ESD STRESSED
(MAGNIFICATION 4000)

Source
Gate

Drain

(A)

International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

Source
Gate

Drain

(B)
FIG. 7 SEM PHOTOS OF A FAILURE VDMOS CELL AS (A)
BEFORE ESD STRESSED; AND (B) AFTER CDM ESD STRESSED
(MAGNIFICATION 4000)

FIG. 8 THE I-V CHARACTERISTICS FOR A VDMOS IC AS (A)

BEFORE ESD STRESSED; AND (B) AFTER ESD STRESSED (HBM
ZAPPING -0.5 KV)

L
R

Gate Pad
Bonding

R
R

L
L

Bonding Pad

(Gate)

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Zener diode Z1 will be collapsed, then also Z2 is

forward conducted, the ESD current has not injured
the gate oxide layer, which will avoid damages in the
IC interior. When a negative ESD pulse zapped into
the gate electrode, also due to the Z2 Zener diode
collapsed, it obtains a conductive way of ESD current
again.
Figure 11(a) is cross-sectional SEM photograph of a
VDMOS cell with the type-1 ESD protection unit
(magnification 4000). From this picture, a conduction
path paralleled and connected the gate pad and source
electrode by a Zener diodes film with thickness about
0.5-m (for example the white arrow indicated). These
diodes are composed of five sections, i.e. from left to
right be n+, p+, n+, p+, and n+ shown in Fig. 11(b).
Furthermore, due to these Zener diodes rings will
surround the gate pad, even if there is 0.5-m
thickness, also sufficiently conducts a heavy ESD
current.
Moreover, a VDMOS IC with the type-2 ESD
protection structure can have more perfect ESD
capability shown in Fig. 12. The entire protection
circuit is composed by a power MOSFET itself, drainto-gate and gate-to-source Zener diodes. This wholechip protection can let a VDMOS IC with a good ESD
resists to defense any direction transient pulse,
therefore, this IC have extremely well ESD ability.
Finally, in HBM ESD testing, the ESD immunity level
of a VDMOS IC with type-2 ESD protection structure
is greater than 8-kV for any testing combination.

R
L

Zener
clamp-diode
rings

Gate Pad
FIG. 9 THE TWO-DIMENSIONAL RLC EQUIVALENT CIRCUITS
FOR A VDMOS IC

ESD Protection Designs in the VDMOS

Gate-triggered and voltage clamping Zener structures
have been commonly used and protected in VLSI
CMOS and high-voltage BCD circuits. Therefore, the
type-1 ESD protection unit of a power VDMOS IC is
designed and located around the gate pad, its topview and equivalent circuit shown in Fig. 10. This
protection circuit is constituted by a set of back-toback Zener diodes in poly-Si film, one end of
protection circuit was connected to the gate electrode;
another end was connected to the source end. When a
positive ESD pulse (voltage) zapped into this gate, the

(A)
Drain

Gate

Z1

(B)

Z2
Source

FIG. 10 (A) TOP VIEW IMAGE (NEAR THE GATE PAD), (B)
EQUIVALENT CIRCUIT OF A VDMOS WITH THE TYPE-1 ESD
PROTECTION STRUCTURE

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International Journal of Energy Science (IJES) Volume 4 Issue 3, June 2014

(A)
Gate

Source

N+

P+

N+

P+

N+

Poly
Zener
Diodes

Oxide
N- Epi-Layer
n+ Substrate
metal

(B)

Drain

FIG. 11 (A)SAMPLE STAINED, AND (B) SCHEMATIC CROSSSECTION VIEW OF A VDMOS WITH THE TYPE-1 ESD
PROTECTION STRUCTURE IN FIG. 10(A)
Zener
clamp-diode
rings

Gate Pad

distributions can be well explained by the low pass

characteristic of 2-D equivalent circuits of a VDMOS.
Although a power VDMOS IC can be operated at the
high voltage and high current, but speaking of on
kilovolt ESD event, the power transistor is still frail.
Therefore, an embedded ESD protection circuit will
promote its anti-ESD ability. This paper provides two
kind of ESD protection constructions, one is with a set
of back-to-back Zener diodes, one end of protection
circuit was connected to the gate electrode, another
end was connected to the source end; Another one, the
entire protection circuit is composed by a power
MOSFET itself, drain-to-gate and gate-to-source
clamping Zener diodes.
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Takatoshi

Ooe,

Masanobu Iwaya, Hitoshi Sumida. "60V-class power IC

technology for an intelligent power switch with an
integrated

trench

MOSFET."

25th

International

Symposium on Power Semiconductor Devices and ICs

(2013): 147-150.
Shen-Li Chen was born in 1958, joined the ERSO, ITRI,
Taiwan in 1987, and worked at the R&D department

84

responsible for reliability analysis in submicron circuits. He

received Ph.D. degree from National Tsing-Hua University,
Taiwan, in 1992. After then, he also acted a director of AX
Electronics Corporation in R&D division, focused on I/O
ESD/Latch-up cells design especially used in HV processes
and the DC-DC analog circuit design. In 2001, he joined the
department of Electronic Engineering of National United
University, Taiwan, as an associate professor.
In 2003, he was the chairman of dept. electronic engineering
of National United University, Taiwan. In 2013, he also was
an adjunct professor of Software and Microelectronics
School at Wuxi of Peking University, China. Recently, he
continues to pursue his research interests in the modeling
and characterization of HV power devices, and high ESD/LU
immunity designs in VLSI and power electronics.