B.

TECH DEGREE EXAMINATION, MAY 2014

FOURTH SEMESTER
Branch: Electronics & Communication Engineering
EC010 406 ANALOG CIRCUITS II

1. Define and explain CMRR. What is its significance?

The common-mode rejection ratio (CMRR) of a differential amplifier (or other device) is the
rejection by the device of unwanted input signals common to both input leads, relative to the
wanted difference signal. An ideal differential amplifier would have infinite CMRR; this is not
achievable in practice. A high CMRR is required when a differential signal must be amplified in
the presence of a possibly large common-mode input.
Ideally, a differential amplifier takes the voltages,

and

on its two inputs and produces an

output voltage
, where
is the differential gain. However, the output
of a real differential amplifier is better described as

where

is the common-mode gain, which is typically much smaller than the differential gain.

The CMRR is defined as the ratio of the powers of the differential gain over the common-mode
gain, measured in positive decibels (thus using the 20 log rule):

he 741 (a common op-amp chip) has a CMRR of 90 dB, which is reasonable in most cases. A
value of 70 dB may be adequate for applications which are insensitive to the effects on amplifier
output;some high-end devices may use op-amps with a CMRR of 120 dB or more.

2. Draw the internal circuit of 741 op-amp and explain it in detail.

An operational amplifier is a direct coupled high gain amplifier consisting of one or more
differential (OPAMP) amplifiers and followed by a level translator and an output stage
The block diagram of OPAMP is shown in fig. 1.

Fig. 1
The input stage is a dual input balanced output differential amplifier. This stage provides most of
the voltage gain of the amplifier and also establishes the input resistance of the OPAMP.The
intermediate stage of OPAMP is another differential amplifier which is driven by the output of
the first stage. This is usually dual input unbalanced output.

Because direct coupling is used, the dc voltage level at the output of intermediate stage is well
above ground potential. Therefore level shifting circuit is used to shift the dc level at the output
downward to zero with respect to ground. The output stage is generally a push pull
complementary amplifier. The output stage increases the output voltage swing and raises the
current supplying capability of the OPAMP. It also provides low output resistance.

3. Draw op-amp buffer. Explain its applications. Obtain its voltage gain.
Voltage follower (unity buffer amplifier)

Used as a buffer amplifier to eliminate loading effects (e.g., connecting a device with a high
source impedance to a device with a low input impedance).

(realistically, the differential input impedance of the op-amp itself, 1 M to 1 T)

I n the above figure a non-inverting voltage follower is shown. The input voltage V1 is applied
on the non-inverting pin of the op-amp. Here the feedback resistance Rf is zero i.e. short circuit.
The gain of the amplifier reduces from ideally infinity to unity.
If V1 is the input voltage at the inverting pin and V0 is the output voltage of the op-amp, then
V0 is exactly equal to V1 in magnitude. Hence the gain is given by the following equation.
Gain=V0/V1= 1
Voltage follower is generally used for amplify the current of a signal keeping the voltage same
incase of driving high output loads (low resistance circuits).

4. What is a Notch filter? Explain its characteristics.

The narrow band reject filter is also called a notch filter. Because of its higher Q, which exceeds
10, the bandwidth of the narrow band reject filter is much smaller than that of a wide band reject
filter.

The most widely used

notch filter is the twin-T
network illustrated in fig.
(a). This is a passive filter
composed of two T-shaped networks. One Tnetwork is made up of two resistors and a
capacitor, while the other is made of two
capacitors and a resistor.One
drawback of above notch filter (passive twinT network) is that it has relatively low figure
of merit Q. However, Q of the network can be
increased significantly if it is used with the voltage follower, as illustrated in fig. (a). Here the
output of the voltage follower is supplied back to the junction of R/2 and 2 C. The frequency
response of the active notch filter is shown in fig (b).

5. Differentiate ADC from DAC. Explain the difference.

In electronics, a digital-to-analog converter (DAC, D/A, D2A or D-to-A) is a function that
converts digital data (usually binary) into an analog signal (current, voltage, or electric charge).
An analog-to-digital converter (ADC) performs the reverse function.

Part B
6. Explain the need for current mirror circuits with neat diagrams.
A current mirror is a circuit designed to copy a current through one active device by controlling
the current in another active device of a circuit, keeping the output current constant regardless of
loading. The current being 'copied' can be, and sometimes is, a varying signal current.

7. Define and explain : 1. Slew rate 2. SVRR

Slew Rate:
Slew rate is defined as the maximum rate of change of output voltage per unit of time under large
signal conditions and is expressed in volts / msecs.

Supply voltage Rejection Ratio: (SVRR)

SVRR is the ratio of the change in the input offset voltage to the corresponding change in power
supply voltages. This is expressed in m V / V or in decibels, SVRR can be defined as
SVRR = D Vio / D V
Where D V is the change in the input supply voltage and D Vio is the corresponding change in
the offset voltage.
For the 741C, SVRR = 150 V / V.

8. Draw an op- amp instrumentation amplifier and explain.

Instrumentation amplifier is a kind of differential amplifier with additional input buffer stages.
The addition of input buffer stages makes it easy to match (impedance matching) the amplifier

with the preceding stage. Instrumentation are commonly used in industrial test and measurement
application. The instrumentation amplifier also has some useful features like low offset voltage,
high CMRR (Common mode rejection ratio), high input resistance, high gain etc.
A circuit providing an output based on the difference between two inputs (times a scale factor) is
given in the above figure. In the circuit diagram, opamps labelled A1 and A2 are the input
buffers. Anyway the gain of these buffer stages are not unity because of the presence of R1 and
Rg. Op amp labelled A3 is wired as a standard differential amplifier. R3 connected from the
output of A3 to its non inverting input is the feedback resistor. R2 is the input resistor. The
voltage gain of the instrumentation amplifier can be expressed by using the equation below.
Voltage gain (Av) = Vo/(V2-V1) = (1 + 2R1/Rg ) x R3/R2

9. Explain the characteristics of an ideal op-amp in detail.

An all-pass filter is a signal processing filter that passes all frequencies equally in gain, but
changes the phase relationship between various frequencies. It does this by varying its phase
shift as a function of frequency.
At high frequencies, the capacitor is a short circuit, thereby creating a unity-gain voltage buffer
(i.e., no phase shift).
At low frequencies and DC, the capacitor is an open circuit[disambiguation needed] and the
circuit is an inverting amplifier (i.e., 180 degree phase shift) with unity gain.
At the corner frequency =1/RC of the high-pass filter (i.e., when input frequency is 1/(2RC)),
the circuit introduces a 90 degree shift (i.e., output is in quadrature with input; it is delayed by a
quarter wavelength).

10. Explain the working principle o0f flash ADC with a neat diagram.
Also called the parallel A/D converter, this circuit is the simplest to understand. It is formed of a
series of comparators, each one comparing the input signal to a unique reference voltage. The

comparator outputs connect to the inputs of a priority encoder circuit, which then produces a
binary output. The following illustration shows a 3-bit flash ADC circuit:

Vref is a stable reference voltage provided by a precision voltage regulator as part of the
converter circuit, not shown in the schematic. As the analog input voltage exceeds the reference
voltage at each comparator, the comparator outputs will sequentially saturate to a high state. The
priority encoder generates a binary number based on the highest-order active input, ignoring all
other active inputs.

Part C
11. Discuss the characteristics of an ideal op-amp in detail.
Ideal characteristics of OPAMP
1. Open loop gain infinite
2. Input resistance infinite
3. Output impedance zero
4. Bandwidth infinite

5. Output voltage is zero when input voltage is zero,ie

Offset voltage is zero
6. CMRR is infinite
7.Slewrate is infinite
8.Perfect balance because of infinite slewrate.
9.Drift of characteristics with temperature is nil.

OR
12. Explain in detail the following
1.Multistage differential amplifier
2.MOS differential amplifier
1.Multistage differential amplifier

Working
A reference bias current IBIAS is generated either externally or using on-chip circuits
The current mirror formed by M8 and M5 supplies the differential pair M1 and M2 with
bias current.

The i/p differential pair is actively loaded with the current mirror formed by M3 and M4
The second stage consists of M6 which is a common source amplifier actively loaded
with M8.
The voltage gain of the first stage
A1=-gm1(r02//r04)
A2=-gm1(r06//r07)
2.MOS differential amplifier
Resistively loaded mos differential amplifier

Zss = Rss//Css
Yss = 1/Rss +SCss
Actively loaded mos differential amplifier

13. (i) Draw a 2 stage op-amp circuit and explain it in detail.

First stage formed by transistors M1 to M4

Second stage formed by transistors M5 to M7
Total Gain = A1*A2
A1 is the gain of first stage
A2 is the gain of second stage
A1 = gm1Ro
Ro = Rup //Rdown
Rup = r03
Rdown = r01
Ro = r03// r01
A1 = gm1(r03// r01)
A2 = gm5(r05// r07)

( ii) Derive an expression for bandwidth of an op-amp.

Finite gain and limited bandwidth are the most serious op-amp non idealities(in ideal case
gain and bandwidth is infinity but in practical case these parameters are infinite.
Frequency dependence of the open loop gain
The differential open loop gain of an opamp is not infinite,rather it is finite and
decreases with frequency.

From the above figure gain is high at dc and low frequencies,it starts to fall off at rather low
frequency.The uniform -20db/decade gain roll off shown is typical of internally compensated opamp.Thesse are units that have a network(usually a single capacitor)included within the same IC
chip whose function is to cause the op-amp gain to have the single time constant(STC) low pass
response shown.This process of modifying the open loop gain is termed frequency
compensation,and its purpose is to ensure that op-amp circuits will be stable.
The gain A(s) of an internally compensated op-amp may be expressed as
A(s) = A0/1+s/wb
Put s = jw
A(jw) = A0/1+jw/wb
= A0 wb /wb+jw
Consider wb << w
A(jw) = A0wb/jw
A0wb/w
From above figure the gain reaches to unity at a frequency denoted by wt and is given by
wt = A0wb
A(jw) = wt/jw
For w>>wb the open loop gain becomes

A(s) = A0/1+s/wb
=

A0 wb /wb+s

w>>wb
= A0 wb/s where A0wb = wt
A(s) = wt/s
= wt/w = ft/f
Increasing f by a factor of 10 results in reducing

by a factor of 10 (20 db).

OR
14. Discuss in detail the frequency compensation and slew rate in 2 stage
opamp with neat diagrams
The need for compensation arises because BH doesnot drop to unity well before <BH
reaches -180

Frequency compensation by
1) Moving phase cross over point Px out
2) Moving gain cross over point Gx in
For getting a stable system

1) Minimizing the overall phaseshift thus pushing the phase cross over out.
2) Dropping the gain thereby pushing the gain crossover in.
Miller compensation

Pole splitting as a result of Miller compensation

Miller compensation entails a very important property,it moves the outpole away from the origin
as shown in above figure.This effect is called pole splitting.In summary miller compensation
moves the interstage pole towards the origin and the o/p pole away from the origin allowing a
much greater bandwidth than that obtained by merely connecting the compensation capacitor
from one node to ground.

15. Explain the applications of OP-Amp in detail.Derive the expressions for

voltage for non-inverting amplifier and summer.
Applications of op-amp
1.Inverting Amplifier

Gain,ACL=VO/VIN = -R2/R1
2. Non-Inverting Amplifier

VIN = R1* VO/R1+R2

VO/VIN = R1+R2/ R1
Gain,ACL = VO/VIN = 1+R2/R1
3. Voltage Follower

VOUT = VIN

4.Integrator

VOUT = -1/RINC VIN (dt) +VOUT(0)

Waveforms

5. Differentiator

VOUT = -RC dVIN/dt

Waveforms

6. Summing Amplifier
a.Non-inverting Summing Amplifier

Va-V1/R + Vb-V1/R + Vc-V1/R = 0

V1 = (Va/R + Vb/R + Vc/R) / (1/R + 1/R + 1/R)
For a non-inverting amplifier
VO= ( 1+Rf/R1) V1
VO= ( 1+Rf/R1) (Va/R + Vb/R + Vc/R) / (1/R + 1/R + 1/R)

R = R1 =Rf/2
VO = ( Va + Vb + Vc)/3

b.Inverting Summing Amplifier

Va/Ra + Vb/Rb + Vc/Rc = - Vo/Rf

Vo = - Rf( Va/Ra + Vb/Rb + Vc/Rc )

OR
16. Draw an OP-amp RC Phase shift Oscillator circuit.Explain its
Working principle in detail.Derive the condition for oscillation
RC Phase Shift Oscillator

Opamp acts as the amplifying stage and RC network acts as feedback circuit.
The feedback circuit provides feedback voltage back into the input.
The opamp is used in inverting mode, so the signal is shifted by 180 at the output.
An additional 180 degree phase shift is provided by RC cascaded network.So the total phase
shift is 360 degrees.
Frequency of oscillation Fo = 1/26RC
Conditions for oscillation
1.The magnitude of the loopgain must be atleast 1.
2. The total phase shift around the loop must be 360 or 0
Degrees.
3.There should be an amplifier section and a feedback section.
Output waveform

17. Bring out the design details of first order high pass filter,with an
example.
First order high pass filter
Circuit diagram

Frequency Response

All Frequencies higher than FC are pass band frequencies

For the first order high pass filter the output voltage is
VO = (1+ RF/R1) V1
= (1+ RF/R1) VIN j2fRC/1+ j2fRC
VO/ VIN = AF (F/FC) / (1+j F/FC)

OR
18. Give an account on
1.Switched capacitor integrator
2.First order SC filter

Switched capacitor integrator

Consider the pole in figure.The transfer function is

19.Draw a dual slope ADC circuit.Explain its principle of

Operation and applications in detail.

Dual-Slope ADC

Working

Now assume positive input voltage is applied to the input through the switch
(SW) as selected by the control logic.
Inverting input of A1 is at virtual ground
Assuming that Vin is constant for a period of time, there will be constant current
through the input resistor R and therefore through the capacitor C.
Capacitor C will charge linearly because the current is constant, and as a result,
there will be a negative-going linear voltage ramp on the output of A1.
Start by assuming counter is reset and the output of the integrator is zero.
When the counter reaches a specified count, it will be reset, and the control
logic will switch the negative reference voltage (- V REF ) to the input of A1.
At this point the capacitor is charged to a negative voltage (- V) proportional
to the input analog voltage.
Now the capacitor discharges linearly because of the constant current from the V REF.
This linear discharge produces a positive-going ramp on the A1 output, starting
at V and having a constant slope that is independent of the charge voltage.
As the capacitor discharges the counter advances from its RESET state.
The time it takes the capacitor to discharge to zero depends on the initial voltage
- V (proportional to Vin) because the discharge rate (slope) is constant.
When the integrator (A1) output voltage reaches zero, the comparator (A 2 )
switches to the LOW state and disables the clock to the counter.
The binary count is latched, thus completing one conversion cycle.
The binary count is proportional to Vin because the time it takes the capacitor to
discharge depends only on - V, and the counter records this interval of time.

OR
20.Write technical notes on
1.Building Blocks of PLL
2.VCO
3.Monostable multivibrator using 555

1.Building Blocks of PLL

Phase detector
The phase detector compares the i/p frequency and VCO frequency and generates a
dc voltage that is proportional to thephase difference between the two frequencies.
Low pass filter
The function of low pass filter is to remove the high frequency components in the
o/p of the phase detector and to remove high frequency noise.
Voltage controlled oscillator
VCO generates an o/p frequency that is proportional to its i/p voltage.

2. Voltage Controlled Oscillator

A timing capacitor C1 is linearly charged or discharged by a constant current

source/sink.
The voltage at pin 6 is held at the same voltage as pin 5.

Thus voltage at pin 5 is increased,the voltage at pin 6 also increases,resulting in

less voltage across R1 and there by decreasing the charging current.
The voltage across C1 is applied to the non inverting i/p terminal of Schmitt trigger
via buffer amplifier.
The o/p voltage of the Schmitt trigger is designed to Vcc and 0.5 Vcc.
When the voltage on the capacitor C1 exceeds 0.5 Vcc during charging the o/p of
the Schmitt trigger goes low.The capacitor now discharges and when it is at
0.25Vcc,the o/p of Schmitt trigger goes high.
Since the source and sink currents are equal,capacitor charges and discharges for
the same amount of time.
This gives a triangular voltage waveform across C1 which is also available at pin 4.
The o/p frequency of the VCO can be calculated as follows
The total voltage on the capacitor changes from 0.25 Vcc to 0.5 Vcc,thus
V=0.25 Vcc
The capacitor charges with a constant current source
So, V/ t = i/C1
0.25Vcc/ t = i/C1
t= 0.25Vcc C1/i
The time period T of the triangular waveform is 2t
Frequency of oscillation Fo= 1/2t
=i/0.5Vcc C1
i = Vcc-Vc/R1
Fo= 2(Vcc-Vc)/ C1 R1Vcc
Where Vc is the voltage at pin 5

3. Monostable multivibrator using 555

Working
Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the
transistor is on and capacitor- C is shorted to ground.
When a negative pulse is applied to pin 2, the trigger input falls below +1/3 VCC,
the output of comparator goes high which resets the flip-flop and consequently the
transistor turns off and the output at pin 3 goes high.

This is the transition of the output from stable to quasi-stable state. As the
discharge transistor is cutoff, the capacitor C begins charging toward +VCC through
resistance RA with a time constant equal to RAC.
When the increasing capacitor voltage becomes slightly greater than +2/3 VCC, the
output of comparator 1 goes high, which sets the flip-flop.
The transistor goes to saturation, thereby discharging the capacitor C and the output
of the timer goes low
Thus the output returns back to stable state from quasi-stable state.
The output of the Monostable Multivibrator remains low until a trigger pulse is
again applied. Then the cycle repeats.
tp = 1.0986 RAC
vc = VCC (1- e-t/RaC)
Substituting vc = 2/3 VCC in above equation we get the time taken by the capacitor to charge
from 0 to +2/3VCC.
So +2/3VCC. = VCC. (1 e-t/RAC) or
t RAC loge 3 = 1.0986 RAC
So pulse width, tP = 1.0986 RAC
= 1.1 RAC