Professional Documents
Culture Documents
Introduction
Hardware
Description
Language
2
DSDA - 2016
V
H
D
L
C. Sisterna
FPGA
Xilinx
Altera
ASIC
Lattice
Actel
3
DSDA - 2016
C. Sisterna
Easy to debug
Parameterized designs
Re-uso
IP Cores (free) available
4
DSDA - 2016
C. Sisterna
5
DSDA - 2016
C. Sisterna
VHDL
VHDL
Synthesizable
Used to implement
the design into
hardware (for
instance in FPGA)
6
DSDA - 2016
C. Sisterna
y
sel
0
1
if(sel=1) then
z <= y;
else
z <= x;
end if;
C. Sisterna
clk
if(clk
)then
q <= d;
else
q <= q;
end if;
if(clk
)then
q <= d;
end if;
if(rising_edge(clk))then
q <= d;
end if;
8
DSDA - 2016
C. Sisterna
entity
I/O
d
clk
q
architecture
Functionality
9
DSDA - 2016
C. Sisterna
d
clk
architecture test of ff is
begin
process(clk)
begin
if(rising_edge(clk)) then
q <= d;
end if;
end test;
10
DSDA - 2016
C. Sisterna
Test Bench
Stimulus
Signals
Tested
Signals
11
DSDA - 2016
C. Sisterna
12
DSDA - 2016
C. Sisterna
VHDL - Synthesis
VHDL
Code
Design
Constraints
NET CLOCK PERIOD = 50 ns;
Design
Attributes
Synthesis
Tool
FPGA list of
Components and
Connections
FPGA Library
of Components
13
Cyclone
Spartan
DSDA - 2016
C. Sisterna
14
DSDA - 2016
C. Sisterna
15
DSDA - 2016
C. Sisterna
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=836&PartNo=1
16
DSDA - 2016
C. Sisterna
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=502
17
DSDA - 2016
C. Sisterna
http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941
18
DSDA - 2016
C. Sisterna
http://www.terasic.com.tw/cgi-bin/page/archive.pl?CategoryNo=139&No=593
19
DSDA - 2016
C. Sisterna
FPGA Xilinx V5
20
DSDA - 2016
C. Sisterna