IPC/JEDEC-9703

Mechanical Shock Test Guidelines

for Solder Joint Reliability
March 2009
A standard developed by IPC/JEDEC

Association Connecting Electronics Industries

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IPC/JEDEC-9703
ASSOCIATION CONNECTING
ELECTRONICS INDUSTRIES

Mechanical Shock Test

Guidelines for Solder
Joint Reliability

Developed by the JEDEC Reliability Test Methods for Packaged Devices

Committee (JC-14.1) and the SMT Attachment Reliability Test Methods
Task Group (6-10d) of the Product Reliability Committee (6-10) of IPC

Users of this publication are encouraged to participate in the

development of future revisions.
Contact:
IPC
3000 Lakeside Drive, Suite 309S
Bannockburn, Illinois
60015-1219
Tel 847 615.7100
Fax 847 615.7105

This Page Intentionally Left Blank

March 2009

IPC/JEDEC-9703

Table of Contents
1

SCOPE ...................................................................... 1

APPLICABLE DOCUMENTS .................................... 1

2.1
2.2

IPC ......................................................................... 1
American Society for Testing and Materials ....... 1

6.6

Failure Analysis .................................................. 12

6.7

Reporting Recommendations .............................. 12

COMPONENT MECHANICAL SHOCK

ASSESSMENT ........................................................ 12

7.1
3
4

USE CONDITIONS OVERVIEW ............................... 2

4.1
4.2

Scope and Application of UCs ............................. 2

Capturing UC Data ............................................... 2

4.3
4.3.1
4.3.2

Methods for Developing UCs ..............................

Approach 1 UC Derivation Approach ..............
Approach 2 Leveraging Existing Data to
Usage Model .........................................................
Torture Tests ..........................................................

4.3.3
5

2
2
3
3

7.6
7.7

Failure Analysis .................................................. 15

Reporting Recommendations .............................. 15

7.2
7.3

12
12
13
13
13
13
14

SYSTEM TESTS ....................................................... 4

5.1
5.1.1
5.1.2
5.1.3

Shock Test Equipment ..........................................

Drop Testers ..........................................................
Shock Machines ....................................................
Inclined Impact .....................................................

5.1.4
5.2
5.2.1

Fixturing ................................................................ 6
Correlation Criteria ............................................... 6
Unpackaged System Input Correlated to
Packaged System Environment ............................ 6

5.2.2

Unpackaged System Input Correlated to

End User Use-Conditions ..................................... 7

5.3
5.3.1
5.4
5.4.1
5.4.2
5.5
5.6
5.6.1
5.6.2

Test Recommendations ......................................... 7

Testing Sample Recommendations ....................... 7
Test Flow ............................................................... 8
Packaged System Testing ..................................... 8
Unpackaged System Testing ................................. 9
Post Test Analysis ................................................. 9
Testing Output and Report Recommendations .. 10
General Considerations ....................................... 10
Electrical Testing ................................................. 10

5.6.3
5.6.4

Failure Analysis Considerations ......................... 10

Reporting Recommendations for Test
Development ....................................................... 10

7.4
7.5
7.5.1
7.5.2

Component Assessment General

Considerations .....................................................
Component Board Testing Recommendations ...
Correlation Criteria and Validity of
Test Setup ............................................................
Equipment Recommendations ............................
Testing Flows ......................................................
Characterization Testing .....................................
Qualification Testing ...........................................

TERMS AND DEFINITIONS ...................................... 1

4
4
5
5

SYSTEM BOARD LEVEL TESTING ...................... 11

6.1
6.2
6.3

Board Testing Background ................................. 11

System Board Testing Recommendations .......... 11
Correlation Criteria and Validity of
Test Setup ............................................................ 11

6.4

Equipment Recommendations ............................ 11

6.5

Test Flows ........................................................... 11

8.1.1
8.1.2

METRICS FOR MATCHING TEST ......................... 15

Acceleration Based Method ................................ 15

Board Strain Based Method ............................... 16

Annex A

Sample Data Reporting Format ............... 20

Annex B

Metrologies

Annex C

Shock Failure Analysis of

Electronic Components ......................... 25

Annex D

Suggestions for Selecting

Sample Size ............................................. 27

Annex E

Suggestions for Finite Element

Analysis in Mechanical Shock .............. 29

.............................................. 22

Figures
Figure 4-1

Typical UCs where Mechanical Shock

May be Expected for a Few Representative
Products .............................................................. 3

Figure 5-1

Example of the Time History Response

Showing the Input from the Shock Table
(trapezoidal shape) and the Response at
Two Locations on the PCB ................................. 7

Figure 5-2

Example of Shock Response Spectra (left)

Derived from the Time History ............................ 8

Figure 6-1

Illustration of a Board Level Test on a

Hard Plate ......................................................... 11

Figure 6-2

Illustration of a Board Level Test on a Rigid

Fixture ............................................................... 12

Figure 6-3

Illustration of a Boundary Condition Simulator

(BCS) ................................................................. 12

Figure 7-1

Flow Chart for Characterization Test ................ 14

Figure 8-1

Basic Model for Board Level Testing

(Assumes Worst Case Amplification
and no other Interaction with Chassis) ............. 16

IPC/JEDEC-9703

March 2009

Figure 8-2

Example of Correlation of a Board Test

to Three Test Systems ...................................... 17

Figure E-6 Comparison of Displacement-Time History

for Experimental Data and FEA Result ............. 37

Figure 8-3

Definition of Board Strain States Plot ............... 17

Figure 8-4

Comparing Board Bend Modes of Board

in System Chassis and Mounted to a
Fixed Plate ........................................................ 18

Figure E-7 Comparison of Board Strain versus Time

History for Experimental Data and FEA
Result ................................................................ 37

Figure 8-5

Settling Time for a Typical System Level

Test with High Damping and Rapid Decay
in the Strain ....................................................... 18

Tables

Typical Time History for a Component

Board Test with Minimal Damping .................... 18

Table 4-1

Example of a UC for a Mobile Phone,

(Illustrative Only) .................................................. 3

Figure B-1 Wire (a) Strain Gage Location with Respect

to Solder Ball at Package Corner. (b)
Orientation of Strain Gages for every
Package Corner ................................................ 22

Table 7-1

Example of Critical Strain Determination

Results. Value indicates number of drops
at each level. (Shadows indicates electrical
failure.) ................................................................ 14

Figure B-2 Wire Routing should be done So as Not

to Affect Results ................................................ 23

Table 8-1

Recommended Matching Criteria for

Selected Use and Test Conditions ..................... 16

Table A-1

Test Report Recommendations (Equipment

and Materials) ..................................................... 20

Table A-2

Test Report Recommendations

(Board Assembly) ............................................... 20

Table A-3

Test Report Recommendations

(Test Results) ..................................................... 21

Table B-1

Recommended Scan Frequencies

for Various Systems ........................................... 23

Figure 8-6

Figure B-3 Wire Artwork Showing Strain Gage Feature

and Internal Board Routing ............................... 23
Figure B-4 Fast Fourier Transform of an Example
System .............................................................. 23
Figure C-1 BGA Solder Joint Failure Modes ...................... 26
Figure C-2 Area Array Cross-Section Diagram ................... 26
Figure E-1 Coarse Mesh of Plate ....................................... 29
Figure E-2 Fine Mesh of Plate ............................................ 29
Figure E-3 Rack Mounted Test Board ................................ 30

Table D-1 Sample Size Estimate for a Single Failure

Mechanism ......................................................... 28
Table E-1

Full, Symmetric, and Asymmetric

Meshes of Plate ................................................. 30

Table E-2

Comparing Implicit and Explicit

Dynamic Solutions .............................................. 33

Figure E-4 Simplified Satellite Antenna Model ................... 31

Figure E-5 Results for Simplified Satellite Antenna
Model ................................................................. 32

ii

March 2009

IPC/JEDEC-9703

Mechanical Shock Test Guidelines

for Solder Joint Reliability
FOREWORD

This publication has been drafted as part of a joint working

group between the IPC 6-10d task group and the JEDEC
JC14.1 subcommittee. It is intended to be used as a general
guideline for mechanical drop and shock testing. It is also
encouraged that future application specific mechanical
shock standards and specifications for IPC and JEDEC
should apply the methods proposed herein.
INTRODUCTION

With the growth of electronics and the increased accessibility and portability, drop shock and other mechanical
impacts are increasingly a concern. This document
attempts to improve upon past mechanical shock test methods, and tie test conditions back to the use-conditions. A
method is proposed such that regardless of what level (system, board assembly, simplified single component board
testing, etc.) testing is conducted, there should be a correlation back to the use-condition. In order to fulfill this goal,
additional metrologies are introduced to aid in these correlations.
Following the requisite introductory sections, the concept
of use-conditions is introduced and suggestions are made
on how use-condition data may be acquired and applied.
Next, the testing methods for fully assembled systems are
introduced. Options for test conditions are discussed and
the data that should be collected is outlined.
Testing of subassemblies and components mimics actual
use configurations less than testing of fully assembled systems; however, the next two document sections outline
considerations to ensure that testing done at these levels
remains relevant to the intended use-condition.
Specific metrics to aid in correlations are outlined in Section 8. The informative annexes that close the document
discuss the common considerations of all mechanical shock
testing methods. These include a sample reporting format
for test data, use and application of strain gages, accelerometers, and high speed photography. A section on failure
analysis is given. Lastly, a review of finite element methods that may be applied to mechanical shock analysis is
given to aid in more in-depth study of shock problems.
1 SCOPE

This document establishes mechanical shock test guidelines for assessing solder joint reliability of Printed Circuit

Board (PCB) assemblies from system to component level.

The three main categories discussed within this document
follow:
1. Methods to define mechanical shock use-conditions.
2. Methods to define system level, system board level and
component test board level testing that correlate to the
use-conditions.
3. Guidance on the use of experimental metrologies for
mechanical shock tests.
2 APPLICABLE DOCUMENTS
2.1 IPC1

Qualification and Performance Specification for

Rigid Printed Boards

IPC-6012

Requirements for Electrical Testing of Unpopulated Printed Boards

IPC-9252

2.2 American Society for Testing and Materials2

ASTM D3332 Standard Test Methods for MechanicalShock Fragility of Products, Using Shock Machines
3 TERMS AND DEFINITIONS

For the purposes of this document, the following terms and

definitions apply:
Accelerometer An electronic device that converts
mechanical deformation of an internal structure caused by
acceleration into electrical signals that can be sensed by a
data acquisition system.
Component Board Level Test A test conducted on a simplified test board which contains only one type of component, although multiple samples of the same component
may be present. This board need not be similar to the final
system board.
ODM

Original design manufacturer.

OEM

Original equipment manufacturer.

Printed wiring board, also known as printed circuit

board (PCB).

PWB

SRS A shock response spectrum is an analysis of the

acceleration output signal into the frequency domain.

1. www.ipc.org
2. www.astm.org

IPC/JEDEC-9703

March 2009

Strain Gage A sensor of mechanical deformation consisting of one or more small serpentine structures whose electrical resistance is changed by deformation of the material
to which the gage has been attached.

change over time, and/or UCs may become void and/or

new UCs may become appropriate to capture. Periodic
review is suggested.

Test of a system board with all

major components being represented either by the actual
components or equivalent test devices.

4.2 Capturing UC Data Different parameters should be

captured in order to completely define the use-condition. A
mobile phone end-user drop UC example is given in Table
4-1. Number of drops, drop height, drop surface and drop
orientation together completely characterize the end-user
drop behavior.

System Board Level Test

Test of a fully assembled system

including chassis or a major subassembly that is received
by the end customer as a unit, (e.g., server modules). This
may also include the packaging used during shipment of
the system.

System Level Test

Use Conditions, a description of the expected events

and frequency of occurrence during the life of the product.

4.3 Methods for Developing UCs Various methods may

be used to define product or product segment UCs, as listed
below. Thinking about the best approach to define UCs is
often a useful starting point.

4 USE CONDITIONS OVERVIEW

If the UC has a strong impact on certification requirements, it may be appropriate to collect actual data.

Historically, shock testing has been based on a few standardized acceleration conditions. This approach, while
simple, is not optimal for the following reasons:

If a new product segment is similar to an existing segment, it may be appropriate to scale existing UCs to the
new product segment.

One set of reliability requirements may not apply to all

market segments.

If time or budget is limited, collaboration of data sharing

with existing UCs may be appropriate.

Testing to standards based tests, or military-based specifications may be unrealistic since it may not be cost effective for products with more mild requirements.

Existing industry data may be leveraged based either on

expected differences to the target application or may often
be based on customer/user expectations.

Accelerated tests with fixed pass/fail requirements offer

little insight into the likely lifetime of a product in the
actual end-user environment.

Finally, if existing data offers insight into specific stages of

the UC (e.g., the human handling portion of a shipping
shock study), judgment can often be used to extrapolate
those UCs to a new application.

UC

This proposal employs market segment based useconditions (UC). Market segment based use-condition testing offers several advantages:
A better understanding of robustness and reliability for a
specific product segment or for products and components
in a specific application.
Avoidance of over-engineering to meet a standardized
acceleration condition, which could add cost.
Scalability across multiple product form factors; meaning,
portions of a usage behavior from one product type might
be applicable to usage behaviors of a new product type.

4.3.1 Approach 1 UC Derivation Approach In this

approach direct data collection is used to derive the UCs.
This may be accomplished using user surveys, field observation of handling behavior, data logging tools, or other
direct means. There are some limitations that should be
considered in adopting this approach:

Behavior will vary by distribution channel.

Uncontrollable variables may be missed or may skew the
results.
Cost may be significant to obtain statistically valid data.

4.1 Scope and Application of UCs For the scope of this

document, the most valuable use-conditions are those that

have direct impact on interconnection (e.g., solder joint)
reliability.
Applicable UCs can typically be categorized into the major
stages of a products life cycle. Those stages include:
assembly, shipping, storage, end-user environment and possibly returns and repairs due to issues in the field. Figure
4-1 gives examples of where these events may occur for
several distinct system types. It should be expected that the
types of events seen during the product life cycle may vary
based on the market segment. Furthermore, UCs may
2

For the example of shipping

shock/drop, data collection is a viable and useful study to
undertake, while being aware of its limitations mentioned
above. Hardware is readily available in the industry to
enable data logging of shipping shock/drop conditions.
Some variations and modulators of results are to be
expected, including:
Example of Approach 1:

Development level of country.

Road conditions, use of automated handling.
Shipping method.
Expedited air delivery, truck, train, etc.

March 2009

IPC/JEDEC-9703

Mechanical Drop / Shock Use Conditions Flow

Assembly

Shipping

Storage

OEM/ODM
Assembly

Shipping Shock

Handling

Drop / Shock

Shipping Shock

Handling

Drop / Shock

Shipping Shock

Handling

Drop / Shock

End-user environment,
including field returns

Desktop

User Drop
& Shock

Mobile PC

Handheld

User Drop
& Shock
IPC-9703-4-1

Figure 4-1

Typical UCs where Mechanical Shock May be Expected for a Few Representative Products
Table 4-1 Example of a UC for
a Mobile Phone, (Illustrative Only)

UC

Value

Justification

Number of Drops

Three drops

Based on expected use

Drop height

1.50 meters

Based on human
factors information

Drop surface

Concrete

Worst-case assumption

Face-down

Worst-case assumption

Drop orientation

onto the docking station), product design (e.g., form factors) and the environment (concrete floor vs. laminate desk
surface).
An understanding of specific usage scenarios will lead to
identifying critical use-condition events of interest. Existing literature data (from publications) can often be leveraged to define the UCs that are relevant to a given market
segment.

Using data loggers attached to accelerometers inside the

shipping box, one can determine the height and number of
drops experienced by a single package during shipment. By
repeating this shipping study with multiple routes and conditions, it is possible to develop a model of the shipping
use-conditions.

Example of Approach 2: Portable music player or barcode

scanner manufacturers may have published certain drop
heights, e.g., 1 meter, corresponding to waist height (relevant to their expected usage model). This data can be used
to define a drop height of a mobile phone based on human
figure proportions (e.g., ear height is 1 .5X waist height).

4.3.2 Approach 2 Leveraging Existing Data to Usage

Model A usage model describes the interactions between

4.3.3 Torture Tests

a user and a product. It is based on the user needs (e.g., a

FedEx package handler vs. a corporate employee), user
behaviors (e.g., drop on the floor, hard dock of a laptop

Torture tests such as a 762.0 mm

[30.0 in] drop or coffee spill test for Mobile PCs, are
sometimes used to evaluate performance against perceived
or observed severe behavior and usage models. In most
instances, torture tests may not be derived from common
3

IPC/JEDEC-9703

UC model or behavior. For torture tests, or other extreme

usage models, care must be taken to balance reasonable
expectations of performance against device survivability
and acceptable costs necessary to enable increased robustness and reliability.
5 SYSTEM TESTS

The purpose of system level shock testing can be to either

demonstrate the ability of the product to survive relatively
infrequent, nonrepetitive shocks encountered during the
intended UCs or to determine the products fragility level so
that appropriate packaging can be designed. The goal of
system testing is to replicate the UC environment utilizing
laboratory equipment. These tests should be correlated to
the UC environment.

March 2009

supplied with a motor hoist to automatically raise and

lower the drop arm with package in place, a micro switch
to preset the drop height for repeatable drops, a drop height
indicator, and a remote hand switch to actuate the system.
The tester should incorporate a small vertical drop prior to
drop arm swing to ensure that the package is not subjected
to rotation. Packages may be released from any angle but
special procedures may be required to assure landing in the
same position. The advantages of a swing arm tester is that
it is fast and easy to use, provides for easy test article set
up, and is relatively inexpensive. They are easy to install
and require no facility modification. Their disadvantage is
that test articles are limited in size and weight and there is
a minimum drop height restriction.

Post test analysis that provides relevant and meaningful

information.

Drop Platform Testers: Drop platform testers are typically

used when the package is of moderate size and weight
accommodating large products and packages weighing up
to 227 Kg [500 Lbs]. They are capable of performing drops
as low as 2.5 cm [1.0 in] and as high as 1.8 m [6 ft]. They
are designed to ensure the flattest impacts possible but, in
addition, they allow drop testing to be performed on the
packages edges and corners for complete performance
evaluation. The drop platform is raised and lowered by an
electric hoist and released via an air actuator. During the
drop test stage, the drop platform is accelerated downward,
thereby allowing the package to free fall while the drop
platform descends into slots below the impact surface.
Rebound of the drop platform is prevented, usually by a
hydraulic damper at the bottom of the slots. The advantages of the drop platform testers are that they can accommodate large packages, perform over a wide range of drop
heights, and provide better guidance of edges and corners
than other types of drop testers. The disadvantages are that
they are relatively expensive and often require facility
modifications to allow for the platform to drop below the
impact surface. Because of the large size and heavy
weights, they can pose a personnel safety risk and often
require protective enclosures with safety interlocks.

Reporting recommendations that include data necessary

for follow-on testing or condition evaluation.

Large Package Quick Release:

The definition of a system may be a fully assembled system as well as sub-systems. (e.g., server modules, board
assembly handled out of system, etc.)
System tests may be performed on either packaged or
unpackaged systems. Packaged system tests are usually
performed to demonstrate that the system and packaging
can withstand shocks that may be encountered in the shipping and distribution environment. Unpackaged system
tests are performed to either ensure the system has enough
robustness to withstand handling shocks in a cost effective
shipping package or to ensure the system can survive shock
events experienced in a typical end-user environment.
The major factors to consider when defining a system
shock test are as follows:
Equipment that provides the appropriate environment.
Input profiles that are correlated to use-condition profiles.
Requirements that ensure the proper test article configuration and desired confidence level.
Procedures that ensure proper test conditions and order of
testing.

5.1 Shock Test Equipment

Package drop testers are simple

machines that allow for repeatable dropping of packages in
terms of height and orientation. Package drop testers can be
either swing arm testers, drop platform testers, or large
package quick release testers.

5.1.1 Drop Testers

The swing arm tester is typically used

when the package is small or light weight and the drop
height is relatively large. Drop heights typically range from
30 to 150 cm [12 to 60 in]. The swing arm tester is usually

Swing Arm Testers:

The quick release drop

testers are designed to drop test larger, bulkier packages
than those possible with drop platform testers. They can
perform repeatable free-fall drop tests (flat, edge and
comer) on packages of virtually any size and shape and can
accommodate packages weighing up to 1360 Kg [3,000
lbs]. Drop test height is limited only by the lifting device
used (forklift, winch, etc.). The quick release drop testers
consist of a quick release mechanism, a lifting ring, and a
foot switch. Straps are wrapped around the test item from
a sling that is attached to the lifting ring, which is placed
in the jaws of the quick release mechanism. The quick
release mechanism and package are then raised to a predetermined height by a forklift, winch, or other lifting device.

March 2009

The foot switch activates a solenoid in the mechanism,

causing the latch jaws to open and the test package to be
released.
The advantages of the quick release drop tester is that it is
relatively inexpensive compared to the other methods, provided the lab already has the lifting device. If the lab does
not have a heavy duty lifting device then the cost increases
considerably. The major disadvantage of this method is that
it is difficult to maintain orientation of the object during the
drop.
Shock tests are used to accurately measure the fragility of products and to evaluate
protective packaging by applying a controlled acceleration
profile. This test data is key information necessary to
ensure that the product is capable of withstanding its real
world environment. Shock machines are used to accurately and repeatedly produce shock profiles that are correlated to the environment that a system experiences in its
shipping and in-use environments. Shock testing with controlled shock inputs is essential to discovering and understanding the risk area of a product.

5.1.2 Shock Machines

Shock Test Systems Large Format Shock Testers: Large

format shock test systems have the ability to test items

weighing up to 1,134 kg [2,500 lbs] with a footprint
dimension up to 95 x 115 cm [37.4 x 45.3 in]. They can
perform a wide variety of shock tests to a maximum acceleration of 600 G. The system consists of a shock table that
is guided by two solid guide rods. The two guide rods are
rigidly attached to a massive, isolated base that helps to
attenuate any shock energy that would otherwise be transmitted to the surrounding building through the laboratory
floor. Also mounted to the base are two damage boundary
programmers, which allow the operator to generate both
half sine and trapezoidal shock pulse waveforms.
At the start of a shock test the shock table is raised until it
reaches the programmed drop height. Upon initiation of the
drop sequence, the lifting mechanism is retracted clear of
the shock table and the brake system releases, allowing the
shock table to free fall. The shock table impacts the damage boundary programmer(s), creating the desired shock
pulse waveform. As the shock table rebounds the brakes
reengage to prevent any secondary impacts. The parameters that can be controlled in the operation of the shock
system are drop height and programmer stiffness. The two
types of damage boundary programmers commonly used
are elastomeric impact cylinders and gas actuated plunger
assemblies. The elastomeric impact cylinders are used to
generate half sine profile shock pulses. The amplitude and
duration of the half sine pulse can be controlled by the drop
height of the table free fall and the geometry and durometer hardness of the elastomeric cylinders. The gas actuated
plunger assemblies are used to generate square wave or
trapezoidal wave shock pulses. The drop height of the table

IPC/JEDEC-9703

free fall and the pressure in the plunger impact cylinder(s)

control the amplitude and duration of the square wave
pulse. The disadvantages of the large format shock test
system are the cost and the limitations of acceleration profiles. The acceleration level is limited by the height of drop
and free fall acceleration. Higher acceleration levels can be
reached by the use of special adapter kits or by the use of
High G shock machines.
The high G shock
testers are similar to large format shock testers but are outfitted with a bungee cord acceleration system which more
than doubles the velocity change capability. When using
them in free fall mode-without the acceleration system-the
maximum payload can be as high as 1,360 kg [3,000 lbs].
While in the accelerated mode, the maximum payload is
limited to 113 kg [250 lbs]. They have a smaller test platform and can only accommodate test items with a footprint
dimension up to 46 cm [18 in] square. A maximum velocity change of 25 m/sec [82 ft. /sec] and a peak acceleration
of 7,500 G can be obtained with specimens weighing up to
45 kg [100 lbs].

High Acceleration (G) Shock Testers:

High G Shock Amplifiers: Another method of producing

high G shocks is the use of a shock amplifier. Shock amplifiers produce high acceleration shocks on a spring loaded
table. One such system, the mousetrap amplifier, consists
of a base plate mounted on the top surface of the shock
machine carriage, a specimen mounting carriage which is
supported by soft springs and a resilient decelerating pad
between the shock machine and its carriage. As the main
carriage accelerates down, impacts upon its resilient pad
and decelerates up, the specimen mounting carriage continues to travel downward (or in the opposite direction of the
main carriage) as they collide. The resultant acceleration at
impact is much greater than would be achievable if only
the main carriage impacted against a stationary base. The
mousetrap shock amplifier can be used for two primary
purposes: as an amplifier to produce increased velocities or,
because the mousetrap amplifier is supported on springs,
the springs act as a mechanical filter which serve to
reduce the ringing associated with short time duration
pulses.
Vibration Machines: Electrodynamic, hydraulic, and
pneumatic vibration machines can also be used to provide
a source of shock pulses as long as the pulse requirements
do not exceed the force and motion capabilities of the
machine. These pulses are typically half sine pulses and
can be on the order of a few milliseconds in duration and
less than 100G in amplitude. The major drawback to this
method is the pre- and post-pulse conditioning required to
generate the shock pulse.
5.1.3 Inclined Impact The purpose of the inclined
impact test is to demonstrate that the packaging and palletizing methods, wrapping and strapping, used on the

IPC/JEDEC-9703

product will protect them from damage due to side impacts.

Inclined impact simulates pallet collision with walls, truck
bulkheads, or other loads experienced during loading of a
truck, airplane, or transport of product in a storage area.
The inclined impact test apparatus consists of a wheeled
carriage, guided by steel rails, upon which the test item is
placed. The rails are inclined at 10 degrees and there is an
impact backstop at the low end, with its surface perpendicular to the carriages direction of travel. When the carriage is pulled up the rails and released, it freely rolls down
the track and the specimen impacts the backstop.
5.1.4 Fixturing Test article fixturing refers to the method

of holding the test article while subjecting it to the shock

environment. It needs to simulate the boundary conditions
of the use environment as much as possible. Care must be
taken to not suppress the failure mode or vibration mode of
interest.
The fixturing for drop testing of
packaged systems is the simplest since it only requires
holding the package prior to the drop. The fixturing should
not interfere with the motion of the package at impact, as
this will impart unwanted loads into the test article. The
standard practice for orienting the package before free fall
drop is to ensure the desired impact location is aligned with
the center of gravity of the packaged item. This is usually
easy to achieve in flat edge drops but may require careful
balancing for edge or corner drops.

Drop Test Fixturing:

The fixturing for drop testing of unpackaged systems is

considerably more difficult. The system must be constrained to impact at the desired location while preventing
any rotational motion of the test article. In addition, the
fixturing must not impede the free fall motion of the system. It must also release the test article before impact so as
to avoid any attenuation of the shock input upon impact.
The method of fixturing the
unpackaged system to the shock table should represent the
use-condition that the test is simulating. Unpackaged system tests that are used to validate robustness to survive
packaged drops should be fixtured to represent the structural support that the system would have in the packaging.
System packaging typically supports the unit only at the
corners or along the edges, and so the fixturing should only
support the system at the same locations. Blocking may be
required to hold the system off of the table so that it only
contacts at these support areas. The blocking material
should be selected to minimize the amount of damping that
is imposed between the table and the system. Typical materials are metal (usually aluminum or steel) but sometimes
wood or a plastic material is required. The advantage that
wood or plastic offers is that is can be easily machined or
molded to the profile of the test item but these materials are
much more compliant, and therefore would provide considerable damping and signal attenuation. Unpackaged system

Shock Table Fixturing:

March 2009

tests that are used to validate the performance of the unit

in end user drop would be fixtured directly to the table so
that the entire surface is exposed to the shock input.
5.2 Correlation Criteria System test input profiles are a
critical component of test procedures. These test profiles
must accurately represent or be correlated to the usecondition that is being represented. These profiles are
straightforward in the case of packaged system test conditions that are representative of transportation and distribution handling. The test profiles are specified as a number of
drops in different orientations from specified heights that
are representative of measured or observed events for packages of similar size and weight and can be performed using
drop test equipment.

The test profiles are more complex for unpackaged system

testing. The unpackaged system test profile must be correlated to the environment that is being represented. In the
case of the test that is conducted in order to ensure the system is sufficiently robust to withstand shocks in a cost
effective shipping package, the test profile must be correlated to the response that the system experiences in its
packaging during the transportation and distribution environment. If the purpose of the test is to ensure the system
can survive shock events experienced in a typical end user
environment, the test profile must be correlated to the
response that the system experiences due to drops, kicks,
and bumps associated with the end user use-conditions.
Several parameters are of interest when matching test conditions to use-conditions. Most real world shock events,
i.e., use-conditions, are quantifiable with acceleration profiles. Drop events can be characterized by system sizes,
drop heights, and impact surface. These events can be
quantified by the acceleration profile of the system and its
characteristic parameters, e.g., amplitude, pulse shape,
duration, frequency content, etc.
5.2.1 Unpackaged System Input Correlated to Packaged
System Environment The acceleration profile experi-

enced by a package in a drop environment can typically be

represented by a half sine pulse. However, the acceleration
profile experienced by the system inside the packaging is
modified by the crushing of the packing material intended
to protect the product. This profile is commonly represented by a trapezoidal or square wave. The trapezoidal
pulse is characterized by the velocity change and the faired
acceleration. Faired acceleration is defined as the average
of the oscillation amplitudes between the first time that the
response goes negative and the last time that the response
goes positive. The velocity change is the area under the
time history curve and is typically the faired acceleration
level times the pulse width. The trapezoidal input pulse can
be correlated to measured responses pulses either by using
time domain comparisons or frequency domain shock
response spectrums.

March 2009

IPC/JEDEC-9703

The trapezoidal input pulse

should envelope the majority of the pulse peaks (80% or
more) measured at several locations in the system near the
contact points with the packaging material. This technique
accounts for the acceleration amplitude and velocity
change but does not consider the frequency content of the
pulse. See Figure 5-1.

Time Domain Correlation:

Aceleration (in gs)

100
80
60
40

pulses. This technique accounts for the acceleration amplitude and velocity change but does not consider the frequency content of the pulse.
The SRS of the
half sine input pulse should envelope the SRS of the
responses measured at several locations in the system in
the direction of the input (drop or bump direction). The
spectra used for the measured responses should be the
composite spectra for both positive and negative directions.
The analyses should be performed for a Q = 10 at a
sequence of natural frequencies at intervals of 16 octave or
smaller to span at least 5 to 500 Hz. This method accounts
for the amplitude, frequency, and energy in the measured
input that is likely to cause damage in the system.
Frequency Domain Correlation (SRS):

20
5.3 Test Recommendations

0
0

10

12

14

16

-20
Time (milli-seconds)

IPC-9703-5-1

Figure 5-1 Example of the Time History Response

Showing the Input from the Shock Table (trapezoidal
shape) and the Response at Two Locations on the PCB
Frequency Domain Correlation: The shock response spectrum (SRS) of the trapezoidal input pulse should envelope
the SRS of the responses measured at several locations in
the system near the contact points with the packaging
material. The spectra used for the measured responses
should be the composite spectra for both positive and negative directions. The analyses should be performed for a Q
= 10 at a sequence of natural frequencies at intervals of 1/6
octave or smaller to span at least 5 to 500 Hz. This method
accounts for the amplitude, frequency, and energy in the
measured input that is likely to cause damage in the system. This is illustrated by the examples shown in Figure
5-2.
5.2.2 Unpackaged System Input Correlated to End User
Use-Conditions The acceleration profile experienced by

an unprotected system in a drop, kick or bump environment

can typically be represented by a half sine pulse. The half
sine pulse is characterized by the pulse amplitude and the
velocity change. The velocity change is the area under the
time history curve and is calculated as twice the amplitude
times the period divided by . The half sine input pulse can
also be correlated to measured response pulses either by
using time domain comparisons or frequency domain
shock response spectrums. Methods similar to those
described in the previous section can be used.
Time Domain Correlation: The half sine input pulse
should envelope the majority of the pulse peaks measured
at several locations in the system in the direction of the
input (drop or bump direction). The duration of the pulse
should envelope the maximum duration of the response

5.3.1 Testing Sample Recommendations

Test Sample Condition/Configuration: Samples need to
represent final system configuration in terms of mass, stiffness, geometry and peripheral hardware. The peripheral
hardware that is normally supplied in the system must be
included in system tests because the mass, stiffness, and
structural characteristics of this hardware can have a significant impact on the dynamic performance of the system
in shock testing. As an example, any add-in cards that plug
into card guides on the processor mother board and also
interface to the chassis side wall should be included in the
system test, as they will change the dynamic response of
the mother board to the shock environment and the resulting stresses on the component solder ball attachments.

Test samples should be randomly selected from production

materials that make up the test system. Selecting all materials from the same production lot will not take into
account production variability that may have a significant
effect on the dynamic performance of any structural hardware in the system. For example, differences in weld quality in chassis manufacturing will alter the dynamic
response of the motherboard mounted in the chassis. Not
all of the hardware used in system testing need be of operational quality. Mechanical surrogate components can be
used in place of those not being electrically tested, but the
configuration, layout, and attachment methods must be
consistent with their operational counterparts. As an
example, daisy chain connectivity of CPU sockets may be
required for in-situ electrical monitoring of solder integrity
during shock testing. However, the geometry, mass, and
stiffness of the interposer used in the CPU socket must be
identical to the processor that it is replacing.
Some systems may be available in multiple configurations
and the cost required to test all configurations may be prohibitive. In this case it is acceptable to test a smaller number of systems deemed to be worst case configurations. The
7

IPC/JEDEC-9703

March 2009

ps modules_8ms In System Time History

50

ps modules_8ms In System Shock Spectra

40

120
30
Aceleration (in gs)

100
20

80
60

10
40
0

20
0
10

100

-10

0 0.005 0.01 0.015 0.02 0.025 0.03 0.035 0.04 0.045 0.05 0.055

SDOF Frequency (hz)

gilbertplngr_BottomDown_1.csv
gilbertplngr_FrontDown_1.csv
gilbertplngr_LeftDown_1.csv
gilbertplngr_RearDown_1.csv
gilbertplngr_RightDown_2.csv
gilbertplngr_TopDown_1.csv
mccar_bladrun_BottomDown25G1.csv
mccar_bladrun_Front25G1.csv
mccar_bladrun_Leftside25G1.csv
mccar_bladrun_Topdown25G1.csv
spec25g
spec40g
spec50g
Figure 5-2

Example of Shock Response Spectra (left) Derived from the Time History

designation of worst case configuration is an engineering

call that must be addressed on a case by case basis and will
depend on the purpose of the test and the anticipated failure modes.
All test articles used in system testing, including peripherals, should be labeled for ease of identification and reporting. This is especially important for investigations into
causes of failures.
Not all defects are
intrinsic to the product, so multiple units should be tested.
The number of units included in the test series, the sample
size, should balance the cost of the test articles and the
confidence level with which one desires to know the true
failure rate of the product. The preferred sample size for
x% failure rate at y% confidence level can be computed
using the statistical approach included in Annex D.
Sample Size Recommendations:

5.4 Test Flow The recommended test flow for system

testing will vary depending on the type of testing being

performed. Packaged system tests, performed to demonstrate the system and packaging can withstand shocks in
shipping and distribution, are performed in representative
8

IPC-9703-5-2

packaging configurations. Unpackaged system tests are

performed to determine the fragility level of the product, to
ensure the system has enough robustness to withstand handling shocks in a cost effective shipping package, or to
ensure the system can survive shock events experienced in
a typical end-user environment.
Shock tests for these
systems are performed by dropping the fully packaged system from a prescribed height that is based on the weight
and configuration of the system. Large systems that are
mounted on pallets for shipping are normally handled using
fork lifts or pallet handling trucks. These packages are
rarely dropped on any surface other than the palletized surface.

5.4.1 Packaged System Testing

Unpalletized systems are manually handled and may be

dropped on any surface. The test flow for packaged system
testing is therefore dependent on whether the system is
palletized or unpalletized for shipment. Packaged product
will normally not be dropped more than once from the
required test height, so it is usually acceptable to change
package components, cushioning material, cardboard, or
test sample during the test.

March 2009
Palletized Packages: The test flow for palletized systems
is recommended to drop the systems on the palletized surface twice from the full height for the particular package
weight and then dropping them an additional number of
times (usually ten) from half that height. Systems weighing
less than 45kgs [100 lbs] are usually dropped from a height
of 30.5 cm [12.0 in]. Larger systems are dropped from a
height of 23.0 cm [9.0 in]. The flat surface drops are then
followed by a number of rotational edge drops (usually
four) on each of the four bottom edges. This is performed
with one edge resting on an elevated surface and the opposite end released from the normal drop height for that size
of system.
Unpalletized Packages: The test flow for unpalletized sys-

tems is recommended to drop the system from a height that

is determined by the package weight. The required height
is based on the defined use-condition for typical handling
of systems of that particular weight. The system is dropped
once on each of the six surfaces. This is followed by a drop
on at least two corners, one being the manufacturers joint
corner and the other one the diagonally opposing corner or
any corner that may be previously determined to be especially vulnerable. The corner drops are then followed by
drops on the three edges radiating from the manufacturers
joint corner. The manufacturers joint corner is defined as
one of the corners of the edge of the packaging where the
cardboard is glued or stapled together. Corner drops are
performed with the package balanced on the corner and the
center of gravity of the package directly over the corner.
Edge drops are performed with the package balanced on
the edge and the center of gravity directly over that edge.
Shock tests for
unpackaged tests are performed with the system supported
in a manner that simulates the chassis dynamics as experienced in the normal shipping package configuration.

5.4.2 Unpackaged System Testing

Fragility Testing: Fragility tests, or damage boundary

assessment, are performed to choose optimum-cushioning
materials for shipping containers or for product designs in
the applications such as automobile or handheld. Product
damage is cumulative due to acceleration during transportation and the velocity change due to free fall drops without adequate protection. The velocity change is represented
by the area under the acceleration time history of the shock
and can be thought of as the energy contained in the shock
pulse. The higher the velocity change, the higher the
energy content and therefore the more potential that the
shock will cause damage to the product. There is a minimum velocity change which must be achieved before damage to the product can occur. This level is called the critical velocity change and below this level no damage occurs
regardless of the input acceleration level. Exceeding the
critical velocity change does not necessarily imply that
damage will result. If the change in velocity occurs in a

IPC/JEDEC-9703

manner which administers acceptable doses of acceleration

to the product, the velocity change can be very large without causing damage. If the critical velocity and critical
acceleration are both exceeded then damage occurs.
Damage boundary is assessed by two different shock tests:
a critical velocity change test and a critical acceleration
test. The product critical velocity change is determined
using shock pulse of any wave form with duration of less
than 3 ms. The critical acceleration limit of a product is
determined using a trapezoidal shock pulse with rise and
fall time of 1.8 ms, or less. The details of these tests methods are described in ASTM D-3332.
Reliability testing is performed to
demonstrate the robustness of a product and its ability to
withstand the use-conditions it will be exposed to in its
expected lifetime. The testing flow for reliability testing
starts with adjusting the shock table settings to produce the
desired acceleration level and velocity change for the test.
This is accomplished by mounting a weight comparable to
the system weight to the shock machine table and adjusting the drop height and programmer pressure until the
desired acceleration and velocity change are achieved.
These table parameters are then used for performing the
testing for all orientations of the product under test. The
shock profile used to simulate the input that an unpackaged
system would experience when dropped in its packaging is
represented by the trapezoidal pulse. This pulse is defined
by velocity change and the faired acceleration (the average
of the oscillations between the first time that the response
goes negative and the last time the wave goes positive).
The shock profile used to simulate the input that an
unpackaged system would experience when dropped without packaging is the half sine pulse. This pulse is defined
by its amplitude and pulse width. A typical unpackaged
system test consists of shocking the test unit in each of the
six orthogonal directions two or three times in each direction. The system is inspected for mechanical damage after
each drop. A typical sample size is a minimum of three
units.

Reliability Testing:

5.5 Post Test Analysis The primary purpose of system

testing is to determine the robustness of the system during
handling operations. The first step is to inspect the system
for mechanical damage caused by the test condition. Packaged system testing analysis consists of first inspecting for
visible damage to the packaging or exterior of the test item.
The test item is then removed from the packaging and
inspected for any hidden damage. The system should then
be opened and the interior inspected for mechanical damage. All of this inspection will indicate the potential for
damage to the electrical components and potential solder
joint damage. Functional test analysis for system testing
typically consists of either operational testing of the test
item in the case of a functional system or at least electrical

IPC/JEDEC-9703

continuity testing of the critical components. Functional

testing consists of applying power to the system and monitoring for any anomaly in the normal start up procedure.
Electrical continuity testing is normally performed at the
board level.
Failure analysis should be performed on any items showing
degradation during the functional testing or continuity testing. Failure analysis is typically performed at the board
level or component level and is described in more detail in
those sections and in Annex A.
5.6 Testing Output and Report Recommendations Re-

porting of results from system level testing is critical in

developing criteria and parameters for follow on activities,
either for board level tests or package design criteria. The
method of testing as well as the test flow is important in
interpreting the results of the test as well as the applicability to these follow-on activities. Output response of system
testing that is important for specifying board test inputs
include the shock input profile, board acceleration
response, board strain response, board bend mode at critical components and frequency content.
5.6.1 General Considerations The general information
that should be included in all test reports are the configuration of the hardware used in the test, all peripheral hardware installed in the system, and the method of fixturing
and materials used in the test set up. Photographs of the
test item in both pre and post test conditions should be
included. Photographs of the test item fixtured to the test
equipment should also be included. For further information
see Annex A.

Instrumentation descriptions and parameters are required in

order to properly interpret the test results. The make, model
and, if available, the serial number of all test equipment
and instrumentation should be reported. The parameters
used in the test set up are also required for proper analysis
of the results. The transducer types and gains are important
as well as the sampling rate used to capture the data. In
addition to sampling rate the use of any frequency filtering
is required in the report. The conditions under which the
test was performed must be reported such as drop height,
impact material, programmer pressure in the case of a
shock machine, and orientation of the test article. All of
this information is important in interpreting the results of
the test or in the ability to replicate the test if the need
arises.
The results of any electrical
testing performed on the test article should be reported. In
the event that in-situ monitoring of the solder ball connections was performed during the test, the results should
include the location of resistance paths (daisy chains)
monitored, the result of that monitoring, i.e., how many
5.6.2 Electrical Testing

10

March 2009

events were recorded, the time from start of testing in

which any events were detected, and the length of events
detected (how many counts). For further information see
Annex A.
The results of shock testing performed with the test article
in its operational mode should be reported also. Any abnormalities in performance or start up performance should be
reported in order to aid in failure mode analysis and
follow-on failure analysis investigation.
5.6.3 Failure Analysis Considerations Failure analysis
at the system level mainly involves inspection for mechanical damage that may be an indicator of damage to the
electronics or interconnects. The methods used in failure
analysis at the board or component level are included in
Annex C.
5.6.4 Reporting Recommendations for Test Development The results from system testing that are necessary

for test development at follow-on levels are acceleration

responses of critical components and hardware attachment
points as well as strain measurements made on the printed
circuit boards. Since strain measurements are taken on the
circuit boards, the analysis and reporting of strain
responses are identical to the methods used in board testing. This information is included in Annex A. Acceleration
responses of the critical components or hardware attachment points are necessary for development of follow-on
testing at the board and component level, or to supply the
packaging engineer information on the level of protection
that should be designed into the packaging. The aspects of
acceleration measurements that should be included in the
report are the magnitude versus time response and the
amplitude versus frequency of the signal which is represented by the shock response spectrum of the signal. For
further information see Annex A.
The peak magnitude of the
acceleration response from the system level test must be
reported for use in design validation investigations as well
as for developing follow-on testing. The magnitude of the
acceleration aids in determining the force that will be
applied to the circuit board during dynamic loading. The
peak acceleration is used to determine an amplification factor to the weight of any large components on the board as
well as to the board itself in order to properly design the
hardware to survive this loading. For further information
see Annex A.

Acceleration Magnitude:

Frequency Response: The frequency response of the

acceleration history is needed in order to assess the damage
potential contained in the shock event. The most damaging
energy is low frequency energy since it is associated with
the largest displacement of the hardware. A typical cut off
frequency for shock analysis is 500 Hz but the most damaging energy is usually contained below 200 Hz. Knowing

March 2009

the frequency content of the signal is also important

because the structural system responds to energy that is at
the resonant frequencies of the system. Knowing the resonant frequencies of the system and the energy in the input
shock at these frequencies can help in designing system
structural elements that can survive these loads. The frequency content of the shock input to the board measured at
the input points can be used in designing test fixtures and
profiles that will stress the board in a representative manner. For further information see Annex B.
6 SYSTEM BOARD LEVEL TESTING
6.1 Board Testing Background The primary goal of a

system board level shock test is to evaluate a system board

design without the chassis or other system components.
This may represent two distinct UCs. First, boards may be
dropped without protection during system assembly. In this
case, the device tested may just be a board or a sub assembly of the board with some system components. The second, a board level shock test, may reproduce the system
board response in the fully assembled system shock. The
components of the system will affect the motion of the
board. It is important to ensure that the impact of these
effects is accounted for in the system board test.
6.2 System Board Testing Recommendations
Sample Recommendations: It is assumed that the system
board used for testing is either the final shipping board or
is the equivalent board using daisy chain or mechanical
dummy components. If an equivalent board is used it
should match the system board in all essential features,
including:

IPC/JEDEC-9703

adjacent to the corners. If noncritical-to-function solder

joints are used, these should be routed in a separate chain
from critical-to-function joints.
Assembled boards should be preconditioned as necessary to the expected use-conditions. This
may include multiple reflow cycles, moisture soaking and
thermal cycling.

Preconditioning:

6.3 Correlation Criteria and Validity of Test Setup It is

expected that the system board test should reasonably correlate to system use conditions. There are two general
methods of matching acceleration and strain. If acceleration based methods are used then the strain should at least
be monitored to ensure the test is not excessive.
6.4 Equipment Recommendations The board level tests
depend on the board design and its interaction with a chassis. The basic concept is to mimic the chassis mounting.

The board can be mounted with the mounting screws onto

the standoff on a hard plate which is fixed on the shock
table, if the board is a through-hole mount, as shown in
Figure 6-1. For rack mounted systems a rigid fixture such
as the one shown in Figure 6-2 may be useful. The board
may be mounted on a boundary condition simulator (BCS)
which is mounted on the shock table (see Figure 6-3), if the
board assembly is an integral part of the system and a better board response match is desired.

Utilize the same BGA pad surface finish and quality.

Utilize the same PCB material and thickness.
Be assembled with a process that is similar to that
expected for the system board in terms of the board flux,
reflow profile and board handling.
Use components that represent the final product configuration materials in terms of mechanical properties, solder
materials, and surface finish; if testing a range of products, a worse case configuration may be used to reduce
testing costs.
Quality: The assembled boards should be free from quality issues that would adversely affect the results. Boards
should be inspected to ensure that the lands are within
dimensional tolerances and are free from plating defects.
Electrical test and X-ray inspection should be conducted on
all assemblies to verify that no opens/shorts exist, and to
establish that typical solder joint assembly criteria for
voids, bridging and abnormalities are met.
Daisy Chain Design: If electrical monitoring is to be used,
the daisy chain design should provide coverage for all corner joints. It is advisable to provide coverage of other joints

Figure 6-1
Plate

Illustration of a Board Level Test on a Hard

A BCS can be a modified version of the fixtures listed

above or a simplified chassis. A BCS should be tunable for
matching tests described in the following sub-sections.
Adjusting the stiffness of the mountings or the patterns of
the mountings, a board response on the BCS can be tuned.
Changing the edge bending to change the local stiffness of
the BCS can tune the board response too.
6.5 Test Flows
Qualification Testing: In this test flow, the correlated sys-

tem test is performed to replicate system level tests. The

11

IPC/JEDEC-9703

March 2009

selected test samples should also be subjected to failure

analysis to confirm results.
6.6 Failure Analysis Normal electrical testing is not
always able to reliably detect failure in solder joints. This
is especially true in shock testing where the joint may open
momentarily but remain in contact after the event passes.
Failure analysis should be used to verify all testing results.
Cross sections of the corner solder joints and stain techniques are both commonly used for these tests. See Annex
C for details.

Detailed reporting
recommendations are found in Annex A. Typically the
report will contain the strain levels tested, the acceleration
inputs (pulse type, duration, and amplitude), the electrical
test results, and failure analysis results. The report or
attached document should also describe the test setup
including the fixtures used, the board bend mode produced,
frequency and the board strain rate if practical.

6.7 Reporting Recommendations

Figure 6-2
Fixture

Illustration of a Board Level Test on a Rigid

7 COMPONENT MECHANICAL SHOCK ASSESSMENT

7.1 Component Assessment General Considerations

The primary goal of the component mechanical shock test

method described below is to create a procedure to evaluate component reliability using a simplified test board
assembly, rather than requiring more complex system level
tests. The mechanical shock response of the test boards are
correlated to the intended system application.
Figure 6-3
(BCS)

Illustration of a Boundary Condition Simulator

number of drops should be at least as great as that required

for the system level. In some cases the number of drops in
the worst case orientation may be raised to ensure robustness. Orientations that show little strain may be neglected
if desired. System boards using daisy chains should be
checked for electrical opens before and after the tests.
Functional system boards should be boot tested in a similar manner. A minimum of three randomly selected test
samples should also be subjected to failure analysis to confirm results.
Fragility Testing: In this test flow, the correlated test is
performed by starting with a selected input level and then
checking for electrical failure. If no failure is found the
input level is raised and the test repeated in this pattern
until failure is detected. Only the worst case orientation is
typically used. The number of drops at each level should be
kept to a minimum to avoid confounding results with
fatigue damage. This test adds the advantage of being able
to assess reliability margins, but is more complicated and
fatigue damage will accumulate during the test making
interpretation more difficult. A minimum of three randomly

12

This document specifies general recommendations for

mechanical shock evaluation of a test board. Derivative or
daughter standards may exist for specific applications and
should be consulted, where applicable.
7.2 Component Board Testing Recommendations
Material Recommendations: Use a test board that reasonably replicates the expected system board in terms of
mechanical properties, thickness, BGA pad surface finish
and quality. The board should be assembled with a process
that is similar to that expected for the system board in
terms of the board flux, reflow profile and board handling.
Use components that represent the final product configuration materials in terms of mechanical properties, solder
materials, and surface finish; if testing a range of products,
a worse case configuration may be used to reduce testing
costs.
Quality: The assembled boards should be free from quality issues that would adversely affect the results. Boards
should be inspected to ensure that the lands are within
dimensional tolerances and are free from plating defects.
Electrical test and X-ray inspection should be conducted on
all assemblies to verify that no opens/shorts exist, and to
establish that typical solder joint assembly criteria for

March 2009

IPC/JEDEC-9703

voids, bridging and abnormalities are met. See IPC-6012

and IPC-9252 for further information on bare board qualification and electrical test.

towers as described in the system test section above,

although any equipment capable of producing repeatable
results that meet the correlation criteria is acceptable.

Daisy Chain Design: If electrical monitoring is to be used,

the daisy chain design should provide coverage for all corner joints. It is advisable to provide coverage of other joints
adjacent to the corners. If noncritical-to-function solder
joints are used, these should be routed in a separate chain
from critical-to-function joints.

There are two general testing flows

for component board testing: characterization tests and
qualification tests. In the former, the goal is to establish the
maximum extent of the components capability. For qualification testing, however, the components ability to meet a
set performance criteria is determined.

Assembled boards should be preconditioned as necessary to the expected use-conditions. This

may include multiple reflow cycles, moisture soaking and
thermal cycling.

7.5.1 Characterization Testing A characterization test

flow consists of two testing rounds. The first round is used
to find the critical strain level at which the component fails
as measured by electrical monitoring. Subsequent testing
can be used to establish the component strain capability
limits in terms of allowable damage. An example test flow
is shown in Figure 7-1.

Preconditioning:

There are other conditions that may also impact the test
results, but at present there is insufficient data to standardize their use. Time between reflow and test may have significant impact on the reliability of the solder and should
be recorded and reported. Enabling hardware used to constrain heat sinks may apply significant load. The strain
induced by this load should be recorded. The component
board test should represent the impact of both the heat sink
mass and compression loads. If supplemental adhesives
such as underfill or corner-glue are to be used on the system, then similar materials and processes should be used in
the component test. Moisture sensitivity level should be
considered if supplemental adhesives are used.
Elapsed Time after Reflow: Strain-to-failure and/or failure
modes may be sensitive to elapsed time between the
mechanical shock test and the last solder ball reflow. Consequently, shock acceptance criteria may differ, depending
upon elapsed time after reflow. For data comparison, the
same elapsed time after reflow and total number of reflow
exposures should be used.
Post-Stress Test: Depending on the specific production

flow or reliability stress test condition, e.g., burn-in, preconditioning, high temperature storage, temperature
cycling, etc., the tested devices may produce lower or
higher strain-to-failure values than the time-zero test
results, and the values expected must be adjusted appropriately. Coarsening of solder grain structure following
extended temperature exposure may result in an increased
bulk solder failure rate.
7.3 Correlation Criteria and Validity of Test Setup Cor-

relation of the component test should be based on the criteria listed in the correlation criteria section of this document. The correlation study should be documented.
It is expected that the component board test should reasonably correlate to system board in terms of the strain range,
bend mode, frequency and board strain rate if practical.
The test equipment
used for component board testing will generally be drop
7.4 Equipment Recommendations

7.5 Testing Flows

As shown in Figure 7-1, the test flow has two distinct

stages, critical strain determination and validation. In the
cliff-finding stage the goal is to determine the maximum
strain value at which the component is still electrically
functional. As illustrated in Figure 7-1, a test board is
tested at increasing level until it fails. Other boards are then
tested to confirm the strain level for failure.
Table 7-1 summarizes an example of this process. In this
example the component is required to survive six drops to
correlate to the expected use-condition. Board number 1 is
dropped six times each at 1,000 Strain and 1,200 Strain
before it failed on the first drop at 1,400 Strain. The second board is then dropped six times at 1,300 Strain and
five times at 1,400 Strain before failing. Since board numbers 1 & 2 both failed at 1,400 t Strain, but only after
many drop cycles, the engineer choose to run board 3 at
1,400 Strain. After passing six drops, the board then failed
on the first drop at 1,500 Strain. To confirm the capability
at 1,400 Strain, board number 4 is also dropped at 1,400
Strain, the required six drops, and fails after two drops at
1,500 Strain. This confirms the maximum strain limit of
1,400 Strain.
It is prudent to define the capability limits of the component based on failure analysis results and electrical data. In
order to demonstrate the true capability of the component,
this test flow includes a validation stage. In this stage, two
strain levels are tested. These have been reduced from the
maximum strain limit found in the first stage. Each sample
should be dropped the number of times required to meet
the use-condition. After testing, each unit should be electrically tested and undergo failure analysis to determine the
extent of solder joint cracking. If the extent of cracking
exceeds the allowable crack size, then retesting may be
required. Otherwise the strain limit should be set to the
highest strain level that meets the crack criteria.
One of the advantages of this test flow is that it gives fundamental understanding of the failure mechanisms and
13

IPC/JEDEC-9703

March 2009

Critical Strain
Determination
Set Initial
Input

Shock with
Electrical Monitor

Increase
Input

No

Fail?

Validation
Strain to failure
Determined?

Yes

Test validation
samples at strain
level 1

Strain = Maximum
Functional Strain
Test validation
Samples at strain
level 2

Remove board from

test fixture,
install new board

Failure Analysis of
all to determine
crack size

Select new
input level
Reduce Strain
And Retest

Both
Fail

Select level
with acceptable
crack
IPC-9703-7-1

Figure 7-1

Flow Chart for Characterization Test

Table 7-1 Example of Critical Strain Determination

Results. Value indicates number of drops at each
level. (Shadows indicates electrical failure.)
Board
#

1
2

1000ue 1100ue 1200ue 1300ue 1400ue 1500ue

1
6

When the user only desires

to know whether a component will meet a particular
requirement, an abbreviated testing flow can be used. This
testing flow consists of testing the component in a prescribed manner and at a prescribed level.

7.5.2 Qualification Testing

mode. It also allows understanding of capability and margins compared to system requirements to better optimize
component and system design. It can be used to quantify
the impact of process and material options. It can also be
used to verify Finite Element simulation results. Lastly,
14

understanding the capability provides some protection

against being forced to retest if the system requirements
should change. This test flow, however, is more expensive
and requires more material, testing and failure analysis
time.

The testing consists of instrumenting a small number of

test boards to ensure that the shock table is properly configured to produce the required response in the component
board. Once the setup has been validated, then the samples

March 2009

are tested and set for failure analysis. If a large sample size
is to be tested, then test boards with strain gages should be
interspersed among the samples to verify that the setup has
not drifted. In this test flow, electrical testing should be
used to demonstrate that the component meets the requirements. A minimum of three randomly selected test samples
should also be subjected to failure analysis to confirm
results.
This test flow has the advantage of being very quick and
limited only to the critical testing levels. It can also be performed on live product samples rather than requiring daisy
chain test vehicles. It does not provide for margin assessment. It requires a very clear correlation to the end usecondition. The test flow may also require multiple tests if a
range of applications are to be supported or if the requirements change after testing has been completed.
7.6 Failure Analysis Normal electrical testing is not
always able to reliably detect failure in solder joints. This
is especially true in shock testing where the joint may open
momentarily, but remain in contact after the event passes.
As such, failure analysis should be used to verify all testing results. Cross sections of the corner solder joints and
stain techniques are both commonly used for these tests.
See Annex C for details.

Detailed reporting
recommendations are found in Annex A. Typically the
report will contain the strain levels tested, the acceleration
inputs (pulse type, duration, and amplitude), the electrical
test results, and failure analysis results. The report or
attached document should also describe the test setup
including the fixtures used, the board bend mode produced,
frequency and the board strain rate if practical.

7.7 Reporting Recommendations

8 METRICS FOR MATCHING TEST

It is very important to choose the right metrics for demonstrating correlation between tests. The available metrics
include acceleration, board strain, and board deflection.
Each is discussed below. Table 8-1 may be useful providing guidance on selecting a method based on the intended
use and test condition.
8.1.1 Acceleration Based Method
Amplification Factor Based Matching: In simple systems

it may be possible to use amplification factors to simulate

the loading of the system on the board. This method is
illustrated in Figure 8-1. In the system, the acceleration (as)
measured at the mount point of the board can be related to
the input acceleration by a simple amplification factor. The
acceleration at the board is usually measured at the heaviest component (ab). The amplification is related to the natural frequency ratio and the mass ratio between the board
and the chassis. In cases where the chassis bending is trans-

IPC/JEDEC-9703

mitted to the board, the factor is approximately two and

reduces for stiffer chassis. This method has been widely
used for simply mounted boards. For boards that have more
complex interactions with the system or chassis, other
methods should be used. In this method the accelerations at
key components and the board mounting points are the initial matching criteria. These should be matched in terms of
both acceleration amplitude and Shock Response Spectra
(SRS). Finally, board strains should also be matched, as
board acceleration does not necessarily replicate solder
joint loading even when matched. Care should also be
taken to ensure that the natural frequency of the board test
sample reasonably matches that of the system test. This is
best ensured by matching the SRS. Lastly, as the board
must be mounted to the shock table, limitations in the
shock table inputs may also limit the ability to match system tests.
Complex System Matching: In many cases the amplifica-

tion method will not be able to sufficiently match the system response. These include cases where there is significant interaction with the chassis and board, such as a laptop
or server board with chassis mounted thermal solutions. In
these cases, the user must decide the extent of matching
desired. The same board may be used in multiple systems.
Within the board there are multiple components. It may not
be practical to attempt to develop a test to match the full
range of systems and the response at every component on
the board. Matching can vary from the simple matching of
the worst case corner of the worst case component (worst
case as determined by system testing and failure analysis),
to matching the entire board response in a single drop orientation. To match a system board level test to that for system level test, it is required that both test board boundary
condition and the shock input be tailored. In cases with
complex interaction, a boundary condition simulator or
chassis surrogate may be used.
One can also improve matching by
matching the distribution of acceleration as a function of
frequency, through the use of SRS. In brief the SRS represents the acceleration response of the system in discrete
frequency bands. This method is described in detail in a
number of shock testing handbooks and textbooks. These
books describe many criteria for matching SRS, but in
practice the most conservative methods are used which
envelope all of the resonant peaks. In Figure 8-2, the SRS
for three systems are shown for an accelerometer mounted
near the component of interest. The board test shows an
attempt to envelope the system responses. As can be seen
in the figure, the response on the board test is larger in
magnitude at nearly every frequency. Importantly, it is
larger at the resonance peaks indicated. However, since the
resonant response of the test board is very much larger than
the systems, this test may be excessively conservative.

SRS Correlation:

15

IPC/JEDEC-9703

March 2009
Table 8-1

Test Condition or
Use Condition

Recommended Matching Criteria for Selected Use and Test Conditions

Packaged System

Unpackaged System

Shipping Drop

Drop Height
Impact Orientation
Package Weight

Acceleration at contact
points
Acceleration response at
large components

End User Drop

N/A

Expected drop height

Impact angle
Impact surface

Handling Shock/
Bump

N/A

Acceleration at contact
points
Orientation

Board Handling
Shock

N/A

N/A

kb
as=Fsa

mb

ks

ab=FbFsa

kb
a

Fsa
IPC-9703-8-1

Figure 8-1 Basic Model for Board Level Testing

(Assumes Worst Case Amplification and no other
Interaction with Chassis)

Implications of acceleration based matching: Acceleration

is a popular approach due to the ease of setup and wide
spread availability of the data acquisition systems; however, for developing tests for solder joints at the system
board or component board level, acceleration poses a
couple of challenges. First, acceleration is a global measure
of motion. One cannot determine if a resonance response is
coming from the board response or from the chassis, without more complex modal analysis. Secondly, recent literature has shown that the flexure of the board is the primary
cause of solder joint failure rather than inertial loading of
the device. Matching the acceleration does not indicate that
the local flexure is equivalent. As such, strain is the preferred matching criteria for board level test.
The use of strain
gages has several advantages for analyzing solder joint reliability. The strain is independent of rigid body motion and
8.1.2 Board Strain Based Method

16

Component Board Test

Acceleration (input
acceleration profile and
SRS amplitude response)
Board Strain

Board Strain (amplitude,

mode, and frequency)

Drop Height
Orientation

Board strain (amplitude,

mode, and frequency)
Input acceleration profile
SRS response

far field motion. Finite element analysis has shown the correlation of the local strain to the stress in the solder joint.
Strain gages can also be placed in highly confined spaces
inside systems and do not require a clear line of sight.

mb ab=FbFsa

ms

System Board Test

Using these advantages, strain gages can be used to correlate shock tests in several ways. These include: comparison
of strain amplitude, frequency or strain rate matching, bend
mode determination and settling time analysis. Each of
these is discussed below.
Board Strain Amplitude Correlation: Board strain amplitude is the most significant correlation metric. It requires a
fine tuning after the other metrics are correlated. For strain
gages placed on the opposite side of the board from the
component, the minimum principal strain is typically used
for correlation, being an indication of tensile loading of the
solder joint. Often a strain time history will show multiple
peaks in the strain signal. The highest should be used.

To accomplish matching, other metrics such as bend mode

and frequency are usually matched first. The table input
can then be increased or decreased to match the strain
amplitude. Care should be taken to ensure the setup
achieves the desired strain at a reasonable input acceleration. A setup requiring excessive acceleration inputs compared to the system level tests may indicate a poor setup
design. Excessively large inputs can lead to issues with
board mounts and/or heat sink attachment failures and/or
other undesirable and artificial failure modes.
At fine tuning, single peak values in maximum principal or
minimum principal strain may be used for direct comparison for convenience. Fine tuning board strain amplitude
normally can be achieved by changing the shock table
input amplitude.
When a circuit board is installed to a chassis, static (or
preload) board strains may result. Typically, thermal solutions, board mounting points and system interface structure
can cause the board to deform during installation. These

March 2009

IPC/JEDEC-9703

800
System 1

700

Board Test

System 2

Acceleration (g)

600

System 3
Board Test

500

System 3
System 1

400

System 2

300
200
100
0
10

100

1000

Frequency (Hz)
Figure 8-2

IPC-9703-8-2

Example of Correlation of a Board Test to Three Test Systems

preloads may affect solder joint reliability and the strain

measurement. If the time duration and thermal exposure
between static strain events are minimal, the creep effects
during board installation may be ignored, depending on
specific solder alloy, surface finish, solder joint geometry,
etc. Assuming minimal elapsed time between static (from
assembly/installation) and dynamic loading, the static and
dynamic strains may need to be combined for proper
matching. The total board strains can be calculated using
the equations below in two steps: In the first step, the combined board strains are computed for each grid of the strain
gauge measurement:

by Figure 8-3. A comparison of the angle of the points

yields the bend mode. Ideally all the points would fall
along the critical angles shown (45 and - 135 for spherical, 0 and -90 for planar, and -45 for saddle or twist). In
practice, the data will scatter and the nearest ideal line
should be selected as illustrated by the colored zones in the
figure.

Min Principal
Spherical

e i (t) = e Si + e Di (t), i = 1, 2, 3

Planar

In the second step, principal strains are computed using the

combined grid strains:
1x2 =

Max Principal

e1 + e3 1

(e1 e2)2 + (e2 e3)2

2
2

Saddle (Twist)

Where ei (i=1, 2, 3) represents the combined grid strain,

the superscripts S and D represent static and dynamic,
respectively and 1 and 2 are maximum principal strain
and minimum principal strain respectively.

Figure 8-3

Board bend mode can be visualized by using board strain states plot, as shown in Figure
8-3. At each strain data point, the minimum and maximum
principal strain are calculated and then plotted as illustrated

The board strain states plot presents the board bend curvature and bend mode that are directly related to solder joint
risk. Finite element modeling has shown that, for the same
strain magnitude, the stress is higher in the solder joint for

Bend Mode Correlation:

IPC-9703-8-3

Definition of Board Strain States Plot

17

IPC/JEDEC-9703

March 2009

When comparing the board bend modes, the X and Y

scales for the plot should be the same. An unequal scaling
can cause skew of the plot thus skew the bend mode. Overlay plot is suggested for better visualization to compare
board test and system test and/or component test. Figure
8-4 shows an example strain state plot comparing the system level test data to a proposed system board level test. In
this case, the system test is more planar. The proposed system board level test matches well in the compressive/
positive portion of the plot and is more conservative (more
spherical) in tensile/negative portion of the plot.
Board Strain States

Figure 8-5 shows the time history of strain in

a system being dropped. In this system there is a single
large strain event. In such cases it can be convenient to
determine the time from the beginning of the event to the
strain peak which is called the rise time (tr). If in two systems the strain magnitude and rise times are matched, then
the strain rate is also matched assuming that the response
can be treated in a linear fashion.
Rise Time:

Board Strain Settling Time

500
Board Strain (ue)

spherical and saddle modes than for planar modes. Matching in the strain state or bend mode is therefore important
in developing a testing method. If a variety of modes are
observed, then it is advisable to use a conservative mode
when matching.

tr

0
2.22 2.24 2.26 2.28 2.3 2.32 2.34 2.36
-500
-1000
-1500

ts

500

Min Principal Strain (ue)

-2000
-500

Time (sec)
0

500

1000

1500

2000

-500
-1000
Chassis
Fixed Plate

-1500
-2000

Max Principal Strain (ue)

IPC-9703-8-4

IPC-9703-8-5

Figure 8-5 Settling Time for a Typical System Level Test

with High Damping and Rapid Decay in the Strain
Frequency Matching: In many cases the shock input will
create an oscillatory motion in the PCB, as shown in Figure 8-5 and Figure 8-6. In these cases it is simple to calculate the resonant frequency of the response. This is commonly done using a Fast-Fourier Transform (FFT)
calculation which is implemented in many data acquisition
systems. From the FFT one can determine the primary frequency components of a response. If the amplitude and
frequency responses of two systems are matched, then
strain rate will also have been matched.

Figure 8-4 Comparing Board Bend Modes of Board in

System Chassis and Mounted to a Fixed Plate

Board Strain Settling Time

properties of solder materials are rate dependent. This

dependency can affect the reliability of the solder joint and
can shift the failure mode. It is therefore important to consider the strain rate in correlating tests. As there is no
means to directly measure the complex strain state in the
solder ball, board strain is substituted.
One can directly compute the
strain rate by taking a derivative of the strain time history.
Care should be taken however to not introduce errors
caused by measurement noise. All experimentally acquired
data is subject to many kinds of noise. Noise prevents use
of a simple forward or backward difference, (i+1 - i)/t,
method of computing the strain rate. The data must either
be smoothed first via filtering or using a regression fit to
the desired portion of the time history.

Strain Rate Calculation:

18

Board Strain (ue)

Frequency/Strain Rate Correlation: It is known that the

500
0
6.5
-500

6.6

6.7 6.8

6.9

7.1

7.2

-1000
-1500

ts
Time (sec)

IPC-9703-8-6

Figure 8-6 Typical Time History for a Component Board

Test with Minimal Damping
Dynamic Event Settling Time Evaluation (Relating to
Dynamic Damping): A board strain response can reveal

the system damping effect. More free vibration cycles are

March 2009

expected to occur for low damping system after a shock or

drop impact. These can lead to fatigue damage. Obviously,
lower damping system means higher solder joint risk, if
they have the same board strain amplitude, board bend
mode and vibration frequency.
As such, it is also important to have a reasonably correlated
settling time. Figure 8-5 and Figure 8-6 compare the settling times of two tests. The second test may lead to overly
conservative results due to the excessive number of board

IPC/JEDEC-9703

oscillations for a single input pulse as compared to the first

test. The settling time can be estimated by assuming the
steady state zone is 10% of the peak value, in this case,
250 Strain. The settling time is the time from the start
of the event to the point at which the strain remains within
the steady-state zone. The zone should be greater than possible error and variance. An alternative way to define the
zone is to use the effective board strain value within which
the solder joint damage is not continued.

19

IPC/JEDEC-9703

March 2009

Annex A Sample Data Reporting Format

Test Report Recommendations A test report including comprehensive documentation of the bend test is recommended
(see Tables A-1 through A-3). Disclosure of the test report contents will depend on specific customer/supplier agreements.
Table A-1

Test Report Recommendations (Equipment and Materials)

Category

Description

Equipment

Manufacturer, model number and operational conditions for the following: drop or shock equipment used
strain measurement equipment
continuity monitoring equipment
spectral analysis/accelerometer equipment

Fixture

type of fixture used and photograph

support locations used
fixture materials

Component

package outline drawing or reference to JEDEC outline

die dimensions (width, length and thickness) and orientation (rectangular die)
daisy-chain connection map and/or net list
measured solder ball or lead coplanarity
solder ball shear values or lead pull strength, and associated failure modes (parts from same production lot
as tested devices)
solder-wetted pad dimensions, if applicable
solder ball land pad type, if applicable (solder mask defined, etc.)
lead finish/pad metallization, including thicknesses of all layers and composition of solder, if applicable

Test Board

width, length and thickness

dielectric material
surface finish
external trace, pad and solder resist opening dimensions measured board coplanarity

Strain Gage

manufacturer and part number resistance

strain gage element size
strain gage locations used

Table A-2

Test Report Recommendations (Board Assembly)

Category

Board Assembly

Description

preheat temperature, ramp rate, critical peak temperatures

(solder, package surface, board, etc.) duration above solder liquidus temperature and cooling rate
solder composition
solder paste metal percentage, particle mesh size type and flux type
reflow atmosphere
nominal solder paste volume
nominal solder joint geometry
component/PCB storage and/or bake-out conditions prior to board assembly
storage conditions and duration following board assembly

20

March 2009

IPC/JEDEC-9703
Table A-3

Test Report Recommendations (Test Results)

Category

Set-up data

Description

drop height or input acceleration history

torque setting used to screw attachments

Strain data (each

test board)

strain vs. time (max & min principal, gage component should be retained)*
maximum strain-rate or strain-rate vs. time **
acceleration (both input and near the component) vs. time

Resistance data
(each test board)

resistance vs. time

Failure distribution

test condition/cycle count at which failure occurred

cumulative failure percentage for test level(s)
failure map by location for dye-and-pry data, showing percent crack and mode

Failure mode

failure mode histogram (all test packages)

time-zero cross-section of a single pkg/board test assembly
failure analysis of representative sample of each observed failure mode

*Note: measurements at each strain gage location should be reported

**It is recognized that the strain rate vs. time calculation is subject to factors which may influence its accuracy and relevance. This calculation is a second
derivative and thus can magnify any noise in the strain vs. time measurement. Although strain rate vs. time information can be valuable, one must use
caution in interpreting the results. If strain rate vs. time is reported, the method used to smooth the data (regression, filter, etc.) should accompany the
report. See 8.1.2 for guidance on performing the calculation.

21

IPC/JEDEC-9703

March 2009

Annex B Metrologies
B.1 Strain Gage Use and Techniques

age. Default location would be opposite the corner most

solder joint. For comparisons between system and component testing, precise gage location should be documented
and held consistent. In the example below, the peak strain
location was offset to the interior from the corner most ball.
The gage was placed accordingly.

B.1.1 Strain Gage Selection There are a multitude of

strain gages available; however, only small, stacked
rosettes are required. Coefficient of thermal expansion
compensation and high temperature dielectric are not
required for room temperature testing. Pre-attached lead
wires simplify instrumentation of the test, but may not be
available or be the at lowest cost. Gage element size should
be on the same order of the package solder ball pitch, not
to exceed 2.0 mm [0.079 in]. For comparisons between
system and component testing, gage selection should be
documented and held consistent. Gage resistance is usually
120 Ohms or 350 Ohms, and either is acceptable. Strain
gages with pre-attached lead wires are available in two and
three wire arrangements. A three-wire configuration is preferred for improved accuracy and noise reduction. A twowire configuration may be used to ease wire routing; however, it is recommended that a transition to a three-wire
configuration be placed as near as possible to the gage.

Orientation of strain gages should be recorded. Recommended strain gage orientations at all corners are shown in
the example in Figure B-1. This arrangement keeps the
orthogonal sensing elements aligned to the edge of the
package.
In situations with high component density, gage lead-wire
routing or interference with other components may constrain gage placement. Small, adjacent, interfering components may be removed without affecting results. It is not
recommended that large adjacent components be removed.
Silk Screen: It is advisable to print a silk screen on the
board to guide the placement of strain gage within acceptable visual tolerance.

Strain gages are typically

located on the secondary side of the board at the highest
strain location. Positioning of the strain gage is in reference
to the center of the gage resistive element grid. Determination of location may be based on finite element analysis,
failure analysis, or experimental measurements. In most
applications, this location will be at the corner of the packB.1.2 Strain Gage Placement

Attachment Method: Follow manufacturers recommendation and process. Cyanoacrylate adhesives are acceptable
for room temperature testing.
Wire Routing: Care should be taken in routing gage leadwires so that they are not to interfere with the dynamic
behavior of the system or test board. This is especially a

PIN-1

3
2

2
3

1
IPC-9703-B-1

Figure B-1 Wire (a) Strain Gage Location with Respect to Solder Ball at Package Corner. (b) Orientation of Strain Gages
for every Package Corner

22

March 2009

IPC/JEDEC-9703

concern for testing of small form factor and hand held

devices. Figure B-2 shows an example of wire routing in a
small form factor laptop. Small diameter wiring is used to
route strain signals away from the components. On the
exterior of the device, it is advised that the wiring is scaled
up to a larger diameter wire which is less fragile and easier
to connect to the data acquisition system.

Gage Lifetime: Gages are designed for single installation.

The adhesive may degrade due to time, temperature and
moisture exposure. Follow gage manufacturer recommendations.
B.1.3 Data Acquisition Recommended scan frequencies

for typical applications are shown in Table B-1.

Table B-1 Recommended Scan
Frequencies for Various Systems
Typical
Frequency
Response
(Hz)*

Minimum
Sampling
Rate (Hz)

Maximum
Hardware
Anti-aliasing
Filter (Hz)

Server/
Communications

20-300

3,000

1 ,200

Desktop

40-500

5,000

2,000

Laptops

50-600

10,000

4,000

500-4000

50,000

20,000

System Type

Cell Phone
and Handheld

Figure B-2 Wire Routing should be done So as Not to

Affect Results

In the case of test boards, this problem may be eased by

including wiring for the strain gage directly in the PCB
circuitry. The gage itself is then connected to the PCB by
soldering the gage leads into plated through holes or surface mount pad. This is illustrated in Figure B-3.

G1-

G1+

*Note: Shipping shock will typically produce a lower frequency response

while user drop of an unpackaged system may excite a higher frequency
response.

Table B-1 follows the rule that the sampling rate should be
greater than 10 times the highest frequency of interest, to
accurately capture strain response.
The frequency range of the system response can be determined via a Fast Fourier Transform (FFT) analysis of the
strain data. An example is shown in Figure B-4. For this
system there is a significant response at approximately 400
Hz; the minimum sampling rate should be at least 4000Hz.

G2+

G3+
G3IPC-9703-B-3

Figure B-3 Wire Artwork Showing Strain Gage Feature

and Internal Board Routing

Response FFT

G2-

240
220
200
180
160
140
120
100
80
60
40
20
0 100 200 300 400 500 600 700 800 900 1000
Frequency (in HZ)

Strain gage lead wires should be protected with adequate strain relief. Damage to unprotected
lead wires is common in mechanical shock testing. In free
fall shock tests it can be challenging to secure the wires in
light weight systems without influencing the way the system falls, so in these cases guided drop systems may be
advised.
Wire Strain Relief:

Quarter Bridge Setup: Strain gages should be wired in a

quarter bridge setup due to a lack of symmetry in strain.

IPC-9703-B-4

Figure B-4
System

Fast Fourier Transform of an Example

Table B-1 also shows the minimum setting for analog antialias filters. These filters are used to prevent the inadvertent sampling of high frequency data as a lower frequency
(see Nyquist Sampling Theorem). Many modern data
acquisition systems may automatically select an appropriate filter.
23

IPC/JEDEC-9703

Digital filters may also be used to eliminate high frequency

noise from the strain signal. Filter type and cut-off frequency should be selected to optimize signal response. If
one suspects excessive electrical noise, it is advisable to
attempt to isolate these by using a three wire setup and
braiding the lead wires where possible. Ground isolation
transformers may also be used to isolate data acquisition
equipment from noise in the incoming power.
B.2

Accelerometers

There are many available accelerometers. The weight of the selected accelerometer should be minimum, internal damping well outside the
frequency of system and size small without interfering. The
frequency range and the linear range should also be considered. For solder joint reliability testing, a single axis accelerometer will be sufficient as the out of plane is of primary
interest.

B.2.1 Accelerometer Selection

B.2.2 Accelerometer Placement Placement depends on

how the data is to be used. Mount points for test development near the components of interest.

For systems that can be easily

opened, simple wax attachment can be used. For systems
that will be subjected to severe shocks or cannot be easily
accessed, adhesive attachment should be used. Follow
accelerometer manufacturer guidelines for adhesive and
wax attach.
Attachment Method:

Wire Routing: Care should be taken in routing accelerom-

eter lead-wires so as not to interfere with the dynamic

behavior of the system or test board. This is especially a
concern for testing of small form factor and hand held
devices.
Wire Strain Relief: Accelerometer lead wires should be
protected with adequate strain relief. Damage to unprotected lead wires is common in mechanical shock testing.
In free fall shock test it can be challenging to secure the
wires in light weight systems without influencing the way
the system falls; in these cases guided drop systems may be
advised.
Instrument Lifetime and Calibration: Accelerometers
should be calibrated per the manufacturers recommendation.
B.3 High Speed Photography and Motion Analysis Systems A high speed camera is a measurement tool that
requires calibration, and (like other measuring tools) is
dependent on proper setup. This includes the selection of
the correct lens, correcting for geometric induced errors
and selecting a frame rate that will eliminate image blur.

24

March 2009

The highest possible pixel resolution of the high speed

camera is also a large factor for total accuracy.
B.3.1

Setup Recommendations

Line of Sight: In order to track the movement of a target

point or feature on a board assembly, the camera must have

an unrestricted line of sight. This can be achieved through
positioning of the camera and/or the use of creative solutions including mirrors, light weight post (target) or line of
sight openings in chassis or test fixtures. With a 2D camera
setup the camera needs to be perpendicular to the centerline of the sample at a vertical angle that will maintain a
line of sight through the event.
Sample Setup and Preparation: To prepare a sample or
printed circuit board for imaging, an array of targets suitable for tracking with the motion analysis software needs
to be applied to the sample in known locations. These X
axis and Y axis dimensions are tied to the Z axis dimensions from the motion analysis software to generate surface
profiles at any selected point in time during the event.
B.3.2 Calibration The point displacements are measured

by tracking a target as it moves through a camera field of

view and assigning a dimensional value for an individual
pixel for the target being tracked. The pixel dimensions are
influenced by the geometric relationship of the target relative to the camera, as well as distortions from the lens curvature.
Geometric Introduced Errors: Geometric factors including
distance of the target from the camera, the relative angle of
the camera and the relative angle change of the sample as
it moves through the field of view will all introduce
changes to the value of a pixel. The tools for correcting
these factors are included in the image analysis software
and it is up to the user to define what methods are best fitted to their accuracy needs.

Basically the angle of the camera is measured and an

image of a scale block with 4 points with known spacing is
captured at the physical point of the target to be tracked.
These captured images are imported into the motion analysis software to create a motion plane that corrects for all of
these factors for the individual target point.
Lens distortion errors can be minimized
by using longer focal length lenses or eliminated with the
use of correction factors included in the software (only
required for wider angle lenses).
Lens Distortion:

There are several software

packages available that will provide the ability to scale and
track target points on an object in motion. Select the best
package that meets your budget and accuracy requirements.

B.3.3 Tracking Software

March 2009

IPC/JEDEC-9703

Annex C Shock Failure Analysis of Electronic Components

C.1 Scope To support the shock methodology, the use of
failure analysis is critical and should be performed at a
level that clearly identifies the failure mechanisms and
locations involved. The following sections discuss failure
analysis recommendations in more detail.

If failure distribution is
unknown and of interest, the Weibull model is recommended. When data is limited, true statistical representation is extremely risky as characterization of mean, standard deviation, etc. becomes meaningless for small sample
sizes.

C.1.1 Failure Statistics

C.1.2 Guidance for Failure Analysis It is recommended

that failure analysis be performed on samples representing
the full population. The use of only early (low strain, low
stress, low cycle count, etc.) or late (high strain, high
stress, high cycle count, etc.) failures could be misleading.
The number of samples selected for failure analysis will be
dependent on the experimental plan, previous knowledge
of failure signatures and testing objectives, etc.
C.1.3 Failure Criteria Prior to a test start, it is necessary
to document a threshold increase in resistance which could
be defined as an electrical failure during shock testing.
This should be accomplished via continuous monitoring on
the order of the strain and acceleration sampling rate, i.e.,
of at least 10x of the natural frequency. In shock testing, an
electrical resistance change, even for a brief period, may be
an indication of damage. Although a 20% increase in daisychain net resistance may be appropriate for transient bend
loading, a different threshold may be required for a
dynamic loading due to test equipment capability and specific daisy-chain design scheme. If no prior knowledge of
the resistance increase is available, it is recommended that
a characterization study be completed before full testing
begins.

The clear goal of failure analysis is the ability to detect the

location, mode and mechanism of damage. A failure can
be defined as observed mechanical damage (pad lifting/
pad cratering, interface delaminations, solder joint cracking, trace cracking, etc.) or an increase in electrical resistance beyond the previously defined acceptable threshold.
For shock tests completed without an electrical failure
being observed, it is recommended that failure analysis be
performed to ensure that damage was not missed due to
issues with test hardware or the inability to monitor partial
damage.
C.1.4 Failure Analysis Techniques Failure analysis
techniques consist of two types: destructive and nondestructive. Nondestructive failure analysis tools that may be

used include x-ray, coupled scanning acoustic microscopy

(CSAM), and side view optical microscopy, etc. Common
methods and tools for destructive failure analysis include
cross section, dye and pry, and dye and pull. Some techniques such as CSAM, x-ray, scanning electron microscopy
(SEM) and energy dispersive x-ray (EDX) can be used to
analyze samples undergoing destructive or nondestructive
techniques.
The mechanical failure mode(s) of each component and
assembly should be identified. It is recommended that each
observed failure mode be documented using an appropriate
failure analysis technique. Before using any destructive
technique, the assembly should be inspected by optical
microscopy and the overall apparent damage, including
those to package, solder joint, and PCB traces/vias, should
be documented. Destructive techniques should then be used
to determine the failures. Example failure modes for solder
ball array style packages are illustrated in Figure C-1. Note
that electrical monitoring may not identify many of the
failure modes shown in this figure. Failure modes include
solder cracking and breakage, package body cracking and
separation/delamination, and cracking between the various
lead, Inter-Metallic Compound (IMC), solder and PCB
metal pad interfaces.
C.1.5 Example of Failure Characterizations
Area Array Cross-Sectioning/Inspection Figure C-2
shows typical cross-sections for an area array package.
Diagonal sections may also be desirable in the package
corners.

The sectioning samples should be potted or encapsulated in

an appropriate medium. The cross-section cut should be
made through the approximate center of each solder joint
depending on the area and pattern geometry.
Inspection should be conducted under a microscope/SEM
and the following images generated:
The whole cross-section (may be combined from multiple
images) Magnified individual failed solder joints (at appropriate magnification levels to clearly show the damage)
C.1.6 Dye and Pull/Pry Test Description The following

procedure describes the method that should be used for

Dye and Pull/Pry.
Recommended Tools:

Low viscosity colored layout fluid (dye).

Mechanical force testing equipment or pull gage (for dye
and pull).
Screwdriver or pliers (for dye and pry).
Microscope.
25

IPC/JEDEC-9703

March 2009

Package Substrate
Metal Pad

Fracture @ pkg side

IMC/solder interface

Fracture @ pkg
metal/IMC interface
Pkg pad lift/crater

Solder Ball

Fracture within bulk solder

Fracture @ PWB side

IMC/solder interface

PWB pad lift/crater

Fracture @ PWB
metal/IMC interface

Metal Pad
Printed Wiring Board (PWB)

IPC-9703-C-1

Figure C-1

BGA Solder Joint Failure Modes

Carefully place the container with the specimen inside

vacuum chamber, to allow the dye to penetrate into any
cracks or crevices.

A1 Corner

Middle (Optional)
(includes center)

Edge

Remove the specimen from the dye. Excess dye is

removed by hanging the specimen and allowing it to drip.
Place the specimen in oven to dry at 100C for eight
hours. Alternatively, place the stained specimen in a ventilated hood in room temperature for 24 hours to allow
the dye to dry.

Diagonal
Pull/Pry Procedure:
IPC-9703-C-2

Figure C-2

Area Array Cross-Section Diagram

Saw for isolating the package area.

Cleaning solution or acceptable PCB assembly cleaning
procedure.
Bake chamber for drying.
Vacuum chamber.
Recommended Dye Procedure:

For Pull: mount the specimen to mechanical pull testing

equipment or pull gage and remove the specimen.
For Pry/Peel: use a screwdriver or pliers to pry the corner
of the package. This should be done quickly with the
intention to remove the entire package.
Visually inspect and document the failure locations on
both board and component side using a microscope and
visual-analysis software (if available).
The presence of dye on a fracture surface is an indication
that damage occurred prior to the package removal.

Place specimen in a container and pour enough IPA to

entirely submerge the specimen in solution. Leave the
specimen in solution for about 5 -10 minutes. Remove
units from IPA use compressed air gun to dry. Let the
specimen air dry for 1-2 minutes and then discard IPA in
a proper container. Or it is permitted to apply a users
standard PCB assembly cleaning procedure. An ultrasonic
bath is not recommended because it can propagate a solder joint crack.

Failure Mechanism and Mode Description:

Place the specimen inside a container and fill the container with dye until the specimen is fully submerged.

Identification of key trends and conclusions/

recommendations.

26

Record all failures by location within the package and

printed circuit board and the type of failure mode.
C.1.7 Report

Background including test setup, DOE plan, etc.

Summary of results including images, failure mode by
location, etc.

March 2009

IPC/JEDEC-9703

Annex D Suggestions for Selecting Sample Size

The definition of sample sizes is a decision that should balance the costs of the experiment with the minimum level of
confidence necessary in the results of the test. With a larger
sample size comes better confidence in the results, but
obviously the test costs and time requirements rise accordingly.

bution model which has the broadest use in the industry to

calculate sample sizes. The following equation shows how
to estimate sample size:

During all phases of testing, multiple, similar products

should be subjected to each test environment. If every failure mechanism were present in every product, testing a
single unit would be sufficient to detect all defects. Unfortunately, because of component and manufacturing process
variability, every product is different from each other and
more than one sample must be tested to prove the performance of a product in the field. In real life applications,
some products will fail while others will not. The desired
confidence level to expose a failure mode in a product will
determine the number of products to test.

Where:
N = number of test specimens
ln = natural log
= 1 - confidence level
p+ = upper confidence limit or failure probability

Assuming that the failure mechanism is present in only a

small percentage of the units, testing with small sample
sizes is very risky. On the same lines, testing on product
with known performance problems will warrant larger
sample sizes than product proven to be defect free.

Based on the binomial distribution, a sample size of 22 is

necessary to achieve a 90% probability of detecting a
defect that occurs in 10% of the population. If you are
concerned with achieving very low defect densities, for
example 1% or less, the sample sizes become very large.
Table D-1 summarizes this calculation for some common
confidence levels and failures rates.

Assuming a normal distribution, a sample size of two produces only a 20% probability of detecting a defect that
occurs in 10% of the products. Testing even 10 units only
raises the probability to about 65%.
If the actual failure distribution of the product under test is
not known, a recommendation is to use a binomial distri-

N=

ln
ln (1 p+)

Example: How many units must be tested without failure to

demonstrate that the probability of failure is less than 0.1
(10%) with 90% confidence?
N=

ln (0.1)
2.30
ln (10.9)
N=
N=
N = 21.8 = 22
ln (10.1)
ln (0.9)
0.105

For a more complete introduction to this topic, the reader

is referred to a text on reliability engineering such as Introduction to Reliability Engineering, by E.E. Lewis, John
Wiley & Sons, Inc. ISBN: 0-471-01833-3.

27

IPC/JEDEC-9703

March 2009
Table D-1

Sample Size Estimate for a Single Failure Mechanism

Max Failure Rate

%

DPM

0.01

28

Confidence Level
25%

50%

60%

70%

80%

90%

95%

99%

100

2877

6931

9162

12039

16094

23025

29956

46049

0.05

500

575

1386

1832

2407

3218

4604

5990

9208

0.10

1000

288

693

916

1203

1609

2301

2994

4603

0.50

5000

57

138

183

240

321

459

598

919

10000

29

69

91

120

160

229

298

458

20000

14

34

45

60

80

114

148

228

30000

23

30

40

53

76

98

151

40000

17

22

29

39

56

73

113

50000

14

18

23

31

45

58

90

60000

11

15

19

26

37

48

74

70000

10

13

17

22

32

41

63

80000

11

14

19

28

36

55

90000

10

13

17

24

32

49

10

100000

11

15

22

28

44

15

150000

10

14

18

28

20

200000

10

13

21

25

250000

10

16

50

500000

75

750000

March 2009

IPC/JEDEC-9703

Annex E Suggestions for Finite Element Analysis in Mechanical Shock

E.1 Linear Dynamics A problem should have the follow-

ing characteristics for it to be suitable for linear transient

dynamic analysis:
The dynamic response of the system should be linear:
linear material behavior, no changing contact conditions,
and small displacement only.
The response should be dominated by relatively few frequencies if modal superposition is to be used. As the frequency content of the response increases, the modal
superposition technique becomes less effective.

(a) Mode 1: 31.1 Hz

The dominant loading frequencies should be in the range

of the extracted frequencies to ensure that the loads can
be described accurately.
The initial accelerations generated by any suddenly
applied loads should be described accurately by the
eigenmodes.

(b) Mode 6: 140 Hz

The system should not be heavily damped.

All mode-based, transient, linear dynamic calculations start
by extracting the natural frequencies of the system, and
these are then used as the basis of the linear dynamic solution. Nonlinear preloading effects can be accounted for in
linear dynamics, in that the stiffness used for the natural
frequency extraction can be the current stiffness after any
preload has been applied.

IPC-9703-E-1

Figure E-1

Coarse Mesh of Plate

plate is such that there is significant excitation of a mode,

a mesh refined sufficiently to model this mode must be
used; the results from a coarse mesh will not be accurate.

E.1.1 Natural Frequency Analysis

Element Selection: In general, the rules for selecting elements for linear dynamics are the same as those for static
simulations. Second-order elements should generally be
used unless there is a particular reason to use a different
element type.

(a) Mode 1: 30.2 HZ

Mesh Design for Dynamics: When designing meshes for

dynamic simulations, the user needs to consider the modes

that will be excited in the response and use a mesh that is
able to represent those mode shapes adequately. This
means that a mesh that is adequate for a static simulation
may be unsuitable for calculating the dynamic response to
loading that excites high frequency modes. Good practice
would be to run a mesh convergence study.
Consider, for example, the plate shown in Figure E-1. The
mesh of first-order shell elements is adequate for a static
analysis of the plate under a uniform load and is also suitable for the prediction of the first mode shape. However,
the mesh is clearly too coarse to be able to model the sixth
mode accurately.
Figure E-2 shows the same plate modeled with a more
refined mesh. The displaced shape for the sixth mode is
modeled more accurately, and the frequency predicted for
this mode is more accurate. If the dynamic loading on the

(b) Mode 6: 124 HZ

IPC-9703-E-2

Figure E-2

Fine Mesh of Plate

It is generally recommended that at least six to eight elements are used per wavelength of the highest frequency
mode to be modeled.
For linear dynamic analysis, care needs to be taken when
introducing symmetry into a model. A symmetric model
assumes that geometry, constraints, loads, and the response
29

IPC/JEDEC-9703

March 2009

will all be symmetric. The assumption of symmetry will

prevent the analysis from extracting non symmetric modes,
if they exist.

Exciter

The Test Board

For example, consider a plate with all edges simply supported. Table E-1 shows the first three modes extracted
from a full model, a half symmetric model and a half
asymmetric model. This clearly shows that modes are missing from the symmetric and asymmetric models.
The material response during a natural frequency extraction is linear. If nonlinear materials are
defined, then, the linearized elastic stiffness will be used. If
there is a preload, then the current, linearized elastic stiffness about the preloaded state of the materials should be
used.

Materials:

Boundary Conditions: Natural frequency extractions can

be performed on either an unconstrained or constrained
body. When the eigenmodes are to be used as the basis for
a transient modal dynamic solution, the boundary conditions for the natural frequency analysis should reflect those
needed for the dynamic analysis. Prescribed motion in the
transient dynamic analysis is applied using boundary conditions called base motions. All points that will either be
fixed or have a prescribed motion in the transient dynamic
analysis will need to be constrained in the natural frequency analysis. If different constraints are to be applied at
different points in the model, then multiple base motions
will have to be defined.

Force
Transducer

An Array of
Accelerometer
IPC-9703-E-3

Figure E-3

Rack Mounted Test Board

motion. So, two base motion sets will be required, one for
each constraint. These base motion sets are defined in the
eigenmode extraction step.

For example, if a test board is to be rack mounted into a

chassis and then have an excitation applied, as shown in
Figure E-3, both the edges of the board and the point of
excitation would be fixed for the natural frequency extraction.

For the primary base motion the constraints are applied

directly. This is not possible for secondary base motion;
instead, big masses with suitable accelerations are applied
(generally this process is automatic and internal to the
solver). There will be additional low frequency modes
associated with the big masses; one per degree of freedom.
So, the solver should automatically increase the number of
modes extracted to account for this and maintain the same
number of real modes, associated with the actual structure.

In the transient dynamic analysis, the edge of the board is

to be fixed, while the excitation point has a prescribed

Contact and Other Constraints: All constraints (such as

multi-point constraints and couplings) will be linearized for

Table E-1

30

Full, Symmetric, and Asymmetric Meshes of Plate

Full Model

Symmetric Model

Asymmetric Model

Mode 1: 13.18 Hz

Mode 1: 13.18 Hz

Mode 1: 17.41Hz

Mode 2: 17.41 Hz

Mode 2: 24.65 Hz

Mode 2: 34.89 Hz

Mode 3: 24.65 Hz

Mode 3: 47.75 Hz

Mode 3: 51.37 Hz

March 2009

IPC/JEDEC-9703

a natural frequency analysis. Any point that was in contact

before the natural frequency will remain in contact for the
duration of the linear analysis; similarly, any point that was
not in contact will remain open for the duration of the linear analysis.
Preloading: Some FE packages allow for the inclusion of
preloading effects, before the natural frequency extraction.
For many structures, assembly and active loading will
change the frequency content; the frequencies will vary
depending on the previous load history. Generally, structures under tension will stiffen, while structures under compression will soften.
Solver: Different solution methods exist for eigenmode
extraction; two such methods are subspace iteration and
Lanczos. Both of these techniques extract undamped eigenmodes. Complex eigenmode solvers are available which
will account for material damping, frictional contact, etc.
These are generally not required for linear dynamics analysis of shock for electronic components.

The Lanczos solver is better suited for larger models, or

when large numbers of modes are to be extracted. It also
has the advantage of being able to make use of the restart
technique such that additional modes can be extracted
without the need to repeat the extraction of the existing
modes. The subspace iteration method may be faster when
only a few eigenmodes (generally less than twenty) are
needed.
Typically, the number of eigenmodes to be extracted can be
specified directly, or a frequency range of interest can be
given. It is generally recommended to use the frequency
range method, as this then avoids any potential problem
with insufficient modes being calculated, when secondary
bases are used with their additional required modes.
Residual Modes: Some FE packages support the inclusion
of residual modes in the modal basis for linear dynamics
calculations. These are pseudo eigenmodes used to augment the true eigenmodes in a mode-based linear dynamics
analysis.

The static solution to a set of load cases (typically is the

excitation loading) forms the basis for the residual modes:
They minimize the number of eigenmodes necessary to
achieve a desired accuracy.
They are typically calculated based on excitation loading.
Typical application: Linear dynamic analyses where the
excitation loads have high frequency content; i.e., in order
to capture the loading behavior, a large number of eigenmodes would be required to obtain an accurate solution
without residual modes.
For example, consider the simplified model of a satellite
antenna shown in Figure E-4. This model is subjected to
various loadings.

IPC-9703-E-4

Figure E-4

Simplified Satellite Antenna Model

The results of a linear dynamic analysis on this model are

shown in Figure E-5. These show that 10 eigenmodes are
insufficient to accurately capture the dynamic response, but
10 eigenmodes and 1 residual mode give a much more
accurate solution and compares well with an analysis using
many more eigenmodes.
31

SF1 at Element 802 Int Point 1 in ELSET OUTEL

IPC/JEDEC-9703

March 2009

For the user, no special consideration needs to be made

when applying either loads or specifying initial conditions
for a modal dynamics analysis provided adequate eigenmodes ( and residual modes) are used. These quantities are
applied in the same way as for any other analysis type.
Prescribed motion is applied through base motions. The
location for these bases are defined in the natural frequency
analysis, as described above. The type, magnitude, and
form of the excitation are defined in the modal dynamic
analysis.

2.80
2.40
2.00
1.60
fiftyModes
tenAndResidualMode
tenModes

1.20
0.80
0.40
0.00
0.00

2.00

4.00
Time

Figure E-5

6.00

8.00
IPC-9703-E-5

Results for Simplified Satellite Antenna Model

Output: Results of interest from an eigenmode extraction

are the shapes of the extracted modes and their associated
frequencies. Other results that should be checked before
continuing to the transient modal dynamic analysis:
Modal Effective Mass: This reports how the total model
mass is distributed to the different directions represented by
a mode shape. For translational modes, the sum (over all
extracted modes) of the modal effective mass should be
close to the bodys total structural mass. If not, additional
modes are needed.
Modal Participation Factor: This indicates the predominant direction (degree of freedom) in which a mode acts.
This information can aid modal identification and help to
choose modes that will best represent the response to a
given loading. It is then possible to select specific eigenmodes to use as the basis for the modal dynamic solution.
E.1.2 Modal Dynamics From an analysis standpoint,
once the frequency extraction is complete, a transient
modal dynamic analysis is performed in a similar manner
to a nonlinear transient dynamic analysis, but it is computationally much faster. The user must ensure that the subset
of modes used as the basis of the solution is sufficient to
accurately represent the response of the structure as it is
loaded.

There are three possible forms of excitation

for modal dynamic problems:

Excitation:

Concentrated and/or distributed loads.

Initial displacement and/or velocity.
Base motion.
32

As previously stated, most natural frequency

solvers extract the modes based on the undamped system.
For small values of critical damping the eigenfrequencies
(and eigenvectors) of the damped system are very close to
the corresponding quantities for the undamped system
(fraction of critical damping, <0.1). As increases, the
undamped eigenfrequencies become less accurate; and as
approaches 1, the use of undamped eigenfrequencies
becomes invalid.

Damping:

In most linear dynamic problems the proper specification

of damping is important to obtain accurate results. However, damping is approximate in the sense that it models
the energy absorbing characteristics of the structure without attempting to model the physical mechanisms that
cause them. Therefore, it is difficult to determine the damping data required for a simulation. Data may be available
from dynamic tests, but often the user will have to work
with data obtained from references or experience. In such
cases, care should be taken in interpreting the results, and
parametric studies should be used to assess the sensitivity
of the simulation to damping values.
The transient modal dynamic procedure requires the user to specify the total time period for
the analysis and a fixed time increment. If the required time
increment is known, then the user can specify a frequency
cut-off for the eigenmode extraction; there is no point in
extracting modes whose period is substantially smaller than
the time increment used. Generally the time increment is
not known. It is more common for the user to extract sufficient eigenmodes to satisfy the modal effective mass
check described above. In this case the given time increment for the transient modal dynamic analysis must be
capable of resolving the highest frequencies of interest.

Time Incrementation:

Processing the output requests for a transient

modal dynamic analysis may be more expensive than
actual analysis. Analysis codes will generally, therefore,
save time by calculating output only for points where it is
requested. It is recommended to request only the necessary
output to reduce the cost of analysis.

Output:

Care needs to be taken when interpreting results from a

transient modal dynamic analysis; most results are given as
perturbations relative to the motion of the primary base.
The sum of the relative motion and the base motion yields

March 2009

IPC/JEDEC-9703

the total motion; separate variables giving this total motion

may also be available. In the absence of primary base
motions, the relative and total motions are identical.
E.2 Nonlinear Dynamics

A dynamics problem is consid-

ered nonlinear when:

The motion or deformation produced by the dynamic
behavior of the structure is large enough that we must
account for the changes in geometry.
Deformation large enough to change the stiffness of the
structure, thereby changing the natural frequency.
The problem involves nonlinear material response.
The problem involves contact.
It is not uncommon for a problem to contain all four
sources of nonlinearity.
A nonlinear dynamic analysis requires the time integration
of the full, coupled equations of motion. The superposition
of eigenmodes cannot be used and, therefore, a frequency
extraction analysis is not required. The loads and boundary
conditions on the structure may be arbitrary because no
projection onto the eigenmodes is necessary. Procedures
for solving nonlinear dynamic problems are much more
computationally intensive than those for linear dynamics.
The equations of motion can either be integrated implicitly
or explicitly. There are advantages and disadvantages to
both methods, and these are briefly listed in Table E-2.
The explicit approach is more suited to impact and shock
type applications, and so that will be the focus of this section.
Table E-2

E.2.1 Explicit Nonlinear Dynamic Analysis

Element Selection: For the explicit dynamic procedure we
need elements with lumped mass matrices. This requirement arises from the need to perform nodal calculations
that invert the mass. Generally this limits the element
selection to first-order elements. Another consideration is
the cost associated with the element calculations, as these
are often the most expensive part of the explicit dynamic
solution. The use of reduced-integration elements minimizes the cost of these calculations. So, for explicit dynamics, the user is typically limited to first-order, reducedintegration elements. Additional simplifications can be
made to further reduce the cost of element calculations
such as the use of small-strain formulation elements. The
user needs to check whether any such simplifications are
being used (they may be default options) and ensure that
they are appropriate for the analysis being performed.

Some FE packages allow the use of special formulation

second-order tetrahedral elements for explicit dynamics.
These elements offer the advantage of being robust for
large deformations and contact, while not demonstrating
shear or volumetric locking problems. They also have the
obvious advantage of allowing tetrahedral meshing to be
used.
For solid meshes the use of hexahedral elements is recommended when such meshing is possible and reasonable. If
mesh generation dictates that tetrahedral elements must be
used, then second-order tetrahedral elements are recommended. For example, many electronic components are

Comparing Implicit and Explicit Dynamic Solutions

Implicit dynamics

Explicit dynamics

The implicit procedure is unconditionally stable. The time

increment size is not limited by stability requirements; generally,
fewer time increments are required to complete a given simulation.

The explicit procedure is conditionally stable. The time increment size is limited by the stability of the algorithm; generally,
many more time increments are required to complete a given
simulation.

Each time increment is expensive since each requires the solution for a set of simultaneous equations.

Each time increment is relatively inexpensive because solving

a set of simultaneous equations is not required.

Iteration is required to meet convergence criteria. Iterations may No iterations or convergence criteria. Nonconvergence is not
not converge.
an issue. Since accuracy is not controlled by convergence,
care must be taken in the time integration algorithms.
Ideal for problems where the response period of interest is long
compared to the vibration frequency of the model, for example,
earthquake shock.
Slow, long time duration dynamics problems difficult to solve
effectively using explicit dynamics because of the limit on the
time increment size.

Ideal for high-speed dynamic simulations.

Require very small time increments; implicit dynamics inefficient
(especially for large models).

Use for problems that are mildly nonlinear and where the nonlinearities are smooth (e.g., plasticity).
With a smooth nonlinear response, implicit solution will need
very few iterations to find a converged solution.
In impact problems, implicit solution has to perform very expensive momentum transfer calculations for each impact.

Usually more reliable for problems involving discontinuous

nonlinearities.
Contact behavior is discontinuous and involves impacts, both
of which are difficult to solve using implicit time integration.
Other sources of discontinuous behavior include buckling and
material failure.

33

IPC/JEDEC-9703

housed in complex-shaped molded plastic parts, and these

are generally modeled with second-order tetrahedral elements. These elements offer reasonable accuracy, even with
a single element through the section and can save significant time in model generation. The use of first-order tetrahedral elements is not recommended; a very fine mesh
would be required to achieve reasonable accuracy.
For shell meshes the use of quadrilateral elements is recommended, with triangular elements being used where
mesh generation dictates. Continuum shell elements have
the topology of a hexahedral continuum element, but use a
shell-type formulation. These elements allow for accurate
modeling of bending with only a single element through
the thickness, and they have advantages over regular shell
elements in terms of contact modeling and visualization.
These elements are therefore ideal for thin components
whose main response is bending; for example, circuit
boards, ICs, LCDs, etc.
Hourglassing must be considered for any first-order,
reduced-integration element mesh. There are a variety of
hourglass suppression methods available and so the user
needs to understand the implication of the method being
used to ensure that accurate results are obtained. Some FE
packages also include options which can help to stop
elements turning inside out under extreme deformation.
These formulations are not physically motivated and are
really used to allow an analysis to progress when it would
ordinarily fail with element distortion problems. This can
be a useful option for soft materials under high compression, for example gaskets and seals.
For complex, system-level
models, good practice is to build the model up part by part,
or by sub-assemblies. It is much easier to debug a partlevel model than a full system-level model. Some FE packages allow models to be defined in terms of parts, instances
of parts, and assemblies. This approach fits well with the
methodology of building models up from parts and means
that assemblies of those parts can easily be added to.
Mesh Design for Dynamics:

Mesh design for nonlinear dynamics is similar to that for

linear dynamic simulations, in that the user needs to consider the modes that will be excited in the response and use
a mesh that is able to represent those mode shapes
adequately.
For explicit dynamics an additional consideration is the
element sizes. For a mesh made up of a homogeneous
material, the smallest element in the model will determine
the stable time increment and, the smaller the element, the
smaller the time increment. So, the user needs to try to balance the element size required for an accurate solution with
the element size required for a reasonable runtime. The use
of small elements where not specifically required should be
avoided.
34

March 2009

Mass scaling can be used to artificially increase the stable

time increment for a given element. Some FE packages
offer semi-automatic mass scaling, whereby only the
masses of elements whose stable time increment is below
some criteria will be scaled, and that scaling can be
repeated periodically during the solution to account for
large deformations of the elements. If accurate surface
stresses are required from a solid mesh, skins of membrane
elements can be used. These elements can be used at strain
gage locations to give the necessary output.
Materials: Most FE packages contain constitutive models
for all materials commonly found in electronics components and assemblies: metal, plastic, rubber, foam, glass,
etc. These materials may require direct specification of
parameters or they may accept test data with which the FE
code will perform the parameter evaluation.

For a nonlinear analysis, many of the available material

models can be made strain-rate dependant, but obtaining
the necessary test data may be difficult.
Material properties may vary with direction, and so orthotropic or fully anisotropic material models may be
required. If this is the case, the user needs to take care
when specifying the local directions for the material properties.
Damping is another factor that could affect analysis, but for
which test data may be difficult to acquire. It may be
possible to use damping to tune the response of a model to
match test data. The resulting damping values could then
be used in other similar analyses.
Some FE packages contain progressive failure models that
can be used to model ductile or brittle failure of materials.
Application areas for this type of material model might be
in detailed solder joint failure models, or LCD failure in a
system-level analysis.
Contact: Contact definition depends on the FE package
being used; it may be necessary to define individual surfaces, and then identify which of those can interact, or an
automatic general contact algorithm may be available.
General contact obviously makes the model generation
very much simpler.

There are a number of different methods available for

enforcing contact constraints. Two of the more common are
the kinematic and penalty methods:
Kinematic enforcement of contact is done by calculating
corrections to accelerations, distributing masses and forces
associated with contacting nodes on to opposing surfaces,
such that no penetration occurs. The advantage of this
method is that the contact condition is exact; no penetration
occurs. The disadvantage of this method is the potential for
conflicts with other constraints in the model, and certain
contact types (for example rigid-rigid) cannot be modeled.

March 2009

Penalty enforcement is done by applying resisting forces to

nodes that have been penetrated. This method allows for
more general contact cases, for example contact between
rigid bodies. Also, this method is less likely to result in
problems when contact nodes are common to other types of
constraint. The disadvantage of this method is that small
penetrations may occur and so the contact condition is not
enforced precisely. If possible, using general automatic
contact with the penalty enforcement method would be the
recommended approach, unless there is good reason to use
an alternative.
Initial overclosures can cause problems with the analysis.
These overclosures may be caused by inaccurate geometry,
or by geometric simplifications and assumptions made for
the analysis. For example, if a small fillet is removed for
the analysis, parts may overlap. Most FE packages will
attempt to resolve any initial overclosures and some offer
tools for the user to manually make these adjustments. The
user should be aware of this potential problem and it is
something that should be checked.
Constraints: Various types of constraint are available for
either modeling joints and interfaces, or just bonding
regions of mesh together. Tie constraints can be used to
join incompatible meshes. In this way, they can also be
used for very simple representations of package interconnects, in that the package mesh can be tied to the circuit
board mesh. This type of constraint is rigid, but some FE
packages may allow the joint to fail.

Some FE packages have spot weld representation, which

are mesh independent constraints that can either behave
rigidly or have material properties associated with them.
The latter option allows for elastic, plastic, and/or failure
response in the joint. These connection types can be used
to represent solder joints and allow for quite complex physics to be modeled using a very simple joint representation.
Boundary Conditions: Most shock tests involve some
amount of free-fall of the part under test, before impact.
There is no need to model this rigid body motion in the
finite element model. Rather, the test part should be modeled in the position just prior to impact and be given the
correct initial velocity to account for the free-fall.
Preloading: Most system-level components include some
type of preloading - snap fit of plastic joints, compression
of gaskets and seals, tightening of bolts or screws, compression of electrical connections, etc. It is not generally
efficient to model these types of preloading operations with
the explicit dynamic method. The preloads are really quasistatic operations which would therefore be required to run
for a long time period, making them computationally
expensive given the small stable time increment required
when using explicit dynamics.

Some FE packages also have implicit solvers which are

compatible with their explicit solver that allow for the

IPC/JEDEC-9703

transfer of data between these solvers. This makes it possible to model the preloading operations with an implicit
solution method, and then import the deformed shape and
associated stresses into the explicit dynamic solution as the
start point for the shock test.
The user generally has the choice of precision
level for the explicit dynamic solver. A double-precision
solution is normally preferred for shock and impact type
load cases. Most FE packages allow the use of parallel
execution and may allow for the use of both shared- and
distributed-memory machines. Depending on model size,
runtime requirements, and available hardware, this option
should be explored.

Analysis:

Output: Typical results of interest from a nonlinear

explicit dynamic shock analysis include the deformed
shape and animations of the same. This allows for an
assessment of which parts come into contact during the
analysis. If high speed video footage of a physical test is
available, then some FE packages allow that video to be
synchronized with the animation from the analysis to allow
for simple side-by-side or overlay comparison.

Stresses and strains in critical components. This allows for

an assessment of whether material yielding or failure may
occur.
Interface or joint loads and stresses. This allows for an
assessment of whether joints or bonds might break. If failure models are included in the analysis, then, parts can
physically separate during the analysis. In this case, failure
could be detected by looking at the deformed shape.
Care needs to be taken when requesting results from an
explicit dynamic analysis. In the absence of runtime filters,
data for xy-plots should be written every increment to
avoid decimation and aliasing of the data. An explicit
dynamic analysis can take tens of thousands to millions of
increments to complete, and writing results every increment will generate an extremely large output file. Most
post-processors have filtering tools to reduce the noise in
an xy trace but, for the results to be truly valid, these filters
need a full set of raw data to operate on. Some FE packages have runtime filters built into the analysis itself. This
means that the analysis code will temporarily store results,
filter it, and then write the filtered data to the output file.
This drastically reduces the amount of information that
needs to be stored.
E.3 Model Validation Techniques

Reality has a lot of challenges for modeling,

such as nonlinearity, uncertainty, variability and complexity. Modeling simulation is limited by engineering knowledge, understanding of physics and limited resources
(trained analysts, computers, software etc.). The growing
need for virtual prototyping is demanding smarter (not

Introduction:

35

IPC/JEDEC-9703

bigger) models that are adequate for its intended purpose

with the required level of accuracy for all necessary features. This requires model validation.
In this section we will suggest some commonly used model
validation methods both in frequency and time domains.
The modal method has been applied to dynamic FE analysis for electronic boards. Modal test and analysis is an
important and effective step in model validation. However,
we believe there are two concerns if model validation is
stopped here. First, the mode shapes and the frequencies
are global measurements and may not account for localized
board deflection or bending which is directly related to the
solder joint stress state. Secondly, modal tests are normally
conducted at a very low excitation input which may not
provide an accurate simulation for large inputs like a shock
event. To address these concerns, a shock simulation model
should be rechecked using time domain measurements.
Direct integration analysis has the advantage in handling
nonlinearity thanks to the FEA software capability and the
growing workstations computing power. The direct integration method solely relies on comparing model simulation with direct board response measurements in the time
domain to validate the model.
Acceleration responses may be used for comparing in the
time domain, between model simulation and empirical
measured board level acceleration measurements. However, as revealed in Section 8, using acceleration alone to
validate a model can lead to incorrect load states of solder
joints, impacting reliability assessment. Thus using either
modal or direct integration analyses, one should additionally obtain a direct measurement of the board deflection
and/or board strain to provide an accurate validation of a
model.
E.3.1 Modal Validation Two sets of data in frequency

domain are available for a modal model validation. One set

is global parameters: natural frequency, mode shape and
damping ratio corresponding to each mode. Another set of
data is FRF (Frequency Response Function) at each measuring point. FRF has more data available without errors
induced in extracting modal parameters and better for high
modal density cases. However, validation by using modal
parameters is more efficient thus is most commonly used.
The following are suggested steps in using modal parameters to update models. Consult the literature for more on
other approaches.
Step 1:

Pretest analysis

Before a modal test, use the finite element model (FEM) to

help determine the locations for sensors and excitations to
avoid mode aliasing and help determine how many and
which modes should be captured. Pretest analysis is recommended to reduce the test effort and the validation effort.

36

March 2009
Step 2:

Correlate measurement points and FEM nodes

Normally the degrees of freedom in FE model are much

higher than the number of test measuring points. Mode
shape truncation in the FE model is recommended since it
is more conservative than mode shape expansion in the test
model.
Step 3:

Compare the natural frequencies

Step 4:

Visual comparison of mode shapes

Step 5:

Correlate mode shapes

The modes may not be in the same order or in the same

numbers between FEM and a modal test. Mode shapes paring is required before computing Modal Assurance Criterion (MAC).
Step 6:

Compute MAC

Mode shape validation can be done not only by visualization through animation, but more importantly by computing the MAC, which is a correlation coefficient between the
two mode shapes in Eq. (E-1) for real (normal) modes or
Eq. (E-2) for complex modes. If the MAC coefficient is
equal to 1.0, then the two shapes are perfectly correlated.
For real (or normal) modes:
MACjk =

T
2
mj ak
(akT ak)(mjT mj)

(E-1)

ak - kth eigenvector from analytical model

mj - jth eigenvector from measurement
For complex modes:
MACjk =

H
2
mj ak
H
H
(ak
ak)(mj
mj)

(E-2)

where superscript H is Hermitian transpose, [A]H = ([A]T)*,

*denotes the complex conjugate.
The computing results are in a matrix. The ideal MAC
matrix is an identity matrix where the coefficients on the
diagonal are 100% and all off the diagonal are 0%. Model
updating is required to improve MAC, increasing the
diagonal and reducing those off the diagonal. Double check
the mode pairs and recomputed MAC before updating the
model.
The equations can also be used for checking the test data
or FEA data to confirm the validity of the data. All modes
should be orthogonal to each other.
Local mode shape correlation can be computed by using
Mode Shape Difference (MSD):
MSD = {a m}
Model updating is required to minimize the differences.

March 2009

IPC/JEDEC-9703

An overlay plot is commonly used for time history comparison. Figure E-6 shows a comparison of the displacement from the model and captured by using the high speed
camera system. Further confirmation was gained by comparing the board strains derived from the model with measurements using strain gages as shown in Figure E-7. As
can be seen from these figures the model captures the
behavior very well.
E3.3 Field Comparison (Contour Plots) Displacement or
strain contour plots have been useful for comparing
between the simulation and the empirical measurements.
When doing so, make sure not only the frame of references
is matched, but also the measuring target grid density is
enough to derive accurate board displacement or strain
contour map. Similar to mode shape correlation, displacement shape (map) at a specified time can be validated by
applying the Displacement Assurance Criterion (DAC):

DAC(Ua ,Um) =

?U

T
2
m Ua
(UaT Ua)(UmT Um)

Displacement (normalized)

When comparing the empirical measurements, make sure

the frame of reference for the measurement is the same as
that in the model. Board acceleration measurement from an
accelerometer is referenced to the earth. Board displacement can be measured relative to the shock table when the
reference is fixed on the table. If the board is mounted on
a rigid fixture, the displacement measured can be the board
deflection. If the board is mounted in a chassis, the board
deflection and the chassis deformation are coupled in the
measurement. Board strain measurements are referenced to
the existing board local flatness at the time zero before taking measurement. Thus board strain measurement can be
freely applied to compare across board level or system
level of shock tests.

1.0
Experiment
FE Model

0.5
0.0
-0.5
-1.0

0.01

0.02

0.03

0.04

Time (seconds)

0.05
IPC-9703-E-6

Figure E-6 Comparison of Displacement-Time History for

Experimental Data and FEA Result

Principal Strain (normalized)

E3.2 Time History Validation No matter which method

is used for FE modeling, a typical shock FE model validation will compare board response time history measured
across the board. The length of the time history should be
long enough to show the dynamic event and the validation
should be across the board. Peak value only or single point
comparison is not sufficient to validate a circuit board FE
model.

1.0
Experiment
FE Model

0.5
0.0
-0.5
-1.0
0

0.01

0.02

0.03

Time (seconds)

0.04

0.05
IPC-9703-E-7

Figure E-7 Comparison of Board Strain versus Time

History for Experimental Data and FEA Result

Where:
Ua Displacement from analytical model
Um Displacement from measurement
The ideal DAC is 1.0, when two displacement shapes are
perfectly matched.
Local correlation can be computed by using Displacement
Shape Difference (DSD):
DSD (Ua ,Um) = {Ua Um}
Model updating is required to minimize the differences.

37

ANSI/IPC-T-50 Terms and Definitions for

Interconnecting and Packaging Electronic Circuits
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