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APT56M50L
500V, 56A, 0.10 Max
N-Channel MOSFET
Power MOS 8 is a high speed, high voltage N-channel switch-mode power
MOSFET. A proprietary planar stripe design yields excellent reliability and manufacturability. Low switching loss is achieved with low input capacitance and ultra
low Crss "Miller" capacitance. The intrinsic gate resistance and capacitance of
the poly-silicon gate structure help control slew rates during switching, resulting
in low EMI and reliable paralleling, even when switching at very high frequency.
Reliability in flyback, boost, forward, and other circuits is enhanced by the high
avalanche energy capability.
T-Ma x TM
TO-264
APT56M50B2
APT56M50L
D
G
S
TYPICAL APPLICATIONS
FEATURES
Fast switching with low EMI/RFI
Low RDS(on)
Buck converter
Flyback
RoHS compliant
Inverters
Parameter
Unit
Ratings
56
35
IDM
VGS
Gate-Source Voltage
30
EAS
1200
mJ
IAR
28
175
Unit
W
PD
780
RJC
0.16
RCS
TJ,TSTG
TL
WT
Package Weight
Torque
0.11
-55
150
300
C/W
0.22
oz
6.2
g
10
inlbf
1.1
Nm
8-2011
Typ
Rev C
Min
Characteristic
050-8073
Symbol
Static Characteristics
Symbol
Parameter
Test Conditions
Min
VBR(DSS)
500
VBR(DSS)/TJ
Drain-Source On Resistance
VGS(th)
VGS(th)/TJ
IGSS
Dynamic Characteristics
Forward Transconductance
Ciss
Input Capacitance
Crss
Coss
Output Capacitance
VDS = 500V
TJ = 25C
VGS = 0V
TJ = 125C
Typ
Max
0.60
0.085
4
-10
0.10
5
100
500
100
VGS = 30V
Unit
V
V/C
V
mV/C
A
nA
Parameter
gfs
IDSS
Symbol
RDS(on)
APT56M50B2_L
Min
Test Conditions
VDS = 50V, ID = 28A
Co(er)
Max
43
8800
120
945
Co(cr)
Typ
Unit
S
pF
550
VGS = 0V, VDS = 0V to 333V
Qg
Qgs
Gate-Source Charge
Qgd
Gate-Drain Charge
td(on)
tr
td(off)
tf
275
220
50
100
38
45
100
33
nC
ns
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 1
Test Conditions
MOSFET symbol
showing the
integral reverse p-n
junction diode
(body diode)
trr
ISD = 28A 3
Qrr
Typ
Max
Unit
56
A
VSD
dv/dt
Min
D
175
1
660
13.2
V
ns
C
V/ns
1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature.
2 Starting at TJ = 25C, L = 3.06mH, RG = 4.7, IAS = 28A.
050-8073
Rev C
8-2011
3 Pulse test: Pulse Width < 380s, duty cycle < 2%.
4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS.
5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any
value of
VDS less than V(BR)DSS, use this equation: Co(er) = -2.04E-7/VDS^2 + 4.76E-8/VDS + 1.36E-10.
6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452)
Microsemi reserves the right to change, without notice, the specifications and information contained herein.
APT56M50B2_L
200
GS
100
= 10V
T = 125C
TJ = -55C
90
TJ = 25C
80
40
TJ = 150C
TJ = 125C
60
50
40
30
20
5V
10
4.5V
0
5
10
15
20
25
VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V)
6V
70
175
NORMALIZED TO
VGS = 10V @ 28A
1.5
1.0
0.5
125
TJ = -55C
100
TJ = 25C
75
TJ = 125C
50
25
0
0
-55 -25
0
25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Figure 3, RDS(ON) vs Junction Temperature
2
4
6
8
10
VGS, GATE-TO-SOURCE VOLTAGE (V)
Figure 4, Transfer Characteristics
20,000
60
C, CAPACITANCE (pF)
TJ = 25C
50
Ciss
10,000
TJ = -55C
TJ = 125C
40
30
20
1000
Coss
100
Crss
10
16
10
20
30
40
ID, DRAIN CURRENT (A)
Figure 5, Gain vs Drain Current
100
200
300
400
500
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 6, Capacitance vs Drain-to-Source Voltage
12
VDS = 100V
10
VDS = 250V
8
6
VDS = 400V
4
2
0
175
ID = 28A
14
10
50
150
125
100
TJ = 25C
75
TJ = 150C
50
25
0
0.2 0.4
0.6 0.8
1.0 1.2 1.4
VSD, SOURCE-TO-DRAIN VOLTAGE (V)
Figure 8, Reverse Drain Current vs Source-to-Drain Voltage
8-2011
Rev C
gfs, TRANSCONDUCTANCE
2.0
70
150
ID, DRAIN CURRENT (A)
2.5
5
10
15
20
25
30
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
050-8073
120
GS
80
160
APT56M50B2_L
250
250
100
100
IDM
IDM
13s
10
100s
1ms
Rds(on)
10ms
100ms
DC line
1
TJ = 125C
TC = 75C
0.1
13s
1ms
10ms
Rds(on)
100ms
DC line
TJ = 150C
TC = 25C
0.1
10
100
600
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 9, Forward Safe Operating Area
100s
10
10
100
600
VDS, DRAIN-TO-SOURCE VOLTAGE (V)
Figure 10, Maximum Forward Safe Operating Area
0.16
D = 0.9
0.14
0.7
0.12
0.10
0.5
Note:
0.08
P DM
0.18
0.3
0.06
t2
SINGLE PULSE
0.1
0.05
0.04
t1 = Pulse Duration
t
0.02
0
10-5
t1
10-4
10-3
10-2
10-1
RECTANGULAR PULSE DURATION (seconds)
Figure 11. Maximum Effective Transient Thermal Impedance Junction-to-Case vs Pulse Duration
1.0
4.60 (.181)
5.21 (.205)
1.80 (.071)
2.01 (.079)
15.49 (.610)
16.26 (.640)
19.51 (.768)
20.50 (.807)
3.10 (.122)
3.48 (.137)
5.38 (.212)
6.20 (.244)
5.79 (.228)
6.20 (.244)
Drai n
Drai n
20.80 (.819)
21.46 (.845)
8-2011
25.48 (1.003)
26.49 (1.043)
2.87 (.113)
3.12 (.123)
2.29 (.090)
2.69 (.106)
1.65 (.065)
2.13 (.084)
19.81 (.780)
20.32 (.800)
1.01 (.040)
1.40 (.055)
19.81 (.780)
21.39 (.842)
Gate
Drai n
050-8073
Rev C
Source
2.21 (.087)
2.59 (.102)
These dimensions are equal to the TO-247 without the mounting hole.
Dimensions in Millimeters (Inches)
0.48 (.019)
0.84 (.033)
2.59 (.102)
3.00 (.118)
0.76 (.030)
1.30 (.051)
2.79 (.110)
3.18 (.125)
5.45 (.215) BSC
2-Plcs.
2.29 (.090)
2.69 (.106)
Gate
Drai n
Source