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Clock Tree Synthesis

Clock Tree Synthesis is a process which makes sure that the clock gets distributed
evenlytoallsequentialelementsinadesign.
ThegoalofCTSistominimizetheskewandlatency.
TheplacementdatawillbegivenasinputforCTS,alongwiththeclocktreeconstraints.
The clock tree constraints will be Latency, Skew, Maximum transition, Maximum
capacitance,Maximumfanout,listofbuffersandinvertersetc.
Theclocktreesynthesiscontainsclocktreebuildingandclocktreebalancing.
Clock tree can be build by clock tree inverters so as to maintain the exact transition
(duty cycle) and clock tree balancing is done by clock tree buffers (CTB) to meet the
skewandlatencyrequirements.
Less clock tree inverters and buffers should be used to meet the area and power
constraints.
Therecanbeseveralstructureforclocktree:
HTree
XTree
Multilevelclocktree
Fishbone
OncetheCTSisdonethanwehavetoagaincheckthetiming.
The outputs of clock tree synthesis are Design Exchange Format (DEF), Standard
ParasiticExchangeFormat(SPEF),andNetlistetc.

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NOTES:
Thenormalinvertersandbuffersarenotusedforbuildingandbalancingbecause, the
clockbuffersprovidesabetterslewandbetterdrivecapabilitywhencomparedtonormal
buffersandclockinvertersprovidesabetterbalancewithriseandfalltimesandhence
maintainingthe50%dutycycle.
EffectsofCTS:Manyclockbuffersareadded,congestionmayincrease,crosstalknoise,
crosstalkdelayetc.
Clocktree optimizations: It is achieved by buffer sizing, gate sizing, HFN synthesis,
Bufferrelocation.
SetUpFixing:

i. Upsizingthecells(increasethedrivestrength)indatapath.
ii. Pullthelaunchclock
iii. Pushthecaptureclock
iv. Wecanreducethebuffersfromdatapath.

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VLSIBasic:ClockTreeSynthesis
v. Wecanreplacebufferswithtwoinvertersplacingfartherapartsothatdelaycanadjust.
vi. Wecanalsoreducesomelargerthannormalcapacitanceonacelloutputpin.
vii. Wecanupsizethecellstodecreasethedelaythroughthecell.
viii. LVTcells

HoldFixing:
Itiswellunderstoodholdtimewillbelargeifdatapathhasmoredelay.Sowehavetoaddmore
delaysindatapath.

i. Downsizingthecells(decreasethedrivestrength)indatapath.
ii. Pullingthecaptureclock.
iii. Pushedthelaunchclock.
iv. Byaddingbuffers/Inverterpairs/delaycellstothedatapath.
v. Decreasingthesizeofcertaincellsinthedatapath,Itisbettertoreducethecellsn capture
pathclosertothecaptureflipflopbecausethereislesschanceofaffectingotherpathsand
causingnewerrors.
vi. Byincreasingthewireloadmodel,wecanalsofixtheholdviolation.
Transitionviolation
In some cases, signal takes too long transiting from one logic level to another, than a transition
violationiscaused.TheTransviolationcanbebecauseofnoderesistanceandcapacitance.

i. Byupsizingthedrivercell.
ii. Decreasingthenetlengthbymovingcellsnearer(or)reducinglongroutednet.
iii. ByaddingBuffers.
iv. By increase the width of the route at the violation instance pin. This will decrease the
resistanceoftherouteandfixthetransitionviolation.
Capviolation
Thecapacitanceonanodeisacombinationofthefanoutoftheoutputpinandcapacitanceofthe
net. This check ensures that the device does not drive more capacitance than the device is
characterizedfor.

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i. Theviolationcanberemovedbyincreasingthedrivestrengthofthecell.
Bybufferingthesomeofthefanoutpathstoreducethecapacitanceseenbytheoutputpin.

Posted by Jitu Mistry at 21:37

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3 comments

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Top comments

kishor chavda 8 months ago - Shared publicly

hello
jitu. i have one question.
why hold time xed after the CTS? Only Setup time taken care into
account before CTS why not hold time ?
+1
2

1 Reply

Jitu Mistry 4 months ago

Hi Kishor,
at Pre-cts stage, clock is still ideal and net route is remaining, so
hold violations estimation is not exact.

Jeba Seelan 1 year ago - Shared publicly

very well explained :)
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