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TI Home > Semiconductors > Amplifiers > Operational Amplifiers (Op Amps) > General-Purpose Op
Amps >

TL081 (ACTIVE)
JFET-Input Operational Amplifier
TL08xx JFET-Input Operational Amplifiers (Rev. I)

In English

Description & parametrics

Online datasheet

Technical documents
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Description
Features
Parametrics
Diagrams
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Description
The TL08xx JFET-input operational amplifier family is designed to offer a wider selection than any
previously developed operational amplifier family. Each of these JFET-input operational amplifiers
incorporates well-matched, high-voltage JFET and bipolar transistors in a monolithic integrated
circuit. The devices feature high slew rates, low input bias and offset currents, and low offset-voltage
temperature coefficient.

Features

Low Power Consumption: 1.4 mA/ch Typical

Wide Common-Mode and Differential Voltage
Ranges

Low Input Bias Current: 30 pA Typical

Low Input Offset Current: 5 pA Typical

Output Short-Circuit Protection

Low Total Harmonic Distortion: 0.003% Typical

High Input Impedance: JFET Input Stage

Latch-Up-Free Operation

High Slew Rate: 13 V/s Typical

Common-Mode Input Voltage Range

Includes VCC+
View more

Parametrics Compare all products in General-Purpose Op Amps

Number of Channels (#)

Total Supply Voltage (Min) (+5V=5, +/5V=10)

Total Supply Voltage (Max) (+5V=5, +/5V=10)
GBW (Typ) (MHz)
Slew Rate (Typ) (V/us)
Rail-to-Rail
Vos (Offset Voltage @ 25C) (Max) (mV)
Iq per channel (Typ) (mA)
Vn at 1kHz (Typ) (nV/rtHz)
Rating
Operating Temperature Range (C)
Package Group
Approx. Price (US$)
Package Size: mm2=WxL (PKG)
(mm2=WxL)
Offset Drift (Typ) (uV/C)
Additional Features
IIB (Max) (pA)

CMRR (Typ) (dB)

Output Current (Typ) (mA)
Architecture

T
L
0
8
2
Q
1

T
L
0
8
2
A

TL
08
1

TL
08
1A

T
L
TL
0
08
8
2
1
B

T
L
TL
0
08
8
4
2
B

T
L
0
8
4
A

T
L
0
8
4
B

1 2

2 2 4

4 4

7 7

7 7 7

7 7

36

36

3 36
6

3
6

3 3 36
6 6

3 3
6 6

3 3

3 3 3

3 3

13

13

1 13
3

1
3

1 1 13
3 3

1 1
3 3

In
to
V+

In
to
V+

I In
n to
V+
t
o

In
to
V
+

V
+

I I In
n n to
V+
t t
o o

I I
n n

V V
+ +

V V
+ +

t t
o o

3 6

6 3 6

6 3

1.4

1.4

1 1.4
.
4

1.
4

1 1 1.4
. .
4 4

1 1
. .
4 4

18

18

1 18
8

1
8

1 1 18
8 8

1 1
8 8

Ca
tal
og

Ca
tal
og

C Ca
a tal
t og
a
l
o
g

A
ut
o
m
ot
iv
e

C
a
t
a
l
o
g

C
a
t
a
l
o
g

40

0
to

0 40

0 0 40

C Ca
a tal
t og
a
l
o
g

C
a
t
a
l
o
g

0 0

to
85
0
to
70

70

PD
IP
S
O
S
OI
C

PD
IP
SO
IC

0.1
2|
1k
u

0.2
6|
1k
u

t to
o 85
0
7 to
0 70

0
to
1
2
5
4
0
to
8
5

t t to
o o 12
5
7 7 0 0 40
to
85
0
to
70

t t
o o

P
D
I
P

PD
IP
S
O
S
S OI
O C
I TS
C S
O
P

S
O
I
C

P
D
I
P

PD
IP
S
O
S
S S OI
O O C
I TS
S C S
O
O
I
P
C

P
D
I
P

0
.
2
9

0.
2
1
|
1
k
u

0
.
2
4

0
.
3
7

0
.
2
6

0
.
3
8

|
1
k
u

|
1
k
u

|
1
k
u

|
1
k
u

8
S
O

S S Se
e e e
e e dat

0.1
9|
1k
u

|
1
k
u

Se
e
dat

Se
e
dat

S Se
e e
e dat

P
D
I
P

0.1
3|
1k
u

7 7
0 0

P
D
I
P

S S
O O
I
S C
O
I
C

S S
e e
e e

as
he
et
(C
DI
P),
Se
e
dat
as
he
et
(P
DI
P)

as
he
et
(C
DI
P),
Se
e
dat
as
he
et
(P
DI
P)

as
he
et
(C
DI
P),
Se
e
dat
as
he
et
(P
DI
P)

I
C
:
2
9
m
m
2:
6
x
4.
9
(
S
O
I
C
)

18

18

1 18
8

1
8

1 1 18
8 8

1 1
8 8

Vo
s
Ad
j
Pi
n

Vo
s
Adj
Pin

V N/
o A
s

N
/
A

N N N/
/ / A
A A

N N
/ /
A A

d
a
t
a
s
h
e
e
t
(
P
D
I
P
)

A
d
j
P
i
n

d
a
t
a
s
h
e
e
t
(
P
D
I
P
)

d
a
t
a
s
h
e
e
t
(
P
D
I
P
)

as
he
et
(C
DI
P),
Se
e
dat
as
he
et
(P
DI
P)

d
a
t
a
s
h
e
e
t
(
P
D
I
P
)

d
a
t
a
s
h
e
e
t
(
P
D
I
P
)

20
0

20
0

2 20
0 0
0

2
0
0

2 2 20
0 0 0
0 0

2 2
0 0
0 0

86

86

8 86
6

8
6

8 8 86
6 6

8 8
6 6

10

10

1 10
0

1
0

1 1 10
0 0

1 1
0 0

FE
T

FE
T

F FE
E T
T

F
E
T

F F FE
E E T
T T

F F
E E
T T

Sa
mp
le
&
Bu
y

Sa
mp
le
&
Bu
y

S
a
m
p
l
e
s

S
a
m
pl
e
&
B
u
y

S
a
m
p
l
e

S
a
m
p
l
e

N
o
t
A
v
a
il
a
b
l
e

Sa
mp
le
&
Bu
y

S
a
m
p
l
e

Sa
mp
le
&
Bu
y

S
a
m
p
l
e

& &

& &

B B
u u
y y

B B
u u
y y

Diagrams (1)

Functional Diagram

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All trademarks are the property of their respective owners.

Featured tools and software

TL081, TL081A, TL081B PSpice Model (Simulation Models)

Universal Operational Amplifier Evaluation Module (Evaluation Modules & Boards)

View All tools and software for TL081

WEBENCH Designer TL081

Amplifier Topology
Noninverting

Inverti
ng

Desired Power Supply Voltage

V

Positive Supply (Vcc):

15.0

Negative Supply (Vee):

-15.0

Allowed Power Supply(Vcc-Vee) = 10.0 to

36.0 V
Desired Input and Output
Requirements
Min

Max
V

Vin

-4.0

Vout

-8.0

V
4.0

V
8.0

Minimum Temperature = 0.0 C

Maximum Temperature = 70.0 C
Open Design
What are WEBENCH tools?

Companion products
Part
number

Name

SN74HC11
2

Dual J-K

Negative-Edge-

Datasheet

Download (

Additional
informatio
n

Why are these

companion
products?

Technical

Customers who
designed with

Part
number

OPA551

Name

Datasheet

Additional
informatio
n

Why are these

companion
products?

Triggered FlipFlops With Clear

and Preset

604KB)

Documents

TL081 also
designed
with SN74HC11
2

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High-Current
Operational
Amplifiers

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1185KB)

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Input ExclusiveOR Gates

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ADS1247

Low Noise,

Precision 24-Bit
Analog-to-Digital
Converter

OPA2340

Single-Supply,
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M) Series

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Technical
Documents
Tools &
Software

Customers who
designed with
TL081 also
designed
with OPA551

Technical
Documents

Customers who
designed with
TL081 also
designed
with SN74HC86

Technical
Documents

Customers who
designed with
TL081 also
designed
with ADS1247

Tools &
Software
Technical
Documents
Tools &
Software

Customers who
designed with
TL081 also
designed
with OPA2340

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