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Hardware
OS 9600
OS 9700
OS 9800
CMM & NIs
System architecture
OS 6850
OS 6200
Aggregation LAN
Access LAN
Core LAN
OmniStack LS 6200
OmniAccess
WLAN
OmniSwitch 6850
WAN/MAN
ESS/SR
7450/7750
OmniSwitch 7000
OmniSwitch 9000
OmniAccess 700
VitalSuite
High
Ava ila bility
Brick
Opera ting
System
Extensive
Ma na gea bility
VitalQIP
Enha nced
Security
OA SafeGuard
OmniSwitch
Range
18 slot chassis (16 NI slots)
Back-plane architecture
Fan trays (hot swappable)
OS9800
2 CMMs (hot swappable)
x management
x switching fabric
OS9700
3/4 PSUs (hot swappable)
x N+1 redundancy
x 110/220V input (AC)
x 48V input (DC)
OS9600
OS6850
OmniSwitch 9600
5 Slot Chassis
4 slots for NIs
Control
Switching Fabric
Backplane capacity
960 Gbps
Hardware specifications
L2: 16K hosts 4K VLANs
L3:
OmniSwitch 9700
10 Slot Chassis
8 slots for NIs
Backplane capacity
960 Gbps
Switch Fabric Performance
24/48 Gbps per slot with 1/2 CMM
installed
Hardware specifications
L2: 16K hosts 4K VLANs
L3: 8K hosts (IPv4) 4K interfaces 12K
LPM (IPv4)
ACL: 2K network policies for L1/L2/L3/L4
classification
QoS: 8 priorities, 2K policers, egress
shaping
OmniSwitch 9800
18 Slots Chassis
2 slots for OS9800-CMM mgt. modules
Backplane capacity
1.92 Tbps
Switch Fabric Performance
24/48 Gbps per slot with 1/2 CMM
installed
Hardware specifications
L2: 16K hosts 4K VLANs
L3:
System Architecture
Fabric Load Sharing
Principle of operation for Fabric Load Sharing
Traffic intra-module is processed & forwarded locally
Traffic inter-module is forwarded through the Virtual Switching Fabric
NI-1
NI-8
Fwd
eng
NI-1
Fwd
eng
NI-5
CFM
NI-2
CMM-A
Fwd
eng
Fwd
eng
NI-6
Fwd
eng
NI-3
CFM
NI-7
CMM-B
Fwd
eng
NI-4
Fwd
eng
NI-8
Port Trunk
RAM
CPU
PHY
Fabric
CMM-A
FBUS+
Prim.
CMM
PHY
Standard
Fwd Engine
PHY
PHY
FBUS+
Fabric
Sec.
CMM
PHY
PHY
CMM-B
PoE feed
PoE Socket
HASH BASED
SELECTION
System Architecture
Distributed Processing
Principle of operation for Distributed Processing
Each module provides a high performance CPU
Each modules CPU has a direct connection with each CMMs CPU
CMM-A
NI-1
CMM-B
CPU
Dedicated Mgmt
Bus (Gigabit
Ethernet)
CPU
NI-8
CPU
CPU
CPU
NI-1
STP BPDU
ARP Request
Routing Update
Management Access
CPU
NI-5
CPU
CPM
CPU
CMM-A
NI-2
CPU
CPU
NI-6
CPU
NI-3
NI-7
CPM
CPU
NI-4
CPU
CMM-B
CPU
NI-8
OS-9000-CMM
CMM 192 Gbps (119 Mpps)
Based on a new Fabric board,
Board
NI slot #8
Flash
CPU
USB
Processor board
Switch
Fabric
(8 x 10G)
OK1, OK2
Control
Fabric
Temp, Fan & PSU
RAM
Eth. Switch
Fabric board
Logically
independent
but
physically
one board
CMM Failover
Primary CPU failure
SW crash or processor failure on the primary CMM triggers a failover to the
CMM Failover
Distributed architecture
ARP table & Layer 3 FDB are duplicated & synchronized
On each NI
On the CMM
CMM
ARP
Cache
BBUS
NI
ARP Cache
ARP Cache
ARP Cache
During Fail-over
Secondary CMM
OS9000 GNIs
OS9-GNI-C24
OS9-GNI-U24
OS9-GNI-P24
OS9-GNI-C20L
OS9-GNI-C48T
48 ports 10/100/1000BaseT/TX using 8 Mini-RJ21 connectors
9600
96
192
9700
9800
384
9600 = 192
9700 = 384
9800 = 768
OS9000 XNIs
OS9-XNI-U2
OS9-XNI-U6
16
32
9800
9600
9700
9800
24
50
100
48
96
Memory
Red. CMM
Eth. Switch
RAM
NI slot #1
Flash
CPU
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
Memory
USB
4 x GigE
4 x GigE
4 x GigE
4 x GigE
4 x GigE
4 x GigE
1 x 10GigE 1 x 10GigE 1 x 10GigE 1 x 10GigE 1 x 10GigE 1 x 10GigE
Processor board
Switch
Fabric
(8 x 10G)
NI slot #8
Fabric board
Logically
independen
t,but
physically
one board
RAM
CPU
PHY
Prim. CMM
PHY
architecture
Standard
Fwd Engine
PHY
PHY
Sec. CMM
PHY
PHY
PoE feed
PoE Socket
Parser
Parsing all first 128 Bytes of each packet
Partial parsing on Fbus+ ports (FBUS+ Header)
Full parsing (128 Bytes) only needed on original ingress Ethernet ports
sFlow
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Security Engine
DoS attack Detection (packets dropped based on the following
conditions)
SIP = DIP for IPv4/IPv6 packets
TCP packets with control flags = 0, and sequence
number = 0
TCP packets with FIN, URG and PSH bits set, and
sequence number = 0
TCP packets with SYN and FIN bits set
TCP source port no. = TCP destination port no.
First TCP fragment does not have the full
TCP header (less than 20 bytes)
TCP header has fragment offset value as 1
UDP source port no. = UDP destination port no.
ICMP ping packets payload is larger than the
programmed value of ICMP maximum size
Fragmented ICMP packets
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Switching Engine
Provides the Switching information
VLAN type select
VLAN look-up
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing Engine
Provides the Routing information (IPv4/IPv6)
L3 unicast look-up
L3 multicast look-up
LPM : Longest Prefix Match Wire Rate from the first packet
4k Interfaces
128 Tunnels
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Classification Engine
and Buffer Management
Known as Content Aware Processor
mapping)
Policers
Counters
buffers
Tracks the number of buffers in use
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Traffic Management
and Modification
Traffic Management
Modification
Queuing
Shaping
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Routing
Engine
Classification
Engine
Switching
Engine
Buffer
Management
Security
Engine
Traffic
Management
Parser
Modification
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
Memory
4 x GigE
1 x 10GigE
4 x GigE
1 x 10GigE
RIP
BGP4
RIB
Software table
is updated via
IPC from the
CMM
Routing/forwarding
is wire rate first
packet because
the LPM hardware
table is updated
before the packet is
received
IPC
Software FIB
LPM Hardware
Table
Software FIB
LPM Hardware
Table
OmniSwitch 6850
10Gig uplinks
101,2 Mpps
OmniSwitch 6850
100Base-FX
10Gbase-LR: SMF 10 km
100Base-LX10
10Gbase-ER: SMF 40 km
100Base-BX10
10Gbase-ZR: SMF 80 km
1000BaseT-SFP
1000Base-SX
SW upgradeable to 10/100/1000
1000Base-LX
4-port combo
1000Base-LH
Dual rate optics
OS6850-U24X
22-port 100/1000 (SFP)
2-port combo
10/100/1000 (RJ45)
100/1000 (SFP)
OS6850-Lite
10/100/1000 (RJ45)
1000 (SFP)
Supported models
OS6850-24L / OS6850-48L
OS6850-P24L / OS6850-P48L
OmniSwitch 6850
Stack LED
RJ-45
console
4 miniGBIC /
Copper combo
ports.
OS6850-48
16 10 Gig ports
Distributed
and
resilient
management
40G full
duplex
stack loop
Smart
Continuous
Switching
Image /
config
rollback
Hot swap
everythin
g
802.3ad
802.1w
OSPF ECMP
VRRP
Selection
Primary
Secondar
y
Idle
Idle
Idle
Idle
Chassis uptime
Selection
Switch connected to primary stacking
port A
Second slowest slot value
chassis
Pass-Through mode
Dupplicate slot number
Forced by >stack clear slot
No disruption of the stack
Existing Stack
Avoid duplicate saved slot numbers
Never attempt to operate more than
crossed
straight
A B
OmniStack LS 6200
Stackable 24/48+4 1U fixed configuration all-in-one designs
2 Gig combo ports (copper, miniGBIC) (100Base-FX SFP supported)
2 10/100/1000 RJ-45 copper stacking ports
OS-LS-6212
OS-LS-6212P
48 x 10/100 w/ PoE
2 x 10/100/1000
2 x combo
OS-LS-6224
OS-LS-6224P
24 x 10/100 w/ PoE
2 x 10/100/1000
2 x combo
OS-LS-6248
OS-LS-6248P
48 x 10/100 w/ PoE
2 x 10/100/1000
2 x combo
OS-LS-6224U
OmniStack LS 6200
Availability
Resilient stacking, across stack features
& management
Backup power supply
DC power
802.1w, 802.1s
802.3ad
QoS: Flow based, 4 egress queues
(strict, WRR), L3 stamping & mapping,
rate limiting per flow/port
Security
Radius & TACACS+
MAC, Proto & IP subnet VLANs
Port mapping (private VLAN)
MAC address lockdown
802.1x
Extended access control lists
SSL, SSH, SNMPv3
Multicast IPTV VLAN registration
VLAN Stacking
DHCP Snooping option 82
Manageability
Industry standard CLI
Dual image/config
WebView element manager
GVRP, AMAP
Virtual cable tester