Chapter 2 The 8051 -Processor

2.1

8051 Microcontroller Pin Configuration

2.2

Memory Organization

2.3

Memory Mapping

2.1

8051 Microcontroller Pin Configuration

2.1.1

Power Connection Pins

The 8051 operates from a single +5V supply (Vcc).

Vcc connection is on pin 40, and the
Vss (GND) connection is on pin 20.

2.1.2

On-chip Oscillator Input

C1
XTAL2 [Pin 18]

C1, C2 = 30 pF 10 pF

C2
XTAL1 [Pin 19]

Typically driven by a crystal connected to pins 18

(XTAL2) and 19 (XTAL1).
The nominal crystal frequency is 12MHz for most ICs in
MCS-51TM family.
TTL clock source may also be connected to XTAL1 and
XTAL2.

2.1.3

Control Pins

Program Store Enable (PSEN): Read strobe to external program

memory.

Activated (held low) when executing code from the external program
memory.

Not activated during internal program memory fetching.

Address Latch Enable (ALE): An output pulse for latching the low byte
of the address during accesses to external memory.
External Access (EA): Must be externally held low (ground) to enable
the device to fetch code from external program memory. If EA is held
high (+5V), the device executes program from internal program
memory.
Reset (RST): Whenever this pin output is high for two machine cycles
while the oscillator is running, it will reset the device.

2.1.4

I/O Pins

The 8051 has 32 pins of I/O port lines. However, 24 of these

lines are dual-purpose.
Each of the lines may operate as I/O, or as a control line, or
part of the address or data bus.
The 8 lines in each port can be treated as a unit in interfacing
with parallel devices such as printers, digital-to-analog
converters and etc.
The lines can be also treated independently in interfacing to a
single-bit device such as switches, LEDs, transistors, motors
and loudspeakers.
There are four I/O ports in 8051 microcontroller, they are:
i.
i.
ii.
iii.

Port 0
Port 1
Port 2
Port 3

i)

Port 0
o
o
o

ii) Port 1
o
o

A dual-purpose port on pins 32 39.

For small design, it is used as general
purpose I/O
port.
For larger designs with external memory,
this port becomes a multiplexed low-byte
address and data bus to access the external
program and data memory.
A dedicated I/O port on pins 1 8.
No alternate function are assigned to this
port, thus they are solely for interfacing
with external devices.
7

iii) Port 2
o
o

iv) Port 3
o
o

A dual-purpose I/O port on pins

21 28.
For designs with external
memory, this port serves as the
high-byte address bus.
A dual-purpose I/O port on pins
10 17.
This pins are multifunctional,
with each having an alternate
purpose related to special
features of the 8051.

Alternate pin functions for Port 3

Bit
P3.0

P3.1

Name

Bit Address

RXD

B0H

TXD

P3.2

INT0

P3.4

T0

P3.3

P3.5

P3.6

P3.7

INT1
T1

WR

RD

B1H

B2H

B3H

B4H

B5H

B6H

B7H

Alternate Function
Receive data for serial port

Transmit data for serial port

External interrupt 0

External interrupt 1

Timer/counter 0 external input

Timer/counter 1 external input

External data memory write strobe

External data memory read strobe

2.2

8051 Memory Organization

8051 implements a separate address space for programs (code)
and data memory.
Both code and data memory may be internal, however both may
be expand using external memory components to a maximum of
64K code memory and 64K data memory.

8051

Program
Memory

Data
Memory

[ROM]

[RAM]
10

2.2.1

8051 Memory Structure

Data
Memory

Program
Memory

FFFF

(Read/Write)

(Read Only)

On-chip
(Internal)
Data Memory
(RAM)
FF

128
bytes

7F
00

Upper
part
Lower
part

SFR

External
Data
Memory
(RAM)

External
Code
Memory
(ROM)
Enabled via
PSEN

Enabled via
WR and RD

1000

4Kb

On-chip
ROM

0FFF

(EA=1)

0000

64K bytes

FFFF

External
ROM
(EA=0)

0000

11

 The on-chip RAM contains of arrangements of general-purpose storage, bitaddressable storage, register banks, and special function register (SFR).
7F

30
2F

20
1F

00

Bit-addressable
Locations
Bank 3
Bank 2
Bank 1
Bank 0

Special Function
Register
(SFR)

Lower

On-chip
RAM

Upper

General-purpose
RAM

FF

00

FF

80

12

2.2.2

Register Banks

The bottom 32 locations of internal memory contain the register banks.

The instruction set supports 8 registers, R0 through R7.

By default (after a system reset), Bank 0 at addresses 00H 07H is used.

1F

00

Bank 3

R7 R6 R5 R4 R3 R2 R1 R0

Bank 2

R7 R6 R5 R4 R3 R2 R1 R0

Bank 1

R7 R6 R5 R4 R3 R2 R1 R0

Bank 0

R7 R6 R5 R4 R3 R2 R1 R0

The active register bank may be altered by changing the register bank
select bits in the program status word (PSW) in SFR.

The advantage of having register banks is to permit fast and effective

context switching.

13

2.2.3

Bit Addressable RAM

The 8051 contains 210 bit-addressable locations, where 128 are at byte
addresses of 20H to 2FH, and the rest are in the SFR.

All bits in this area can be set (1), cleared (0), ANDed, ORed, and so on
with a single instruction.

2F

Bit-addressable
Locations
20

27

3F

3E 3D 3C 3B 3A 39 38

2F

7F

7E 7D 7C 7B 7A 79 78

26

37 36 35 34 33 32 31 30

2E

77 76 75 74 73 72 71 70

25

2F

2E 2D 2C 2B 2A 29 28

2D

6F

24

27 26 25 24 23 22 21 20

2C

67 66 65 64 63 62 61 60

23

1F

2E 2D 1C 1B 1A 19 18

2B

5F

22

17 16 15 14 13 12 11 10

2A

57 56 55 54 53 52 51 50

21

0F

0E 0D 0C 0B 0A 09 08

29

4F

20

07 06 05 04 03 02 01 00

28

47 46 45 44 43 42 41 40

6E 6D 6C 6B 6A 69 68

5E 5D 5C 5B 5A 59 58

4E 4D 4C 4B 4A 49 48

These bit-addressable location may also be accessed as bytes,

depending on the instruction.

14

For example, to set bit 3 in byte address 25H, we use the instruction:
SETB

2F

Bit-addressable
Locations
20

2BH

27

3F

3E 3D 3C 3B 3A 39 38

2F

7F

7E 7D 7C 7B 7A 79 78

26

37 36 35 34 33 32 31 30

2E

77 76 75 74 73 72 71 70

25

2F

2E 2D 2C 2B 2A 29 28

2D

6F

24

27 26 25 24 23 22 21 20

2C

67 66 65 64 63 62 61 60

23

1F

2E 2D 1C 1B 1A 19 18

2B

5F

22

17 16 15 14 13 12 11 10

2A

57 56 55 54 53 52 51 50

21

0F

0E 0D 0C 0B 0A 09 08

29

4F

20

07 06 05 04 03 02 01 00

28

47 46 45 44 43 42 41 40

6E 6D 6C 6B 6A 69 68

5E 5D 5C 5B 5A 59 58

4E 4D 4C 4B 4A 49 48

To access these location by bytes instruction, i.e. to set only bit 3 of

byte address 2BH (i.e. 5BH), we may use the instruction as follows:
MOV

2BH, #08H

15

2.2.4

General-purpose RAM
General-purpose RAM occupies 80 bytes of RAM location from
addresses 30H to 7FH.

Any location in this area can be accessed freely using direct or

indirect addressing modes (discussion on addressing mode will be on
Chapter 3).
7F
Direct Addressing Mode:

MOV

General-purpose
RAM

30

A, 5FH

Indirect Addressing Mode:

MOV
MOV

@R0, 5FH
34H, #R1

16

2.2.5

Special Function Registers (SFR)

The 8051 has 21 SFRs as shown in the

figure. Note that some of the SFRs are
not defined.

Some of the SFR may not be bitaddressable, while some are both byteaddressable and bit-addressable.
For example, the instruction
SETB 0E0H

sets the bit 0 in the accumulator, ACC at

address E0H whereas the instruction
MOV A, #01010101B

will write the accumulator with the

value 01010101B or in hex, 55H.
Also notice that all I/O ports are in SFR,
at addresses 80H (Port 0), 90H (Port 1),
A0H (Port 2) and B0H (Port 3).

17

Following sections will discuss the functions of each SFRs.

2.2.5.1 Program Status Word (PSW)

PSW internal address D0H with reset value 00H.

It is bit addressable: i.e. PSW.0 - PSW.7

Contains several status bits that reflect the current state of CPU as
summarized below:
BIT

PSW.7
PSW.6
PSW.5
PSW.4
PSW.3
PSW.2
PSW.1
PSW.0

SYMBOL

ADDRESS

CY
AC
-RS1
RS0
OV
-P

D7H
D6H
D5H
D4H
D3H
D2H
D1H
D0H

BIT DESCRIPTION

Carry Flag
Auxiliary Carry Flag
Undefined
Register Bank Select 1
Register Bank Select 0
Overflow Flag
Undefined
Parity Flag
18

Carry Flag (C or CY) is used for arithmetic operations where it will be

set when:
o theres a carry out of bit 7 during addition (ADD) operation
o theres a borrow into bit 7 during a subtract (SUB) operation
For example,
Ex:

Result:
ACC =
C=

MOV R5, #55H

MOV A, #0AAH
ADD A, R5

ACC =
C=

ADD A, #1

CY flag is also the Boolean Accumulator, serving as a 1-bit register for

Boolean instruction operation operating on bits.

For example, the following instruction ORs bit 24H with the CY and
places the result back in the CY flag.
ORL

C, 24H

19

Auxiliary Carry Flag (AC) is set in BCD addition when:

o
o

theres a carry out of bit 3 into bit 4, or

the result in the lower nibble is in the range of 0AH 0FH.

If the values added are BCD, then the ADD instruction must be
followed by DA A (decimal adjust accumulator) to bring results
greater than 910 back into range.
For example, (with initial ACC = 0)
MOV R5, #1
MOV A, #9
ADD A, R5

Result:
ACC =
AC =

AC = 1 as the lower nibble (10102 = A 16 ) is greater than 910.

Flag 0 is a general purpose flag bit for user applications. Example:

Results:

SETB, F0

PSW.5 =

20

Register Bank Select Bits (RS1 and RS0) determine the active
register bank.

Default register bank used is Bank 0, where RS1 and RS0 are cleared
after a system reset.
Bank
Bank
Bank
Bank

0
1
2
3

RS1
0
0
1
1

SETB RS1
SETB RS0
MOV R7, #1

Bank 3

SETB RS1
CLR RS0
MOV R7, #1

Bank 2

CLR RS1
SETB RS0
MOV R7, #1

Bank 1
Bank 0

RS0
0
1
0
1

1FH
18H
17H
10H
0FH
08H
07H
00H

21

Overflow Flag (OV) is set after an addition or subtraction if there was an

arithmetic overflow.

For unsigned number addition operation, OV is set to 1 when there is a

carry out of bit 7.
For signed number addition operation, OV is set to 1 when:
o
o

Theres a carry out of bit 6 to bit 7 and no carry out of bit 7

Theres a carry out of bit 7 and no carry out from bit 6 to bit 7

OV is also used in multiplication (MUL AB) and division (DIV AB)

operation.
For division operation, OV will be set when the division is invalid (B=0).

For multiplication operation, OV will be set when the product of the

operation is greater than FFH. For example:
MOV R7, #0FH
MOV A, #7FH
ADD A, R7

Result:
ACC =
OV =

22

Parity (P) bit is automatically set or cleared to establish even parity

with the accumulator.
This bit is set when the number of 1s in accumulator is odd.

If the number of 1s in the accumulator is even, then P = 0. For example,

MOV A, #10101101B

Result:
P=

2.2.5.2 B Register (B)

B register, or accumulator B is used along with the accumulator [Acc]

for multiplication and division process.

The B register can also be treated as a general-purpose register. It is

bit-addressable through bit addresses F0H to F7H.
For example:

MOV A, #55H
MOV B, #22H
MUL AB

ACC =
B
=

23

2.2.5.3 Stack Pointer (SP)

SP is an 8-bit register at address 81H. It contains the address of the data

item currently in the top of the stack.

Stack operations include pushing data on the stack and popping data
off the stack.
o Pushing increments the SP before writing data.
o Popping reads data and decrement s the SP.
The default value of SP upon system reset is 07H. For example, to
reinitialize the SP with the stack begin at 60H:
MOV SP, #5FH

PUSH A
PUSH PSW
POP PSW
POP A

7F
.
.
.
.
.
.
62
61
60
5F

PSW
A
24

2.2.5.4 Data Pointer (DPTR)

DPTR is used to access external code or data memory. It is 16-bit

register at addresses 82H and 83H. 82H is for DPL (low-byte) and
83H for DPH (high-byte)
Ex:
MOV A, #01H
MOV DPTR, #0FF38H
MOVX @DPTR, A

write 01H into

external device
location FF38H

2.2.5.5 Port Registers (P0, P1, P2, P3)

The 8051 consist of Port 0 at address 80H, Port 1 at address 90H,

Port 2 at address A0H and Port 3 at address B0H.
Port 0 and Port 2 may not be available for general-purpose I/O if
external memory is used.

Port 3 may also not available for general-purpose I/O if some of

8051 special features, such as interrupts and serial port are used.
All ports are bit-addressable.

25

Example:
SETB P1.7

[97H ] = 1

MOV P2, #01H

[A0H] = 00000001

2.2.5.6 Timer Registers (TMOD, TCON, TH0, TL0, TH1, TL1)

The 8051 contains two 16-bit timer registers for timing intervals or
counting events.

Timer 0 is at addresses 8AH (TL0, low-byte) and 8CH (TH0, highbyte)

Timer 1 is at addresses 8BH (TL1, low-byte) and 8DH (TH1, highbyte)
Timer operation is set by the timer mode register (TMOD) at address
89H and the timer control register (TCON) at address 88H.

26

2.2.5.7 Serial Port Registers

Used for communicating with serial devices as terminals or modems,

or for interfaces with other ICs with a serial interface.

Serial data buffer (SBUF) at address 99H, holds both the transmit data
and receive data.

Modes of operation are programmable through the bit-addressable

serial port control register (SCON) at address 98H.

2.2.5.8 Interrupt Registers

Interrupts are disabled after a system reset and then enabled by

writing to the interrupt enable register (IE) at address A8H.

Priority level for each interrupts can be set through interrupt priority
register (IP) at address B8H.
Both register are bit-addressable.

27

2.2.5.9 Power Control Registers (PCON)

The PCON register at address 87H contains miscellaneous control bits.

SMOD

--

--

--

GF1

GF0

PD

IDL

The SMOD bit doubles the serial port baud rate when set

GF1 and GF0 are available for general-purpose flag bits for user
applications.

The power control bits, power down (PD) and idle (IDL), were
originally available in all MCS-51 family ICs but are now
implemented only in CMOS versions.
PCON is not bit-addressable.

28

2.3

Memory Mapping
The MCS-51 architecture provides memory expansion capability, in the
form of 64K external code memory and 64K external data memory.
Extra ROM and RAM can be added as desired. Peripheral interface ICs
can also be added to expand the I/O capability.
When external memory is used:
o
o

2.3.1

Port 0 is unavailable as an I/O port. It becomes a multiplexed

address (A0 A7) and data (D0 D7) bus.
Port 2 is usually employed for the high-byte of address bus.

Accessing External Code Memory

External code memory is read-only memory (ROM) enabled by PSEN

signal.

The hardware connections for external ROM memory are shown in the
next slide.

29

8051

ROM
Port 0

D0 D7
74HC373

EA

ALE

A0 A7

Port 2

A8 A15

PSEN

OE

30

Read Timing Diagram [From External ROM]

One machine cycle
State 1
P1 P2

State 2
P1 P2

State 3
P1 P2

State 4
P1 P2

State 5
P1 P2

Op
code

PCL

State 6
P1 P2

State 1
P1 P2

Oscillator
ALE
PSEN
Port 0
Port 2

PCL

PCH

Byte 2

PCH

31

Connections to be remembered:
i) PSEN
ii) EA
iii) ALE
iv) Port 0
v) Port 2

2.3.2

OE
Grounded
G of Latch
Lower Address Bus (A0 A7)
Upper Address Bus (A8 A15)

Accessing External Data Memory

External data memory (RAM) is accessed by read/write memory
enabled (RD and WR) pin on P3.7 and P3.6.

The only access to external data memory is with the MOVX instruction,
either using the 16-bit DPTR, R0 or R1 as the address register.
RAMs maybe interfaced to the 8051 the same way as ROMs except:
o the RD line connects to the RAMs output enable, OE line
o the WR line connects to the RAMs write enable, WE line.

32

8051

RAM

Port 0

D0 D7
VCC

74HC373
D

A0 A7

EA
ALE
Port 2
RD
WR

G
A8 A15
OE
WE

33

MOVX A, @DPTR [Reading from External Data Memory]

Machine cycle 1

Machine cycle 2

State State State State State State State State State State State State State
1
2
3
4
5
6
1
2
3
4
5
6
1
ALE

PSEN
RD

Port 0

Port 2

Op
code

PCL

PCH

Data
in

DPL

DPH

34

MOVX @DPTR, A [Writing onto External Data Memory]

Machine cycle 1

Machine cycle 2

State State State State State State State State State State State State State
1
2
3
4
5
6
1
2
3
4
5
6
1
ALE

PSEN
WR

Port 0

Port 2

Op
code

PCL

PCH

DPL

Data out

DPH
35

2.3.3

Address Decoding
If multiple ROMs and/or RAMs are interfaced to an 8051, address
decoding is required.

A decoder IC, such as 74HC138 is used with its outputs connected

to the chip select (CS) inputs on the memory ICs. The 8051 can
accommodate up to 64K each of ROM and RAM.
74HC138

A15

A14

A13

2
3
4
5
6
7

A15-A13

(CS)

000

RAM #1

010

RAM #3

100

ROM #1

101

ROM #2

110

ROM #3

001

RAM #2

36

Address bus
Data bus

D0 D8
PSEN

OE

C
B
A

RD

OE

WR

D0 D8

A0 A12

A0 A12

CS

CS
CS

74HC138

ROM
(8K bytes)

RAM
(8K bytes)

CS
CS

CS

0
1
2
3
4
5
6
7

37

2.3.4

Design Problem 1

Design an 8051-based system with 8Kbytes of external data RAM.

(4K*8 bit Memory ICs are available. Assume internal ROM is used)

Solution
Step 1- Find number of memory blocks needed..

Target = 8 Kbytes
Available = 4KBytes
Needed = 2 blocks of 4KBytes* 8 bits

Step 2- Find the total address line needed to accommodate memory

space given..
2n = Memory Space
2n = 4K
log2 2n = log2 4K
n log2 2 = log2 4K
n = log2 4K
log2 2
=

P0 to accommodate 8 lines
(P0.0 P0.7)

P2 to accommodate another 4 lines

(P2.0 P2.3)

38

Step 3- Determine number of data bus

8 bit= 8 data buses.

Step 4- Determine any control signals used..

RD OE, WRWE (As it involved RAM blocks )
EA Vcc (Used internal ROM)

ALE; for latching the lower bytes address

Step 5- Memory Space Allocation and Chip Select

2 blocks needed 1 bit address line required as CS

A12 as CS

Chip Select
Upper Bytes Address Lower Bytes Address
(A12 <-> P2.4) (A8-A11 <-> P2.0-P2.3) (A0-A7 <-> P0.0-P0.7)

12
02

1111 2

1111 1111 2

0000 2

0000 0000 2

1111 2

1111 1111 2

0000 2

0000 0000 2

39

Step 3- Draw the connections between 8051 and external RAM

8051

4 K RAM

Port 0

D0 D7
VCC

EA
ALE

74373
D Q

A0 A7

P2.0 P2.3

4 K RAM

A8 A11
A12

CS

D0 D7

RD

OE

WR

WE

A0 A7

P2.4

PSEN
Not connected

A8 A11
CS
OE
WE
40

2.3.5

Design Problem 2
Design an 8051-based system with 32Kbytes of ROM
(32Kb ROM & RAM ICs are available)

Solution
Step 1- Find number of memory blocks needed..

Target =32Kbytes
Available = 32KBytes
Needed =

Step 2- Find the total address line needed to accommodate memory

space given..
2n =
2n =
2n =
2n =
n=

Memory Space
32K
25 * 210
215

P0 to accommodate 8 lines
(P0.0 P0.7)

P2 to accommodate another 7 lines

(P2.0 P2.6)

41

8051

32 K ROM

42

2.3.6

Design Problem 3
You are given 32Kb ROM & RAM ICs. Design an 8051based system with 32Kbytes of ROM and 32Kbytes of RAM

Solution
8051

32 K x 8 ROM
D0 D7

74373
D Q

A0 A7

A8 A14

P2.0 P2.6
PSEN
P2.7

OE
A15

CS

RD
WR

32 K x 8 RAM
D0 D7
A0 A7
A8 A14
CS
OE
WE

43

2.3.7

Reset Operation

The 8051 is reset by holding RST high for at least two machine cycles
and then returning it to low. RST may be activated by a switch, or it may
be activated upon power-up using RC (resistor-capacitor) network.

The content of on-chip RAM is not affected by a reset operation. The

state of all the 8051 registers after a system reset summarized as:
REGISTER(S)
Program Counter (PC)
Accumulator (ACC)
B Register
PSW
Stack Pointer (SP)
Data Pointer (DPTR)
P0, P1, P2 and P3
Interrupt Priority (IP)
Interrupt Enable (IE)
Timer Registers
SCON
SBUF
PCON (CMOS)

CONTENTS
0000H
00H
00H
00H
07H
0000H
FFH
XXX00000B
0XX00000B
00H
00H
00H
0XXX0000B

44