CHANDIGARH UNIVERSITY, GHARUAN

Experiment-5
Aim: - To design, simulate and synthesize
a) SR Flip Flop
b) T Flip Flop
c) JK Flip Flop
Apparatus: - Xilinx ISE
Theory: a) SR Flip Flop: A flip-flop circuit can be constructed from two NAND gates or two NOR gates. These flip-flops are
shown in Figure. Each flip-flop has two outputs, Q and Q, and two inputs, set and reset. This type
of flip-flop is referred to as an SR flip-flop.

Truth Table: CLK

QBAR

NO CHANGE

NO CHANGE

NO CHANGE

NO CHANGE

Code: library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity sr_ff is
Port ( s,r,clk: in STD_LOGIC;
q,qbar: out STD_LOGIC);
end sr_ff;
architecture Behavioral of sr_ff is
begin
process(s,r,clk)
variable temp : std_logic;
begin
if(clk='1')then
if(s='0' and r='0')then
temp:=temp;
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CHANDIGARH UNIVERSITY, GHARUAN

elsif(s='0' and r='1')then
temp:='0';
elsif(s='1' and r='0')then
temp:='1';
else
temp:='Z';
end if;
end if;
q<=temp;
qbar<=not temp;
end process;
end Behavioral;
Output: -

b) JK Flip Flop
Theory: 33

CHANDIGARH UNIVERSITY, GHARUAN

A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is
defined in the JK type. Inputs J and K behave like inputs S and R to set and clear the flip-flop (note
that in a JK flip-flop, the letter J is for set and the letter K is for clear).
Truth Table: CLK

QBAR

NO CHANGE

NO CHANGE

NO CHANGE

NO CHANGE

Not(Q0)

Not(Q)

Code: library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity jk_ff is
Port ( j,k,clk : in STD_LOGIC;
q,qbar : out STD_LOGIC);
end jk_ff;
architecture Behavioral of jk_ff is
begin
process(j,k,clk)
variable temp : std_logic;
begin
if(clk='1')then
if(j='0' and k='0')then
temp:=temp;
elsif(j='0' and k='1')then
temp:='0';
elsif(j='1' and k='0')then
temp:='1';
else
temp:=not temp;
end if;
end if;
q<=temp;
qbar<=not temp;
end process;
end Behavioral;

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CHANDIGARH UNIVERSITY, GHARUAN

Output: -

c) T Flip Flop: Theory: The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is obtained from the JK
type if both inputs are tied together. The output of the T flip-flop toggles with each clock pulse.

Truth Table: CLK

QBAR

NO CHANGE

NO CHANGE

NO CHANGE

NO CHANGE

Not(Q0)

Not(Q)

Code: library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
entity tff is
Port ( t,clk : in STD_LOGIC;
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CHANDIGARH UNIVERSITY, GHARUAN

q,qbar: out STD_LOGIC);
end tff;
architecture Behavioral of tff is
begin
process(clk)
variable tmp: STD_LOGIC :='0';
begin
if(clk='1' and clk'event) then
if t='0' then
tmp:=tmp;
elsif t='1' then
tmp:=not (tmp);
end if;
end if;
q<=tmp;
qbar<=not tmp;
end process;
end Behavioral;

Output: -

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