Class AB output stages for low voltage CMOS opamps with

accurate quiescent current control by means of dynamic

biasing.
A. Torralba I , R. G. Cawajal I, J. Ramirez-Angulo ', J.Tombs' andJ. Galan'
'Dpto. de Ing. Electronica, Escuela Superior de Ingenieros, Universidad de Sevilla, Sevilla, Spain
*Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM.

Abstract
Two new class AB output stages for CMOS opamps are
proposed with accurate quiescent current control. The
second proposed stage also provides accurate control of
the minimum current through the output transistors. The
proposed stages can be operated with a supply voltage
close to a transistor threshold voltage. A dynamic biasing
scheme allows them to operate in a wide range of supply
voltages. Simulation and experimental results are provided
that are in good agreement with expected values.

2. Proposed class AB output stages and

quiescent current control
In this paper two new CMOS class AB output stages for
continuous-time operation are presented with simple md
accurate quiescent current control (figures la and 2).
A

1. Introduction
The market of portable electronic equipment has pushed
industry to produce circuit designs with very low supply
voltage. Although two oxides are presently available in
some analogue technologies, digital compatibility forces
analogue circuits to operate with supply voltages close to
a transistor threshold voltage.
Several low-voltage (VDD<1SV)class-AB op-amp schemes
have been recently reported [ 11441. The Monticelli's
scheme [l] for quiescent current control uses two
complementary head-togail connected transistors and two
matched current sources to implement a floating voltage
source. This scheme achieves an accurate quiescent
current control by means of a translinear loop at the
expense of a high supply voltage (larger than two VGs).In
[2] the (negative) floating voltage source of figure 1 b was
implemented with one current source and one transistor,
although a complex control loop was required for quiescent
current control. In [3], diode connected transistors acting
as loads of simple common source amplifiers were used to
bias the output transistors. Although the proposed stage
is very simple, no a good class AB behavior was achieved
and dependence on process variations was not fully
eliminated. In [4] a folded version of the Monticelli's
output stage was proposed to achieve operation with low
supply voltage. Other output stages using a feedback loop
for quiescent current control can also be found in the
literature, but they have a slower speed and may have
stability problems because of the feedback loop.

0-7803-7057-0/01/$10.00 02001 IEEE.

(4
Figurel: First proposed class-AB output stage: a) Basic
idea, b) dynamic biasing circuitry, c) practical
implementation.
a) First output stage @gure la).
Figure 2a shows the first proposed output stage and figure
lb its biasing circuit for quiescent current control. The
proposed stage uses resistor R and current sourCes I , to
implement the floating voltage source VASof figure 1 b. The
input and output terminal voltages are V,and E,, Cross
connecting terminals X and Y to the gates of transistors
MOut,,and
respectively, allows the supply voltage to
be close to a transistor threshold voltage. For larger supply
voltages a straight connection of these terminal should be
done.

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On the other hand, if lVABlwas too small, transistors Mlpand Ml,-M2, would operate in linear region.
Appropriate values for V? and VF are: VxQ= VDD - VsGMIpQ
- VDBar- dvxMAx/
2, and V p = VGsMln+ VDBa,+ oVxMAx/
2,
where dvxMAXis the maximum expected variation for the
input node voltage Vx . As a result, an appropriate value
for VAS= VP- VP = vDD - VGsMInQ - V S G ~ ~- ~ 2vDSat
~ Q
oVxMA".If the input node Vxin figure 3 is the first stage
output of an opamp, negative feedback reduces &xMAX to
only a few mVso that, for a 0.8,&ICMOS technology with
0.8 V of transistor threshold voltages, VDD - VABis in the
order of 1.8 to 3 V depending on transistor sizes and
biasing currents. According to this reasoning, this stage
can be operated with less than 1 V supply voltage and VAS
= - 0.8 V. Note that this stage can be also operated with a
high supply voltage if V,, is positive. The same dynamic
biasing scheme of figure 2b can be used to generate the
floating voltage sources VAS between nodes X-Y and W-Z
by means of two matched (and, normally scaled) replicas of
current sources I,' and resistor R'.

In figure lb, transistor MI and current source Zldetermine

V,=Vxe (upper index Q means quiescent value), while
transistor M2 and current source I2 = I1 determine V2=V?.
The resistor R' and the differential amplifier DA driving two
matched current sources I,.' constitute a voltageto-current
converter [ 6 ] ,so that I,' = - V,, / R' = ( V? - VxQ ) I R' .
This floating voltage source VAe is replicated in figure la,
by means of matched resistor R and current sources Z, In a
real implementation, to reduce power consumption, M I
(Md and I, = I, would be a scaled version of MoUrp
(M,,,,J
and bo,,,,Q
= hOumQ
, respectively. Figure IC shows a
pmctical implementation of the whole output stage, where
the amplifier DA of figure lb has been implemented by
means of a simple PMOS differential amplifier. Bottom
current sources I, and Zr'have been implemented by means
of a low voltage current mirror, allowing operation with less
than 1V supply voltage. Note that the circuit in figure IC
maintains its operation independent on the supply voltage,
as long as VA, remains negative (which approximately
means VDD < 2 V in our technology). For larger supply
voltages, the polarity of the floating voltage sources can
be reversed by changing the role of nodesX-Y.

3. Simulation and experimental results

The proposed output stages have been simulated with
HSPICE and the parameters of a standard 0.8 p n CMOS
technology whose transistor threshold voltages are in the
order of 0.85 V. Design parameters for the first output
stage (figure 1) are resumed in Table I. Figure 4a presents
the transistor currents IMOueand IMoumfor Vx in the range
[0.45V, 0.9v],with VDD=I.5Vshowinga typical class AB
behavior. The quiescent output current I,,? of 103.9 ,Ut is
in good agreement with the expected value ( I 00 ,Ut).

$+Iz

r'
V C M ADJ

Mal

Figure 2 : Second proposed class-AB output stage

b) Second output stage figure 2)

The second proposed output stage is shown in figure 2. In
this figure, the bias current I, in the low voltage differential
pairs Mlp-hf3p and MI,-M~,[5] accurately determines the
, ~
quiescent output current I~,,,Q= ~ o u m Q = ~ o u =2a0.
Furthermore, the minimum current in the output transistors
is given by ZouF'N = IMOumM"
= &oupMIN =ao.
Note that IOU?
and
do not depend on the value of the floating
voltage sources GB,which is selected to allow an accurate
copy of currents 1 ~ and
3 Z
~ Mto
~ transistors
~
MoUtpand
M,,,,,
respectively. Under quiescent conditions, if IVAd was too
large, transistors
and
would not be in saturation.

Zo,rN

.
.
I

, I -

_.-.-

Figure 3: Simple op-amp in voltage follower configuration

for testing output stages performances.

968

An opamp was built using the proposed output stage with

a simple PMOS differential pair as input stage. This op-amp
can be used for very low voltage switched op-amp

applications using the scheme proposed in [7] or in

sampled-data and continuous-time applications with the dc
level shift in the input stage provided by the circuit
proposed in [2]. For the sake of simplicity, the opamp was
simulated in a voltage follower configuration (figure 4) with
0. I 5 Vof quiescent input voltage, allowing up to 0.4 V
peak input signal with 1.5 Vsupply. Figure 4b shows the
transient response with a 0.3 Vpeak, 1.67 MHz square
input signal. Note that a slew rate of 12 V/,L&was achieved.
Intermediate column in Table I1 resumes simulated opamp
performances. The same simulations were repeated for the
second proposed output stage (figure 2). Figure 6a shows
the transistor currents IM,, and ZM~,,,for VXin the range
[O.IV, O.7V],with VO0=1.5V. In this case, not only I,,? but
also J,,;"'" are accurately determined by the biasing
circuitry. An opamp was also built with a PMOS
difirential input stage and simulated in a voltage follower
configuration(figure 3). Figure 6b shows the transient
response with a 0.3 Vpeak, 1.67 MHz square input signal.
Last column in Table I1 resumes simulated opamp
performances. Note that PSRR performance for both
Units
Mourn
MouW

W/L

Output Stage
of figure 2c
50011

1 W/L I 16511

I 165/1

WiL.

5011

20/1

M2

W/L

16.5/1

6/ 1

I,=I*

p.4

lO/l

1011

50011

500/1

4,

pA

200

200

M1bM2p

W/L

2511

M3P

w/L

50/1

M3n

I,

w/L
Ip.4

I-

191: I I

Output Stage
of figure 3
50011

MI

M,,,, Mln2 W/L

show the experimental transient response of the circuits to

a square input signal of 30hVpeak.topeak.
In both cases the
results obtained match with the simulated response. In the
final version of this paper detailed experimental results will
be shown. 11,DC Response

16.5/1

Figure 4: Simulation and results for the first proposed

output stage: a) Class AB behaviour, b transient response,
c) experimental transient response.

Table I Op-amp design parameters.

The proposed circuits were sent for fabrication using the
was
configuration of figure 3 @C level shift VCM.ADJ
implemented by means of a SC circuit). Figures 5c and 6c

4. Conclusions
Two new low voltage output stages have been proposed
for class-CMOS opamps. A new dynamic biasing
technique allows an accurate quiescent current control and
provides good PSRR. The second proposed stage also
allows to set the minimum current through output

969

transistors, which is a very convenient property for classAB output stages. Simulation and experimental results
show the classAB behavior of proposed stages.

[4]

DC Psspnnse

[5]

[6]

[7]

with quiescent current control, IEEE J. of SolidState Circuits, 1998, SC-33, (6), pp. 915-920.
DE LANGEN, and HUISING, H.J.: Compact low
voltage power-efficient operational amplifier cells
for VLSI, IEEE J. of Solid-state Circuits, 1998,
SC-33, (lo), pp. 1482-1496.
PELUSO, V., VANCORELAND, P., MARQUES,
A.M., STEYAERT, M.S.J., and SANSEN, W.: A
900mV low-power AID converter with 77 -dB
dynamic range, IEEE J. Solid-State Circuits,
1998, SC-33, (12), pp. 1887-1897.
RAM&Z-ANGULO,J., TORRALBA, A., and
CARVAJAL, R.G.: Low-voltage CMOS amplifiers
with wide inputautput voltage swing based on a
novel scheme, to be published in IEEE Tramon
CAS-II, 2000, CASH7 (5).
BASCHIROTTO, A., CASTELLO, R., and
MONTAGNA, G.P: Active series switch for
switched opamp circuits, Electron. Lett., 1999,
35, (4), pp. 263-264.
Units

m~

am

om

Mnn

tiNrc (

mh

;)

1.x

DcGain

(b)

Phase Margin
Unity Gain fequency

dB

Output
Output
Stage of Stage
fig.2c
offig.3
67
60

1 1 1 :l
0

7(P

60

MHz

18

20

332

387

Quiescent
output (p.4)
current
Minimum
output
current
(PA)
Supply current

(a)

I
I c-

(c)

PsRR

Figure 5: Simulation results for the second proposed

output stage: a) Class AB behaviour, b) transient response
c) experimental transient response.

dB

I40

I dB

I45

I 45

5. References
[l]

MONTICELLI, D.M.: A quad CMOS smglesupply op amp with rail-to-rail output swing.
IEEE J. of Solid-State Circuits, 1986, SC-21, (6),
pp. 1026-1034.

[2]

RAMIREZ-ANGULO,J., CARVAJAL, R.G,

[3]

500

TOMBS, J., and TORRALBA, A.: A simple

technique for opamp continuous-time 1 V supply
operation, Electron. Lett., 1999, 35, (4), pp. 263264.
YOU, F., EMBABI, S.H.K, and S h C H E Z SINENCIO, E.: Lowvoltage class AB buffers

Table IL Simulated performances

(G=lOpF, VorF1.5, G=lOpF, &500q VC~AIJJ=~OO~V)
(*) Transient response, 0.3V peak square input signal.

970