Professional Documents
Culture Documents
Preface
Preface
Introduction
This guide and the relevant operating or service manual documentation for the equipment provide
full information on safe handling, commissioning and testing of this equipment.
Documentation for equipment ordered from NR is dispatched separately from manufactured goods
and may not be received at the same time. Therefore, this guide is provided to ensure that printed
information normally present on equipment is fully understood by the recipient.
Before carrying out any work on the equipment, the user should be familiar with the contents of
this manual, and read relevant chapter carefully.
This chapter describes the safety precautions recommended when using the equipment. Before
installing and using the equipment, this chapter must be thoroughly read and understood.
Are familiar with the installation, commissioning, and operation of the equipment and of the
system to which it is being connected;
Are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorized to energize and de-energize equipment and to
isolate, ground, and label it;
Are trained in the care and use of safety apparatus in accordance with safety engineering
practices;
i
Date: 2015-10-22
Preface
DANGER! means that death, severe personal injury and considerable equipment damage
will occur if safety precautions are disregarded.
WARNING! means that death, severe personal and considerable equipment damage
could occur if safety precautions are disregarded.
CAUTION! means that light personal injury or equipment damage may occur if safety
precautions are disregarded.
NOTICE! is particularly applies to damage to device and to resulting damage of the protected
equipment.
DANGER!
NEVER allow a open current transformer (CT) secondary circuit connected to this
device while the primary system is live. Open CT circuit will produce a dangerously high
voltage that cause death.
WARNING!
ONLY qualified personnel should work on or in the vicinity of this device. This personnel
MUST be familiar with all safety regulations and service procedures described in this
manual. During operating of electrical device, certain part of the device is under high
voltage. Severe personal injury and significant device damage could result from
improper behavior.
WARNING!
Do NOT touch the exposed terminals of this device while the power supply is on. The
generated high voltage causes death, injury, and device damage.
WARNING!
Thirty seconds is NECESSARY for discharging the voltage. Hazardous voltage can be
present in the DC circuit just after switching off the DC power supply.
CAUTION!
Earthing
Securely earthed the earthing terminal of the device.
Operating environment
ONLY use the device within the range of ambient environment and in an
ii
Preface
Tel: +86-25-87178888
Fax: +86-25-87178999
Website: www.nrelect.com, www.nrec.com
Version: R2.01
iii
Date: 2015-10-22
Preface
Documentation Structure
The manual provides a functional and technical description of this relay and a comprehensive set
of instructions for the relays use and application.
All contents provided by this manual are summarized as below:
1 Introduction
Briefly introduce the application, functions and features about this device.
2 Technical Data
Introduce the technical data about this relay, such as electrical specifications, mechanical
specifications, ambient temperature and humidity range, communication port parameters, type
tests, setting ranges and accuracy limits and the certifications that our products have passed.
3 Operation Theory
Introduce a comprehensive and detailed functional description of all protective elements.
4 Supervision
Introduce the automatic self-supervision function of this device.
5 Management
Introduce the management function (measurement and recording) of this device.
6 Hardware
Introduce the main function carried out by each plug-in module of this relay and providing the
definition of pins of each plug-in module.
7 Settings
List settings including system settings, communication settings, label settings, logic links and etc.,
and some notes about the setting application.
9 Configurable Function
Introduce configurable function of the device and all configurable signals are listed.
10 Communication
Introduce the communication port and protocol which this relay can support, IEC60970-5-103,
IEC61850 and DNP3.0 protocols are introduced in details.
iv
Preface
11 Installation
Introduce the recommendations on unpacking, handling, inspection and storage of this relay. A
guide to the mechanical and electrical installation of this relay is also provided, incorporating
earthing recommendations. A typical wiring connection to this device is indicated.
12 Commissioning
Introduce how to commission this relay, comprising checks on the calibration and functionality of
this relay.
13 Maintenance
A general maintenance policy for this relay is outlined.
&
AND gate
1
OR gate
Comparator
BI
SET
EN
v
Date: 2015-10-22
Preface
SIG
XXX
Output signal
Timer
t
t
0ms
0ms
[XXX]
[XXX]
Example
A, B, C
L1, L2, L3
AN, BN, CN
Ua, Ub, Uc
ABC
L123
U (voltage)
U0, U1, U2
VN, V1, V2
vi
1 Introduction
1 Introduction
Table of Contents
1 Introduction ....................................................................................... 1-a
1.1 Application....................................................................................................... 1-1
1.2 Function ........................................................................................................... 1-4
1.3 Features ........................................................................................................... 1-7
List of Figures
Figure 1.1-1 Typical application of PCS-931 for single circuit breaker ................................. 1-1
Figure 1.1-2 Typical application of PCS-931 for double circuit breakers .............................. 1-2
Figure 1.1-3 Functional diagram of PCS-931............................................................................ 1-3
1-a
Date: 2015-10-22
1 Introduction
1-b
Date: 2015-10-22
1 Introduction
1.1 Application
PCS-931 is a digital line differential protection with the main and back-up protection functions,
which is designed for overhead line or cables and hybrid transmission lines of various voltage
levels.
52
52
PCS-931
PCS-931
In the case of main protection, PCS-931 comprises dual-channels current differential protection
which can clear any internal fault instantaneously for the whole line with the aid of protection signal.
Pilot distance protection (PUTT, POTT, blocking and unblocking) and pilot directional earth-fault
protection with dual-channels (selectable for independent communication channel or sharing
channel with POTT) are optional. Deviation of power frequency component (DPFC) distance
protection with fixed forward direction can perform extremely high speed operation for close-up
faults. There is direct transfer trip (DTT) feature incorporated in the device.
PCS-931 also includes distance protection (1 forward zones and 4 settable forward or reverse
zone distance protection with selectable mho or quadrilateral characteristic, dedicated pilot
distance zone for pilot distance protection), out-of-step protection, 4 stages directional earth fault
protection, 4 stages directional phase overcurrent protection, 3 stages directional
negative-sequence overcurrent protection, 3 stages voltage protection (under/over voltage
protection), 1 stage negative-sequence overvoltage protection, 4 stages frequency protection
(under/over frequency protection), broken conductor protection, reverse power protection, pole
discrepancy protection, breaker failure protection, thermal overload protection, and dead zone
protection etc. Morever, a backup overcurrent and earth fault protection will be automatically
enabled when VT circuit fails.
In addition, stub differential protection is provided for one and a half breakers arrangement when
transmission line is put into maintenance.
PCS-931 can be configured to support single circuit breaker application or double circuit breakers
application by PCS-Explorer. If the device is applied to double circuit breakers mode, all protection
functions related to the number of circuit breaker will be affected, including circuit breaker position
supervision, breaker failure protection, dead zone protection, pole discrepancy protection,
synchrocheck, automatic reclosure, trip logic, CT circuit supervision, control and synchrocheck for
manual closing.
1-1
Date: 2015-10-22
1 Introduction
Bus1
Single-phase
voltage
52
PCS-931
Line 1
Three-phase
voltage
52
Line 2
Single-phase
voltage
52
Bus2
PCS-931 has selectable mode of single-phase tripping or three-phase tripping and configurable
auto-reclosing mode for 1-pole, 3-poles and 1/3-pole operation.
PCS-931 with appropriate selection of integrated protection functions can be applied for various
voltage levels and primary equipment such as cables, overhead lines, interconnectors and
transformer feeder, etc. It also supports configurable binary inputs, binary outputs, LEDs and IEC
61850 protocol.
1-2
Date: 2015-10-22
1 Introduction
BUS
52
81
85
21D
59Q
87L
21
50/51P
50/51G
50/51Q
50GVT
50PVT
50BF
49
46BC
32R
62PD
FR
59G
78
59P
FL
Data Transmit/Receive
27P
50DZ
25
79
LINE
Function
ANSI
87L
Pilot protection
85
21D
Distance protection
21
Out-of-step protection
78
50/51P
50/51G
50/51Q
Overvoltage protection
59P
10
Undervoltage protection
27P
11
59Q
12
59G
13
Frequency protection
81
14
46BC
15
32R
16
50BF
17
49
18
87STB
19
50DZ
20
62PD
21
SOTF
22
50PVT
23
50GVT
24
Synchronism check
25
1-3
Date: 2015-10-22
1 Introduction
25
Automatic reclosure
79
26
Fault recorder
FR
27
Fault location
FL
1.2 Function
1.
Protection Function
One zone distance protection with fixed forward direction (including phase-to-ground and
phase-to-phase, mho or quadrilateral characteristic)
One zone pilot distance protection with fixed forward direction (including phase-to-ground
and phase-to-phase, mho or quadrilateral characteristic)
One zone pilot distance protection with fixed reverse direction (including phase-to-ground
and phase-to-phase, mho or quadrilateral characteristic)
Four zones distance protection with settable forward or reverse direction (including
phase-to-ground and phase-to-phase, mho or quadrilateral characteristic)
Power swing blocking releasing, selectable for each of above mentioned zones
Out-of-step protection
Overcurrent protection
Four stages directional earth fault protection, selectable time characteristic (definite-time
or inverse-time) and directionality (forward direction, reverse direction or non-directional)
1-4
Date: 2015-10-22
1 Introduction
Voltage protection
Frequency protection
Control function
Synchro-checking
Automatic reclosure (single shot or multi-shot (max. 4) for 1-pole AR and 3-pole AR)
1-5
Date: 2015-10-22
1 Introduction
Dual-channels redundancy
2.
Synchronism check for remote and manual closing (only for one circuit breaker)
Energy metering (active and reactive energy are calculated in import respectively export
direction)
3.
Logic
4.
Additional function
Fault location
VT circuit supervision
CT circuit supervision
Self diagnostic
Event Recorder including 1024 disturbance records, 1024 binary events, 1024 supervision
events, 256 control logs and 1024 device logs.
Disturbance recorder including 32 disturbance records with waveforms (The file format of
disturbance recorder is compatible with international COMTRADE file.)
Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the optical coupler
PPS (DIN): Pulse per second (PPS) via the optical coupler
SAS
1-6
Date: 2015-10-22
1 Introduction
Advanced
NoTimeSync
5.
Monitoring
Channel status
Frequency
6.
Communication
Optional 2 or 4 Ethernet ports (depend on the chosen type of MON plug-in module) conform
to IEC 61850 protocol, DNP3.0 protocol or IEC 60870-5-103 protocol over TCP/IP
Optional 2 Ethernet ports via optic fiber (ST interface) conform to IEC 61850 protocol, DNP3.0
protocol or IEC 60870-5-103 protocol over TCP/IP
7.
User Interface
Friendly HMI interface with LCD and 9-button keypad on the front panel.
Auxiliary softwarePCS-Explorer
1.3 Features
The intelligent device integrated with protection, control and monitor provides powerful
protection function, flexible protection configuration, user programmable logic and
configurable binary input and binary output, which can meet with various application
requirements.
1-7
Date: 2015-10-22
1 Introduction
Fast fault clearance for faults within the protected line, the operating time is less than 10 ms
for close-up faults, less than 15ms for faults in the middle of protected line and less than 25ms
for remote end faults.
The unique DPFC distance element integrated in the protective device provides extremely
high speed operation and insensitive to power swing.
Self-adaptive floating threshold which only reflects deviation of power frequency component
improves the protection sensitivity and stability under the condition of load fluctuation and
system disturbance.
Advanced and reliable power swing blocking releasing feature which ensure distance
protection operate correctly for internal fault during power swing and prevent distance
protection from maloperation during power swing
Flexible automatic reclosure supports various initiation modes and check modes
Multiple setting groups with password protection and setting value saved permanently before
modification
Powerful PC tool software can fulfill protection function configuration, modify setting and
waveform analysis.
1-8
Date: 2015-10-22
2 Technical Data
2 Technical Data
Table of Contents
2 Technical Data ................................................................................... 2-a
2.1 Electrical Specifications ................................................................................. 2-1
2.1.1 AC Current Input .................................................................................................................. 2-1
2.1.2 AC Voltage Input .................................................................................................................. 2-1
2.1.3 Power Supply ....................................................................................................................... 2-1
2.1.4 Binary Input .......................................................................................................................... 2-1
2.1.5 Binary Output ....................................................................................................................... 2-2
2-a
Date: 2015-10-21
2 Technical Data
2-b
Date: 2015-10-21
2 Technical Data
ABC
50Hz, 60Hz
1A
Linear to
5A
Thermal withstand
-continuously
4In
-for 10s
30In
-for 1s
100In
250In
Burden
Number
ABC
50Hz, 60Hz
100V~130V
Linear to
1V~170V
Thermal withstand
-continuously
200V
-10s
260V
-1s
300V
Burden at rated
Number
IEC 60255-11:2008
Rated voltage
110Vdc/125Vdc/220Vdc/250Vdc
110Vac/220Vac
88~300Vdc
88~264Vac
Burden
Quiescent condition
<30W
Operating condition
<35W
Rated voltage
110Vdc
220Vdc
1.1mA
2.2mA
On value
2-1
Date: 2015-10-21
2 Technical Data
Off value
<66Vdc
300Vdc
Withstand voltage
1ms
Number
2.
<132Vdc
Rated voltage
110Vdc
125Vdc
220Vdc
220Vdc
1.1mA
1.25mA
2.2mA
2.85mA
On value
77-132Vdc
87.5-150Vdc
154-264Vdc
176-264Vdc
Off value
<55Vdc
<62.5Vdc
<110Vdc
<140Vdc
300Vdc
Withstand voltage
1ms
Number
Tripping/signaling contact
Output mode
380Vac, 250Vdc
Continuous carry
8A
<5ms
Dropoff time
<5ms
0.65A@48Vdc
0.35A@110Vdc
0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
12A@3s
18A@1s
24A@0.5s
40A@0.2s
10000 operations
Number
2.
Output mode
250Vdc
Continuous carry
10A
Pickup time
<1ms
Dropoff time
<10ms
10A
15A@3s
PCS-931 Line Differential Relay
2-2
Date: 2015-10-21
2 Technical Data
30A@1s
Durability (Loaded contact)
10000 operations
Number
3.
Output mode
380Vac, 250Vdc
Continuous carry
5A
Pickup time
<1ms
Dropoff time
<5ms
0.65A@48Vdc
0.35A@110Vdc
0.30A@125Vdc
0.20A@220Vdc
0.15A@250Vdc
8A@3s
12A@1s
16A@0.5s
30A@0.2s
10000 operations
Number
Flush mounted
Chassis color
Silver grey
Approx. 15kg
Chassis material
Aluminum alloy
Location of terminal
Device structure
Protection class
Standard
IEC 60255-1:2009
Front side
IP51
Other sides
IP30
IP20
IEC 60255-1:2009
Operating temperature
-40C to +70C
Permissible humidity
Pollution degree
2-3
Date: 2015-10-21
2 Technical Data
Altitude
<3000m
Protocol
IEC 60870-5-103:1997
Maximal capacity
32
Transmission distance
<500m
Safety level
Twisted pair
RJ-45
ST (Multi mode)
Transmission rate
100Mbits/s
Transmission standard
100Base-TX
100Base-FX
Transmission distance
<100m
<2km (1310nm)
Protocol
Safety level
Connector type
ST
Fibre type
Multi mode
Transmission distance
<2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Min. -30.0dBm
Margin
Min +3.0dB
Connector type
LC
Fibre type
Multi mode
Transmission distance
<2km
Wave length
1310nm
Transmission power
Min. -20.0dBm
Min. -30.0dBm
Margin
Min +3.0dB
2-4
Date: 2015-10-21
2 Technical Data
Connector type
FC
ST
Fibre type
Single mode
Multi mode
Wave length
1310nm
1550nm
850nm
Transmission distance
Max.40km
Max.100km
Max.2km
Transmission power
-13.03.0 dBm
-12dBm~-20 dBm
Min.-37 dBm
Min.-36 dBm
Min. -30.0dBm
Min.-3 dBm
Min.-3 dBm
Min.-8 dBm
Connector type
ST
Fibre type
Multi mode
Wave length
850nm
Min. -25.0dBm
Margin
Min +3.0dB
RS-232
Baud Rate
Printer type
Safety level
RS-485
Transmission distance
<500m
Maximal capacity
32
Timing standard
PPS, IRIG-B
Safety level
IEC60068-2-1:2007
IEC60068-2-2:2007
IEC60068-2-30:2005
2-5
Date: 2015-10-21
2 Technical Data
IEC 60255-27:2013
Dielectric tests
Overvoltage category
Insulation
resistance
measurements
Spot frequency
Radiated amplitude-modulated
10V/m (rms), f=80MHz/160MHz/450MHz/900MHz
Radiated pulse-modulated
10V/m (rms), f=900MHz
IEC 60255-26:2013
Conducted
RF
Electromagnetic
Disturbance
IEC 60255-26:2013
Power supply, AC, I/O, Comm. Terminal: Class , 10Vrms, 150
kHz~80MHz
IEC 61000-4-8:2001
Immunity
IEC 61000-4-9:2001
class , 6.4/16s, 1000A/m for 3s
IEC 61000-4-10:2001
immunity
2-6
Date: 2015-10-21
2 Technical Data
IEC 60255-26:2013
- Voltage dips
2.6 Certifications
ISO9001:2008
ISO14001:2004
OHSAS18001:2007
ISO10012:2003
CMMI L5
2.7 Terminals
Connection Type
Wire Size
2
AC current
AC voltage
Power supply
Contact I/O
Range
Accuracy
Phase range
0~ 360
Frequency
fn3 Hz
0.02Hz
0.05~5.00In
Voltage
0.05~1.50Un
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
2-7
Date: 2015-10-21
2 Technical Data
Energy (Wh)
Energy (VAh)
0.05~1.50Un
0.05~5.00In
0.05~1.50Un
0.05~5.00In
Local or remote
1s
3s
3s/day
1ms
Recording position
1ms
Potential-free contact
Resolution of SOE
2ms
0.050In~30.000In (A)
Accuracy
0.050In~30.000In (A)
Accuracy
Un~2Unn (V)
Accuracy
2-8
Date: 2015-10-21
2 Technical Data
<5ms
<25ms
(0.000~4Unn)/In (ohm)
Accuracy
Resetting ratio
105%
Time delay
0.000~10.000 (s)
Accuracy
1%Setting+30ms
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~20.000 (s)
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~20.000 (s)
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~20.000 (s)
Un~2Unn (V)
Accuracy
2-9
Date: 2015-10-21
2 Technical Data
Resetting ratio
95%
Time delay
0.000~30.000 (s)
0~Unn (V)
Accuracy
Resetting ratio
105%
Time delay
0.000~30.000 (s)
2~200 (V)
Accuracy
Resetting ratio
95%
Time delay
0.000~3600.000 (s)
0~Un (V)
Accuracy
Resetting ratio
95%
Time delay
0.000~30.000 (s)
50.00~65.00 (Hz)
Accuracy
0.02Hz
Time delay
0.000~100.000 (s)
Accuracy
45.00~60.00 (Hz)
Accuracy
0.02Hz
Time delay
0.000~100.000 (s)
Accuracy
2-10
Date: 2015-10-21
2 Technical Data
df/dt blocking setting range
0.200~20.000 (Hz/s)
Accuracy
0.02Hz/s
<20ms
Drop-off time
<20ms
0.050In~30.000In (A)
0.050In~30.000In (A)
0.050In~30.000In (A)
Accuracy
0.000~10.000 (s)
0.000~10.000 (s)
0.050In~30.000In (A)
Accuracy
0.100~100.000 (min)
1.000~3.000
1.000~3.000
Resetting ratio
95%
Drop-off time
<30ms
Time accuracy
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
Time delay
0.000~10.000 (s)
Accuracy
0.050In~30.000In
Accuracy
Resetting ratio
95%
Time delay
0.000~10.000s
Accuracy
1%Setting+30ms
0.050In~30.000In (A)
0.050In~30.000In (A)
Accuracy
Resetting ratio
95%
2-11
Date: 2015-10-21
2 Technical Data
Time delay
0.000~600.000 (s)
Accuracy
0.20~1.00
Accuracy
2.5% of setting
Resetting ratio
95%
Time delay
0.000~600.000 (s)
Accuracy
1%Setting+30ms
0.100In~50.000In
Accuracy
Resetting ratio
95%
Time delay
0.010~300.000 (s)
Accuracy
1%Setting+30ms
2.10.20 Auto-reclosing
Phase difference setting range
0~89 (Deg)
Accuracy
2.0Deg
0.02Un~0.8Un (V)
Accuracy
Max(0.01Un, 2.5%)
0.02~1 (Hz)
Accuracy
0.01Hz
1%Setting+20ms
1%Setting+20ms
1%Setting+20ms
< 2.5%
Tolerance will be higher in case of single-phase fault with high ground resistance.
2-12
Date: 2015-10-21
3 Operation Theory
3 Operation Theory
Table of Contents
3 Operation Theory .............................................................................. 3-a
3.1 System Parameters ......................................................................................... 3-1
3.1.1 General Application.............................................................................................................. 3-1
3.1.2 Function Description ............................................................................................................ 3-1
3.1.3 Settings ................................................................................................................................ 3-1
3-a
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
3 Operation Theory
List of Figures
Figure 3.3-1 Logic diagram of frequency calculation.............................................................. 3-3
Figure 3.4-1 Logic diagram of CB position supervision ......................................................... 3-6
Figure 3.4-2 Logic diagram of trip&closing circuit supervision ............................................ 3-6
Figure 3.4-3 Logic diagram of circuit breaker position ........................................................... 3-7
Figure 3.5-1 Flow chart of protection program ...................................................................... 3-12
Figure 3.5-2 Logic diagram of fault detector .......................................................................... 3-13
Figure 3.6-1 Logic diagram of auxiliary element.................................................................... 3-21
Figure 3.7-1 Operating time of single-phase fault (50Hz, SIR=1) ......................................... 3-25
Figure 3.7-2 Operating time of single-phase fault (60Hz, SIR=1) ......................................... 3-26
Figure 3.7-3 Operating time of two-phase fault (50Hz, SIR=1) ............................................. 3-26
Figure 3.7-4 Operating time of two-phase fault (60Hz, SIR=1) ............................................. 3-27
Figure 3.7-5 Operating time of three-phase fault (50Hz, SIR=1) ........................................... 3-27
Figure 3.7-6 Operating time of three-phase fault (60Hz, SIR=1) ........................................... 3-28
Figure 3.7-7 Operating time of single-phase fault (50Hz, SIR=30) ....................................... 3-28
Figure 3.7-8 Operating time of single-phase fault (60Hz, SIR=30) ....................................... 3-29
Figure 3.7-9 Operating time of two-phase fault (50Hz, SIR=30) ........................................... 3-29
Figure 3.7-10 Operating time of two-phase fault (60Hz, SIR=30) ......................................... 3-30
Figure 3.7-11 Operating time of three-phase fault (50Hz, SIR=30) ....................................... 3-30
Figure 3.7-12 Operating time of three-phase fault (60Hz, SIR=30) ....................................... 3-31
Figure 3.7-13 Operation characteristic for forward fault....................................................... 3-32
Figure 3.7-14 Operation characteristic for reverse fault ....................................................... 3-33
Figure 3.7-15 Logic diagram of DPFC distance protection................................................... 3-34
Figure 3.7-16 Distance element with load trapezoid.............................................................. 3-35
Figure 3.7-17 Phase-to-ground operation characteristic for forward fault ......................... 3-37
Figure 3.7-18 Phase-to-phase operation characteristic for forward fault ........................... 3-38
Figure 3.7-19 Operation characteristic for reverse fault ....................................................... 3-40
Figure 3.7-20 Steady-state characteristic of three-phase short-circuit fault ...................... 3-40
3-i
3 Operation Theory
3 Operation Theory
Figure 3.8-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm .... 3-81
Figure 3.8-3 Connect to a communication network via communication convertor........... 3-81
Figure 3.8-4 Connect to a communication network via MUX-64 .......................................... 3-81
Figure 3.8-5 Connect to a communication network via MUX-2M ......................................... 3-82
Figure 3.8-6 Schematic diagram of communication channel time ...................................... 3-84
Figure 3.8-7 Logic diagram of differential protection enabling alarm ................................. 3-86
Figure 3.8-8 Logic diagram of receiving signal n .................................................................. 3-86
Figure 3.9-1 Operation characteristic of DPFC current differential element ...................... 3-89
Figure 3.9-2 Operation characteristic of DPFC current differential element ...................... 3-90
Figure 3.9-3 Operation characteristic of steady-state current differential element ........... 3-91
Figure 3.9-4 Operation characteristic of steady-state current differential element ........... 3-92
Figure 3.9-5 Operation characteristic of neutral current differential element .................... 3-93
Figure 3.9-6 equivalent circuit ........................................................................................... 3-94
Figure 3.9-7 Equivalent circuit of shunt reactor .................................................................... 3-95
Figure 3.9-8 Relation between CT saturation differential current and restraint current ... 3-96
Figure 3.9-9 Enabling/disabling logic of current differential protection ............................. 3-99
Figure 3.9-10 Differential condition of current differential protection .............................. 3-100
Figure 3.9-11 DPFC differential element of current differential protection ....................... 3-101
Figure 3.9-12 Steady-state differential element of current differential protection ........... 3-102
Figure 3.9-13 Neutral current differential element of current differential protection ...... 3-103
Figure 3.9-14 Differential inter-trip element of current differential protection ................. 3-104
Figure 3.9-15 Weak infeed logic of current differential protection .................................... 3-104
Figure 3.9-16 Sending permissive signal of current differential protection ..................... 3-105
Figure 3.9-17 Self-check of current differential protection ................................................. 3-105
Figure 3.10-1 Enabling/disabling logic of pilot distance protection .................................. 3-108
Figure 3.10-2 Logic diagram of receiving signal.................................................................. 3-109
Figure 3.10-3 Zone extension ................................................................................................. 3-109
Figure 3.10-4 Simple schematic of PUTT .............................................................................. 3-110
Figure 3.10-5 Logic diagram of pilot distance protection (PUTT) .......................................3-111
Figure 3.10-6 Simple schematic of POTT ..............................................................................3-111
3-k
3 Operation Theory
Figure 3.10-7 Logic diagram of pilot distance protection (POTT) ...................................... 3-112
Figure 3.10-8 Simple schematic of system fault .................................................................. 3-113
Figure 3.10-9 Simple schematic of blocking ........................................................................ 3-113
Figure 3.10-10 Logic diagram of pilot distance protection (Blocking) .............................. 3-114
Figure 3.10-11 Logic diagram of pilot distance protection (Unblocking) .......................... 3-114
Figure 3.10-12 Current reversal ............................................................................................. 3-115
Figure 3.10-13 Logic diagram of current reversal blocking ............................................... 3-116
Figure 3.10-14 Line fault description..................................................................................... 3-116
Figure 3.10-15 Weak infeed logic during pickup .................................................................. 3-117
Figure 3.10-16 Weak infeed logic without pickup ................................................................ 3-117
Figure 3.10-17 Simplified CB echo logic for POTT .............................................................. 3-118
Figure 3.11-1 Enabling/disabling logic of pilot directional earth-fault protection ........... 3-121
Figure 3.11-2 Logic diagram of receiving signal .................................................................. 3-122
Figure 3.11-3 Forward/reverse direction of zero-sequence power .................................... 3-122
Figure 3.11-4 Simple schematic of DEF (permissive scheme) ........................................... 3-123
Figure 3.11-5 Logic diagram of DEF (permissive scheme) ................................................. 3-123
Figure 3.11-6 Simple schematic of blocking ........................................................................ 3-124
Figure 3.11-7 Logic diagram of DEF (Blocking scheme)..................................................... 3-125
Figure 3.11-8 Logic diagram for unblocking ........................................................................ 3-125
Figure 3.12-1 Line fault description ....................................................................................... 3-128
Figure 3.12-2 Vector diagram of current and voltage .......................................................... 3-129
Figure 3.12-3 Vector diagram of zero-sequence power ...................................................... 3-131
Figure 3.13-1 Logic diagram of phase overcurrent protection .......................................... 3-138
Figure 3.14-1 Logic diagram of earth fault protection (stage 1) ......................................... 3-147
Figure 3.14-2 Logic diagram of earth fault protection (stage x) ......................................... 3-148
Figure 3.15-1 Logic diagram of negative-sequence overcurrent protection .................... 3-158
Figure 3.15-2 Logic diagram of stage 4 of negative-sequence overcurrent protection .. 3-159
Figure 3.16-1 Logic diagram of overcurrent protection for VT circuit failure................... 3-168
Figure 3.17-1 Logic diagram of phase current SOTF protection ....................................... 3-172
Figure 3.18-1 Logic diagram of residual current SOTF protection .................................... 3-175
3-l
3 Operation Theory
3 Operation Theory
3 Operation Theory
List of Tables
Table 3.1-1 System parameters .................................................................................................. 3-1
Table 3.2-1 Line parameters ....................................................................................................... 3-2
Table 3.3-1 I/O signals of frequency calculation ...................................................................... 3-3
Table 3.4-1 I/O signals of CB position supervision.................................................................. 3-5
Table 3.4-2 Internal settings of CB position supervision ........................................................ 3-7
Table 3.5-1 I/O signals of fault detector .................................................................................. 3-12
Table 3.5-2 Settings of fault detector ...................................................................................... 3-13
Table 3.6-1 I/O signals of auxiliary element ............................................................................ 3-16
Table 3.6-2 Settings of auxiliary element ................................................................................ 3-21
Table 3.7-1 I/O signals of DPFC distance protection ............................................................. 3-34
Table 3.7-2 Settings of DPFC distance protection ................................................................. 3-34
Table 3.7-3 I/O signals of load encroachment ........................................................................ 3-36
Table 3.7-4 Settings of load encroachment ............................................................................ 3-36
Table 3.7-5 I/O signals of distance protection (Mho) ............................................................. 3-43
Table 3.7-6 Settings of distance protection (Mho) ................................................................. 3-46
3-o
3 Operation Theory
3 Operation Theory
3 Operation Theory
3-r
3 Operation Theory
3.1.3 Settings
Table 3.1-1 System parameters
No.
Name
Range
Step
Unit
Active_Grp
1~10
Opt_SysFreq
50 or 60
PrimaryEquip_Name
U1n
10.00~65500.00
0.01
kV
U2n
80.00~220.00
0.01
CBx.I1n
100~30000
Remark
Active setting group
Hz
System frequency
The name of primary equipment
Primary rated value of VT (phase to
phase)
Secondary rated value of VT (phase to
phase)
Primary rated value of CT corresponding
to circuit breaker No.x
Primary calculation base rated current of
I1n_Base
100~30000
I2n_Base
1 or 5
Secondary
calculation
base
rated
current of CT
Frequency upper limit setting
f_High_FreqAlm
50~65
Hz
The
device
will
issue
an
alarm
10
f_Low_FreqAlm
45~60
Hz
The
device
will
issue
an
alarm
3-1
3 Operation Theory
3.2.3 Settings
Table 3.2-1 Line parameters
No.
Name
Range
Step
Unit
X1L
(0.000~4Unn)/In
0.001
ohm
R1L
(0.000~4Unn)/In
0.001
ohm
X0L
(0.000~4Unn)/In
0.001
ohm
R0L
(0.000~4Unn)/In
0.010
ohm
X0M
(0.000~4Unn)/In
0.001
ohm
R0M
(0.000~4Unn)/In
0.01
ohm
LineLength
0.00~655.35
0.01
km
Remark
Positive-sequence reactance of the whole
line (secondary value)
Positive-sequence resistance of the whole
line (secondary value)
Zero-sequence reactance of the whole line
(secondary value)
Zero-sequence resistance of the whole line
(secondary value)
Zero-sequence
mutual
reactance
(secondary value)
Zero-sequence mutual resistance of the
whole line (secondary value)
Total length of the whole line
3 Operation Theory
algorithms and the performance of protection functions. For the power system using 50Hz or 60Hz
as reference frequency, the frequency track function can be disabled if the fluctuation of the
frequency range is not great. For the power system that the fluctuation of the frequency range is
great, the frequency track function can be enabled to improve protection performance.
It adopts the positive-sequence voltage which derived from protection used voltage as the
calculation reference, the positive-sequence voltage can be calculated as following:
U1 (U a U b e j120 U c e j 240) / 3
When no VT is connected to the device, the frequency track function is disabled automatically, and
then the device calculates protection algorithm using the system reference frequency. When the
device detects a fault happening to the power system or the voltage is smaller than 0.15Un, the
frequency track function is disabled.
f
Alm_Freq
Input Signal
FreqTrack
fn
No.
Description
It is used to enabled or disable frequency track function by the configuration
software PCS-Explorer.
It is the system frequency, which is decided by the setting [Opt_SysFreq].
Output Signal
Description
Alm_Freq
3.3.5 Logic
SIG
U3P
SIG
fn
SIG
FreqTrack
SIG
f<[f_Low_FreqAlm]
SIG
f>[f_High_FreqAlm]
Frequency
calculation
>=1
Alm_Freq
3-3
3 Operation Theory
CBx.Alm_52b
CBx.52b_PhB
CBx.52b_PhC
CBx.ManCls
CBx.Test
2.
3-4
3 Operation Theory
CB Position Supervision
CBx.52b
CBx.Alm_52b
CBx.ManCls
CBx.Test
3.
CBx.TCCS.Alm
CBx.52b
CBx.TCCS.Input
CBx.ManCls
CBx.Test
TCCS will be disabled automatically when it is used for phase-segregated circuit breaker. x=1 or 2
Input Signal
Description
CBx.52b_PhA
CBx.52b_PhB
CBx.52b_PhC
CBx.Test
should be set as 1 in fixed, and CB No.x will be not take effect in corresponding
protection logics. (CB position supervision is still kept.) It is only available for
double circuit breakers mode.
External manual closing binary input of circuit breaker No.x, it is only applied to
CBx.ManCls
CBx.52b
CBx.52a
SOTF logic
Control circuit failure of circuit breaker No.x (normally closed contacts of tripping
8
CBx.TCCS.Input
position (52b) and closing position (52a) of three-phase circuit breaker are all
de-energized due to DC power loss of control circuit)
No.
Output Signal
Description
CBx.Alm_52b
CBx.TCCS.Alm
3-5
3 Operation Theory
NOTICE!
The signal [CBx.52a] only take effect in the tripping/closing circuit supervision and not
affect any protection function. Only if tripping/closing circuit supervision is configured,
this signal needs to be connected to the device.
3.4.5 Logic
[CBx.52b_PhA]
BI
>=1
&
&
[CBx.52b_PhB]
BI
>=1
&
&
>=1
10s
BI
[CBx.52b_PhC]
BI
[CBx.52b]
>=1
>=1
10s
CBx.Alm_52b
&
&
SIG
CBx.Ia>I_Line
&
SIG
>=1
CBx.Ib>I_Line
&
SIG
CBx.Ic>I_Line
BI
[CBx.52a]
BI
[CBx.52b]
BI
[CBx.TCCS.Input]
>=1
>=1
[CBx.TCCS.t_DPU]
[CBx.TCCS.t_DDO]
CBx.TCCS.Alm
3-6
3 Operation Theory
BI
[CB1.52b_PhA]
>=1
&
52b_PhA
BI
[CB1.52b_PhB]
BI
[CB1.52b_PhC]
BI
[CB1.52b]
BI
[CB1.Test]
BI
[CB2.52b_PhA]
>=1
BI
[CB2.52b_PhB]
>=1
BI
[CB2.52b_PhC]
BI
[CB2.52b]
BI
[CB2.Test]
>=1
>=1
&
52b_PhB
&
>=1
52b_PhC
x=1 or 2
I_Line is threshold value used to determine whether line is on-load or no-load. Default value
0.06In.
3.4.6 Settings
Table 3.4-2 Internal settings of CB position supervision
No.
Name
Default Value
Unit
CBx.TCCS.t_DPU
0.5
CBx.TCCS.t_DDO
0.5
Remark
Pickup delay time of control circuit failure alarm for
circuit breaker No.x (x=1 or 2)
Dropoff delay time of control circuit failure alarm for
circuit breaker No.x (x=1 or 2)
3 Operation Theory
Otherwise, the output relays would not operate. An alarm message will be issued with blocking
outputs if a protection element operates while the fault detector does not operate.
Fault detector based on DPFC current: DPFC current is greater than the setting value
2.
Fault detector based on residual current: Residual current is greater than the setting value
3.
4.
Fault detector based on phase current: Phase current is greater than the setting value
5.
Fault detector based on voltage: Phase voltage or phase-to-phase voltage is greater than the
setting value
6.
Fault detector based on circuit breaker position: Circuit breaker position discrepancy
7.
Fault detector based on weak infeed logic or inter-trip logic of current differential protection:
Weak infeed logic or inter-trip logic of current differential protection pickup
8.
9.
If any of the above conditions is complied, FD will operate to activate the output circuit providing
DC power supply to the output relays. The fault detector based on DPFC current and the fault
detector based on residual current are always enabled, and all protection functions are permitted
to operate when they operate.
3.5.2.1 Fault Detector Based on DPFC Current
DPFC phase-to-phase current is obtained by subtracting the phase-to-phase current from that of a
cycle before.
3-8
3 Operation Theory
200
100
0
-100
-200
20
40
60
Original Current
80
100
120
20
40
60
DPFC current
80
100
120
100
50
0
-50
-100
From above figures, it is concluded that DPFC can reflect the sudden change of current at the
initial stage of a fault and has a perfect performance of fault detection.
It is used to determine whether this pickup condition is met according to Equation 3.5-1.
For multi-phase short-circuit fault, DPFC phase-to-phase current has high sensitivity to ensure the
pickup of protection device. For usual single phase to earth fault, it also has sufficient sensitivity to
pick up except the earth fault with very large fault resistance. Under this condition, DPFC current is
relative small, however, residual current is also used to judge pickup condition.
This element adopts adaptive floating threshold varied with the change of load current
continuously. The change of load current is small and steadily under normal or power swing
condition, the adaptive floating threshold with the ISet is higher than the change of current under
these conditions and hence maintains the element stability.
The criterion is:
IMAX>1.25ITh+ISet
Equation 3.5-1
Where:
IMAX: The maximum half-wave integration value of phase-to-phase current (=AB, BC, CA)
ISet: The fixed threshold value (i.e. the setting [FD.DPFC.I_Set])
ITh: The floating threshold value
The coefficient, 1.25, is an empirical value which ensures the threshold always higher than the
unbalance output value of the system.
If operation condition is met, the fault detector based on DPFC current will operate to provide DC
power supply for output relays, the pickup signal will maintain 7s after the fault detector based on
DPFC current drops off.
3-9
3 Operation Theory
3-10
3 Operation Theory
2.
3.
Hardware self-check
4.
5.
6.
Channel supervision
Once the protection fault detector element in protection calculation DSP picks up, the protection
device will switch to fault calculation program, for example the calculation of distance protection,
and to determine logic. If the fault is within the protected zone, the protection device will send
tripping command.
The protection program flow chart is shown as Figure 3.5-1.
3-11
3 Operation Theory
Main program
Sampling program
No
Yes
Pickup?
Regular program
The protection FD pickup conditions are the same as the FD in fault detector DSP as shown below.
The operation criteria for the conditions are also the same as that in fault detector DSP. Please
refer to section 3.5.2 for details.
Output Signal
Description
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
FD.NOC.Pkp
3-12
3 Operation Theory
3.5.6 Logic
SIG
Ia
SIG
Ib
SIG
Ic
Iab>[FD.DPFC.I_Set]
>=1
Ibc>[FD.DPFC.I_Set]
FD.DPFC.Pkp
Ica>[FD.DPFC.I_Set]
>=1
0s
3I0>[FD.ROC.3I0_Set]
I2>[FD.NOC.I2_Set]
7s
FD.Pkp
FD.ROC.Pkp
&
FD.NOC.Pkp
EN
FD.NOC.En
3.5.7 Settings
Table 3.5-2 Settings of fault detector
No.
Name
Range
Step
Unit
FD.DPFC.I_Set
(0.050~30.000)In
0.001
FD.ROC.3I0_Set
(0.050~30.000)In
0.001
FD.NOC.I2_Set
(0.050~30.000)In
0.001
Remark
Current setting of DPFC current fault
detector element
Current setting of residual current fault
detector element
Current setting of negative-sequence
current fault detector element
Enabling/disabling negative-sequence
FD.NOC.En
0 or 1
0: disable
1: enable
3-13
3 Operation Theory
It shares DPFC current element of DPFC fault detector. If DPFC fault detector operates
(FD.DPFC.Pkp=1) and current change auxiliary element is enabled, current change auxiliary
element operates.
2.
There are 3 stages for residual current auxiliary element (AuxE.ROC1, AuxE.ROC2 and
AuxE.ROC3). Each residual current auxiliary element will operate instantly if calculated residual
current amplitude is larger than corresponding current setting
The criteria are:
AuxE.ROC1: 3I0>[AuxE.ROC1.3I0_Set]
AuxE.ROC2: 3I0>[AuxE.ROC2.3I0_Set]
AuxE.ROC3: 3I0>[AuxE.ROC3.3I0_Set]
Where:
3I0: The calculated residual current
3.
There are 3 stages for phase current auxiliary element (AuxE.OC1, AuxE.OC2 and AuxE.OC3).
Each phase current auxiliary element will operate instantly if phase current amplitude is larger than
corresponding current setting.
The criteria are:
AuxE.OC1: IMAX>[AuxE.OC1.I_Set]
AuxE.OC2: IMAX>[AuxE.OC2.I_Set]
AuxE.OC3: IMAX>[AuxE.OC3.I_Set]
Where:
IMAX: The maximum phase current among three phases
4.
3-14
3 Operation Theory
AuxE.UVG will operate instantly if any phase-to-ground voltage is lower than corresponding
voltage setting.
The criterion is:
UMIN<[AuxE.UVG.U_Set]
Where:
UMIN: The minimum value among three phase-to-ground voltages
6.
AuxE.UVS will operate instantly if any phase-to-phase voltage is lower than corresponding voltage
setting.
The criterion is:
UMIN<[AuxE.UVS.U_Set]
Where:
UMIN: The minimum value among three phase-to-phase voltages
7.
AuxE.ROV will operate instantly if calculated residual voltage is larger than corresponding voltage
setting.
The criterion is:
3U0>[AuxE.ROV.3U0_Set]
Where:
3U0: The calculated residual voltage
3-15
3 Operation Theory
AuxE.St
AuxE.OCD.Blk
AuxE.OCD.St_Ext
AuxE.ROCm.En
AuxE.OCD.On
AuxE.ROCm.Blk
AuxE.ROCm.St
AuxE.OCm.En
AuxE.ROCm.On
AuxE.OCm.Blk
AuxE.OCm.St
AuxE.UVD.En
AuxE.OCm.StA
AuxE.UVD.Blk
AuxE.OCm.StB
AuxE.UVG.En
AuxE.OCm.StC
AuxE.UVG.Blk
AuxE.OCm.On
AuxE.UVS.En
AuxE.UVD.St
AuxE.UVS.Blk
AuxE.UVD.St_Ext
AuxE.ROV.En
AuxE.UVD.On
AuxE.ROV.Blk
AuxE.UVG.St
AuxE.UVG.StA
AuxE.UVG.StB
AuxE.UVG.StC
AuxE.UVG.On
AuxE.UVS.St
AuxE.UVS.StAB
AuxE.UVS.StBC
AuxE.UVS.StCA
AuxE.UVS.On
AuxE.ROV.St
AuxE.ROV.On
Input Signal
AuxE.OCD.En
Description
Current change auxiliary element enabling input, it is triggered from binary input or
3-16
3 Operation Theory
programmable logic etc.
2
AuxE.OCD.Blk
AuxE.ROC1.En
AuxE.ROC1.Blk
AuxE.ROC2.En
AuxE.ROC2.Blk
AuxE.ROC3.En
AuxE.ROC3.Blk
AuxE.OC1.En
10
AuxE.OC1.Blk
11
AuxE.OC2.En
12
AuxE.OC2.Blk
13
AuxE.OC3.En
14
AuxE.OC3.Blk
15
AuxE.UVD.En
16
AuxE.UVD.Blk
17
AuxE.UVG.En
18
AuxE.UVG.Blk
19
AuxE.UVS.En
20
AuxE.UVS.Blk
21
AuxE.ROV.En
22
AuxE.ROV.Blk
Current change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Stage 1 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Stage 3 of phase current auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from binary input or
programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from binary input or
programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Residual voltage auxiliary element enabling input, it is triggered from binary input
or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from binary input
or programmable logic etc.
3-17
3 Operation Theory
No.
Output Signal
Description
AuxE.St
AuxE.OCD.St_Ext
AuxE.OCD.On
AuxE.ROC1.St
AuxE.ROC1.On
AuxE.ROC2.St
AuxE.ROC2.On
AuxE.ROC3.St
AuxE.ROC3.On
10
AuxE.OC1.St
11
AuxE.OC1.StA
12
AuxE.OC1.StB
13
AuxE.OC1.StC
14
AuxE.OC1.On
15
AuxE.OC2.St
16
AuxE.OC2.StA
17
AuxE.OC2.StB
18
AuxE.OC2.StC
19
AuxE.OC2.On
20
AuxE.OC3.St
21
AuxE.OC3.StA
22
AuxE.OC3.StB
23
AuxE.OC3.StC
24
AuxE.OC3.On
25
AuxE.UVD.St
26
AuxE.UVD.St_Ext
27
AuxE.UVD.On
28
AuxE.UVG.St
29
AuxE.UVG.StA
30
AuxE.UVG.StB
31
AuxE.UVG.StC
32
AuxE.UVG.On
33
AuxE.UVS.St
34
AuxE.UVS.StAB
35
AuxE.UVS.StBC
36
AuxE.UVS.StCA
37
AuxE.UVS.On
38
AuxE.ROV.St
39
AuxE.ROV.On
3-18
3 Operation Theory
3.6.5 Logic
SIG AuxE.OCD.En
&
SIG AuxE.OCD.Blk
AuxE.OCD.On
EN
&
AuxE.OCD.En
0s [AuxE.OCD.t_DDO]
AuxE.OCD.St_Ext
SIG FD.DPFC.Pkp
SET 3I0>[AuxE.ROCm.3I0_Set]
SIG
AuxE.ROCm.En
SIG
AuxE.ROCm.Blk
EN
AuxE.ROCm.En
SIG
AuxE.OCm.En
SIG
AuxE.OCm.Blk
EN
AuxE.OCm.En
&
AuxE.ROCm.St
&
AuxE.ROCm.On
&
AuxE.OCm.On
SET Ia>[AuxE.OCm.I_Set]
&
AuxE.OCm.StA
SET Ib>[AuxE.OCm.I_Set]
&
AuxE.OCm.StB
SET Ic>[AuxE.OCm.I_Set]
&
AuxE.OCm.StC
SET Ia>[AuxE.OCm.I_Set]
&
>=1
AuxE.OCm.St
SET Ib>[AuxE.OCm.I_Set]
SET Ic>[AuxE.OCm.I_Set]
3-19
3 Operation Theory
SET
Ua>[AuxE.UVD.U_Set]
SET
Ub>[AuxE.UVD.U_Set]
SET
Uc>[AuxE.UVD.U_Set]
SIG
AuxE.UVD.En
SIG
AuxE.UVD.Blk
EN
AuxE.UVD.En
SIG
AuxE.UVG.En
SIG
AuxE.UVG.Blk
EN
AuxE.UVG.En
SET
UA<[AuxE.UVG.U_Set]
>=1
&
AuxE.UVD.St
0s
[AuxE.UVD.t_DDO]
AuxE.UVD.St_Ext
&
AuxE.UVD.On
&
AuxE.UVG.On
&
AuxE.UVG.StA
SET
UB<[AuxE.UVG.U_Set]
&
AuxE.UVG.StB
SET
UC<[AuxE.UVG.U_Set]
&
AuxE.UVG.StC
SET
UA<[AuxE.UVG.U_Set]
SET
UB<[AuxE.UVG.U_Set]
SET
UC<[AuxE.UVG.U_Set]
SIG
AuxE.UVS.En
SIG
AuxE.UVS.Blk
EN
AuxE.UVS.En
SET
UA<[AuxE.UVS.U_Set]
&
AuxE.UVG.St
>=1
&
AuxE.UVS.On
&
AuxE.UVS.StA
SET
UB<[AuxE.UVS.U_Set]
&
AuxE.UVS.StB
SET
UC<[AuxE.UVS.U_Set]
&
AuxE.UVS.StC
SET
UA<[AuxE.UVS.U_Set]
SET
UB<[AuxE.UVS.U_Set]
SET
UC<[AuxE.UVS.U_Set]
&
>=1
AuxE.UVS.St
3-20
3 Operation Theory
SIG
3U0>[AuxE.ROV.3U0_Set]
SIG
AuxE.ROV.En
SIG
AuxE.ROV.Blk
EN
AuxE.ROV.En
SIG
AuxE.OCD.St_Ext
SIG
AuxE.ROC1.St
SIG
AuxE.ROC2.St
SIG
AuxE.ROC3.St
SIG
AuxE.OC1.St
SIG
AuxE.OC2.St
SIG
AuxE.OC3.St
SIG
AuxE.UVD.St_Ext
SIG
AuxE.UVG.St
SIG
AuxE.UVS.St
SIG
AuxE.ROV.St
&
AuxE.ROV.St
&
AuxE.ROV.On
>=1
>=1
>=1
AuxE.St
>=1
>=1
>=1
>=1
Where:
m=1, 2, 3
Calculate residual current: 3I0=Ia+Ib+Ic
Calculate DPFC phase voltage: Ua=(Ua-Ufa), Ub=(Ub-Ufb), Uc=(Uc-Ufc)
Calculate residual voltage: 3U0=Ua+Ub+Uc
3.6.6 Settings
Table 3.6-2 Settings of auxiliary element
No.
1
Name
AuxE.OCD.t_DDO
Range
0.000~10.000
Step
Unit
0.001
Remark
Drop-off time delay of current change
auxiliary element
Enabling/disabling current change
AuxE.OCD.En
auxiliary element
0 or 1
0: disable
1: enable
AuxE.ROC1.3I0_Set
(0.050~30.000)In
0.001
3-21
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Enabling/disabling stage 1 residual
AuxE.ROC1.En
0 or 1
0: disable
1: enable
AuxE.ROC2.3I0_Set
(0.050~30.000)In
0.001
AuxE.ROC2.En
0 or 1
0: disable
1: enable
AuxE.ROC3.3I0_Set
(0.050~30.000)In
0.001
AuxE.ROC3.En
0 or 1
0: disable
1: enable
AuxE.OC1.I_Set
(0.050~30.000)In
auxiliary element
Enabling/disabling stage 1 phase
10
AuxE.OC1.En
0 or 1
0: disable
1: enable
11
AuxE.OC2.I_Set
(0.050~30.000)In
auxiliary element
Enabling/disabling stage 2 phase
12
AuxE.OC2.En
0 or 1
0: disable
1: enable
13
AuxE.OC3.I_Set
(0.050~30.000)In
auxiliary element
Enabling/disabling stage 3 phase
14
AuxE.OC3.En
0 or 1
0: disable
1: enable
15
AuxE.UVD.U_Set
0~Un
0.001
16
AuxE.UVD.t_DDO
0.000~10.000
0.001
17
AuxE.UVD.En
auxiliary element
0 or 1
0: disable
1: enable
18
AuxE.UVG.U_Set
0~Un
0.001
3-22
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
under voltage auxiliary element
Enabling/disabling phase-to-ground
19
AuxE.UVG.En
0 or 1
0: disable
1: enable
20
AuxE.UVS.U_Set
0~Unn
0.001
21
AuxE.UVS.En
0 or 1
0: disable
1: enable
22
AuxE.ROV.3U0_Set
0~Un
0.001
23
AuxE.ROV.En
auxiliary element
0 or 1
0: disable
1: enable
2.
3.
3 Operation Theory
5.
6.
7.
Load encroachment
It is used to prevent all distance elements from undesired trip due to load encroachment
under heavy load condition especially for long lines.
8.
9.
3-24
3 Operation Theory
transformer, voltage transformer and inaccuracies of line parameter from which the relay settings
are calculated. It is recommended the zone 1 reach is set to 80%~85% of the protected line in
consideration the aforesaid errors and safety margin to prevent instantaneously tripping for faults
on adjacent lines. The remaining 20% of the protected line relies on the zone 2 distance elements.
With the pilot scheme distance protection, fast fault clearance could also be achieved for end zone
faults at both ends of the protected line.
The general rule for zone 2 impedance reach setting is set to cover the protected line plus 20% of
the adjacent line. However, the coverage of adjacent line should be extended in the presence of
additional infeed at the remote end of the protected line to ensure 20% coverage of adjacent line.
This assures the fast operation of zone 2 distance element for faults at the remote end of the
protected line since the fault is well within zone 2 reach. This is important for pilot protection as the
impedance reach of pilot zone is the same as that of zone 2 distance element. In a parallel line
situation, a fault cleared sequentially on a line may cause current reversal in the healthy line. If the
pilot zone settings are set to cover 50% of adjacent line and the POTT or Blocking scheme is used,
the current reversal in the healthy line could cause relay mal-operation. Therefore, current reversal
logic is required and explained in section 3.10.2.6.
For different system impedance ratio (SIR), the operating time of distance protection for different
fault location are shown as the following figures.
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-25
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-26
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
35
30
25
Operating Time (ms)
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-27
3 Operation Theory
30
25
Operating Time (ms)
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
33
32.5
32
Operating Time (ms)
31.5
31
30.5
30
29.5
29
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
3-28
3 Operation Theory
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
45
40
35
Operating Time (ms)
30
25
20
15
10
5
0
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-29
3 Operation Theory
35
30
Operating Time (ms)
25
20
15
10
5
0
0%
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
33
32
Operating Time (ms)
31
30
29
28
27
0
10%
20%
30%
40%
50%
60%
70%
80%
90%
100%
3-30
3 Operation Theory
27.5
27
Operating Time (ms)
26.5
26
25.5
25
24.5
24
23.5
0%
10%
20%
30%
40%
50%
60%
70%
80%
90% 100%
3-31
3 Operation Theory
EM
EN
I
ZS
ZK
jX
Zzd
Zk
Zs+Zk
-Zs
Where:
ZZD: the setting of DPFC distance protection
ZS: total impedance between local system and device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [21-1.phi1_Reach]
Figure 3.7-13 shows the operation characteristic of DPFC distance protection on R-X plane when
a fault occurs in forward direction, which is the circle with the Zs as the center and theZs+Zzd as
the radius. When measured impedance Z k is in the circle, DPFC distance protection will operate.
DPFC distance protection has a larger capability of enduring fault resistance than distance
protection using positive-sequence as polarized voltage.
3-32
3 Operation Theory
ZZD
F
EM
EN
I
ZK
ZS
jX
Z's
Zzd
-Zk
21D
21D.En
21D.Op
21D.Blk
21D.On
3-33
3 Operation Theory
Input Signal
21D.En
21D.Blk
No.
Description
DPFC distance protection enabling input, it is triggered from binary input or
programmable logic etc.
DPFC distance protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
21D.Op
21D.On
3.7.3.4 Logic
[21D.En]
EN
21D.On
&
SIG
21D.En
SIG
21D.Blk
SIG
FD.Pkp
EN
[VTS.En_Out_VT]
SIG
SIG
SET
[21D.Z_Set]<0.05/In
SET
Z<[21D.Z_Set]
SIG
UP<0.85Un
SET
Z<[21D.Z_Set]
SIG
UPP<0.85Unn
SIG
PD signal
&
>=1
&
>=1
&
21D.Op
&
&
NOTICE!
PD signal only blocks DPFC distance element of corresponding phase (i.e. broken
phase), and healthy phases (operation phases) are not affected.
3.7.3.5 Settings
Table 3.7-2 Settings of DPFC distance protection
No.
1
Name
21D.Z_Set
Range
Step
Unit
(0.000~4Unn)/In
0.001
ohm
3-34
Remark
Impedance setting of DPFC distance
protection
PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
21D.En
DPFC
distance
protection
0 or 1
0: disable
1: enable
jX
Load
Load
Load Area
Load Area
R
RLoad
RLoad
Two settings are equipped to exclude the encroachment of the load impedance:
RLoad: the minimum load resistance
Load: the load area angle
These values are common for all zones.
3-35
3 Operation Theory
LoadEnch
LoadEnch.En
LoadEnch.St
LoadEnch.Blk
LoadEnch.On
Input Signal
LoadEnch.En
LoadEnch.Blk
No.
Description
Load trapezoid characteristic enabling input, it is triggered from binary input or
programmable logic etc.
Load trapezoid characteristic blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
Measured impedance is inside the load area.
If load trapezoid characteristic is enabled and measured impedance is inside the
LoadEnch.St
LoadEnch.On
3.7.4.4 Settings
Table 3.7-4 Settings of load encroachment
No.
Name
Range
Step
Unit
Remark
Angle
setting
characteristic,
1
LoadEnch.phi
0~45
deg
of
it
load
should
trapezoid
be
set
(Load_Max),
Load_Max+5 is
recommended.
Resistance setting of load trapezoid
2
LoadEnch.R_Set
(0.05~200)/In
0.01
ohm
characteristic,
it
according
the
to
should
be
minimum
set
load
LoadEnch.En
load
trapezoid
characteristic
0,1
0: disable
1: enable
3-36
3 Operation Theory
EM
IN
EN
I
ZS
ZK
jX
ZZD
ZK
-2ZS/3
Where:
ZZD: the setting of distance protection
ZS: total impedance between local system and protective device location
ZK: measurement impedance
: positive-sequence sensitive angle, i.e. [21-x.phi1_Reach] (x=1, 2, 3, 4, 5)
Phase-to-neutral positive sequence voltage is used as polarized signal for phase-to-ground
distance protection. Phase-to-ground distance protection is controlled by the fault detector based
on residual current.
For zone 1, 2:
Operation voltage:
3-37
3 Operation Theory
Polarized voltage:
In short line, phase shift 1 could be applied to the polarized voltage to improve the performance
against high resistance fault. The device provides an angle-shift setting, [21Mx.ZG.phi_Shift], to
set value of 1 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1
are respectively shown as the impedance circle A, B and C in Figure 3.7-22. (x=1, 2)
For zone 3, 4, 5:
Operation voltage:
Polarized voltage:
UP uses phase positive-sequence voltage as polarized voltage. For earth fault, positive-sequence
voltage is mainly formed from healthy phases, basically retaining the phase of the
positive-sequence voltage before fault.
Phase comparison equation is:
The operation characteristic is shown in Figure 3.7-17. Operation characteristic of ZK on R-X plane
is a circle with line connecting ends of ZZD and -2ZS/3 as the diameter. The origin is enclosed in the
circle.
2.
ZZD
ZK
-ZS/2
3 Operation Theory
Operation voltage:
Polarized voltage:
Phase shift 2 could be applied to polarized voltage of zones 1 and 2 just like 1 in
phase-to-ground distance element. It is also used for improving performance against high
resistance fault in short line. The device provides an angle-shift setting, [21Mx.ZP.phi_Shift], to set
value of 2 among 0, 15and 30. Their impedance shift characteristics towards quadrant 1 are
respectively shown as the impedance circle A, B and C in Figure 3.7-22. (x=1, 2)
For zone 3, 4, 5:
Operation voltage:
Polarized voltage:
Phase-to-phase positive-sequence voltage is applied as the polarized voltage of this element.
Phase comparison equation is:
EN
I
ZK
ZS
3-39
3 Operation Theory
jX
Z'S
ZZD
R
-ZK
Z'S: total impedance between remote system and protective device location
jX
ZZD
ZK
Phase-to-phase distance protection is also used for three-phase short-circuit fault. The operation
characteristic is shown in Figure 3.7-20. Operation characteristic of ZK on R-X plane is a circle with
setting impedance ZZD as the diameter.
3-40
3 Operation Theory
jX
ZZD
ZK
R
Circle C
-ZS
Circle B
Circle A
Where:
ZZD: the setting of distance protection (zone x)
ZS: total impedance between local system and protective device location
ZK: measured impedance
: positive-sequence characteristic angle, i.e. [21-x.phi1_Reach] (x=1, 2, 3, 4, 5)
Circle A: transient characteristic
Circle B: steady-state characteristic shifting towards quadrant
Circle C: steady-state characteristic shifting towards quadrant
As shown in Figure 3.7-21, the characteristic of the distance protection for a three-phase fault on a
system is an impedance circle cross the origin, and there is a voltage dead zone around the origin.
In order to eliminate the dead zone of the distance protection for a close up three-phase fault
memorized positive-sequence voltage is adopted as polarized voltage when the
positive-sequence voltage drops down to 15%Un or below.
The transient (during process of memory) operation characteristic is shown as the impedance
circle A in the above figure. The circle takes Z ZD and -ZZS as diameter and thus the origin is within
the impedance circle. When three-phase fault happens in reverse direction, its transient
characteristic is shown in Figure 3.7-19, i.e. the distance protection has a clearly defined
directionality and no dead zone during the process of memory.
For phase-to-phase distance protection, if distance protection operates with memorized polarizing
voltage, this means a close up forward fault. When the memory fades out, the operation
characteristic will be reverse offset a little to enclose the origin as impedance circle B shown in
Figure 3.7-21 to ensure keeping operating of distance protection until the fault being cleared. If
distance protection does not operate with memorized polarizing voltage, it will be a close up
3-41
3 Operation Theory
reverse fault. When the memory fades out, the operation characteristic will be forward offset not to
enclose the origin as impedance circle C shown in Figure 3.7-21, and the distance protection will
not mal-operate even if voltage is zero.
The distance protection with such design thoroughly eliminates the dead zone when three-phase
close up fault occurs. It also has favorable directivity and will not operate for a reverse three-phase
fault at busbar.
When receiving manual closing signal or 3-pole reclosing signal, the operation characteristic of
phase to phase distance protection will always shift in reverse direction. It is ensured to enclose
the origin of impedance and without dead zone for three-phase fault, i.e. the reverse shift
impedance circle B shown in Figure 3.7-21.
jX
B: 15 C: 30
ZZD
A: 0
D
-ZS
The impedance characteristic of phase-to-ground distance protection is the circle with line
connecting ends of ZZD and -2ZS/3 as the diameter and that of phase-to-phase distance is the
circle with line connecting ends of ZZD and -ZS/2 as the diameter.
In order to prevent the transient overreach caused by the infeed power supply from the remote
end, the zero-sequence reactance line D is added. These measures have enhanced the capacity
against fault resistance when using distance protection in short lines.
3-42
3 Operation Theory
21Mx.On
21.Blk
21Mx.Op
21Mx.ZG.En
21Mx.ZP.En
21Mx.ZG.Blk
21Mx.ZP.Blk
21Mx.En_ShortDly
21Mx.Blk_ShortDly
21M1.En_Instant
Input Signal
Description
Distance protection enabling input, it is triggered from binary input or
21.En
21.Blk
21Mx.ZG.En
21Mx.ZG.Blk
21Mx.ZP.En
21Mx.ZP.Blk
21Mx.En_ShortDly
21Mx.Blk_ShortDly
21M1.En_Instant
No.
Output Signal
Description
21Mx.On
21Mx.Op
3-43
3 Operation Theory
3.7.5.4 Logic
21.En
SIG
&
21.Enable
21.Blk
SIG
21.Enable
EN
[21M1.ZG.En]
&
&
21M1.ZG.Enable
&
SIG
21M1.ZG.En
SIG
21M1.ZG.Blk
EN
[21M1.ZP.En]
SIG
21M1.ZP.En
SIG
21M1.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
>=1
21M1.On
&
&
&
21M1.ZP.Enable
>=1
SIG
21M1.Rls_PSBR
SIG
FD.Pkp
SIG
21M1.ZG.Enable
SIG
Flag.21M1.ZG
SIG
LoadEnch.St (PG)
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21M1.ZP
SIG
LoadEnch.St (PP)
SIG
FD.Pkp
SIG
21M1.ZP.Enable
SIG
21M1.En_Instant
SIG
21M1.ZG.Op
&
&
[21M1.ZG.t_Op]
&
>=1
21M1.ZG.Op
&
&
>=1
21M1.Flg_PSBR
&
&
[21M1.ZP.t_Op]
&
>=1
21M1.ZP.Op
&
>=1
21M1.Op
SIG
21M1.ZP.Op
Where:
21M1.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3-44
3 Operation Theory
3.7-42.
Flag.21M1.ZG means that measured impedance by zone 1 of phase-to-ground distance
protection is within the range determined by the setting [21M1.ZG.Z_Set].
Flag.21M1.ZP means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the setting [21M1.ZP.Z_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG
21.Enable
EN
[21Mx.ZG.En]
SIG
21Mx.ZG.En
SIG
21Mx.ZG.Blk
EN
[21Mx.ZP.En]
SIG
21Mx.ZP.En
SIG
21Mx.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Mx.En_ShortDly
SIG
21Mx.Blk_ShortDly
EN
[21Mx.En_ShortDly]
SIG
21Mx.On
&
&
21Mx.ZG.Enable
&
>=1
21Mx.On
&
&
&
21Mx.ZP.Enable
>=1
&
&
21Mx.Enable_ShortDly
3-45
3 Operation Theory
SIG
21Mx.Enable_ShortDly
SIG
21Mx.Rls_PSBR
SIG
21Mx.ZG.Enable
SIG
FD.Pkp
SIG
Flag.21Mx.ZG
SIG
LoadEnch.St (PG)
&
[21Mx.ZG.t_ShortDly]
>=1
21Mx.ZG.Op
&
&
[21Mx.ZG.t_Op]
&
>=1
&
SET
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21Mx.ZP
SIG
LoadEnch.St (PP)
SIG
21Mx.ZP.Enable
21Mx.Flg_PSBR
&
&
[21Mx.ZP.t_Op]
&
>=1
21Mx.ZP.Op
&
SIG
FD.Pkp
SIG
21Mx.Enable_ShortDly
SIG
21Mx.ZG.Op
SIG
21Mx.ZP.Op
[21Mx.ZP.t_ShortDly]
>=1
21Mx.Op
Where:
x=2, 3, 4, 5
21Mx.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-42.
Flag.21Mx.ZG means that measured impedance by zone x of phase-to-ground distance protection
is within the range determined by the setting [21Mx.ZG.Z_Set].
Flag.21Mx.ZP means that measured impedance by zone x of phase-to-phase distance protection
is within the range determined by the setting [21Mx.ZP.Z_Set].
3.7.5.5 Settings
Table 3.7-6 Settings of distance protection (Mho)
No.
Name
Range
Step
Unit
Remark
Direction option for zone x of distance
21-x.DirMode
0 or 1
protection (x=2, 3, 4, 5)
0: Forward
1: Reverse
Real component of zero-sequence
21-x.Real_K0
-4.000~4.000
0.001
21-x.Imag_K0
-4.000~4.000
0.001
3-46
Imaginary
component
of
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
zero-sequence
compensation
21-x.phi1_Reach
30.00~89.00
0.01
deg
21Mx.ZG.phi_Shift
0, 15 or 30
deg
21Mx.ZP.phi_Shift
0, 15 or 30
deg
Phase angle of
positive-sequence
shift
of
phase-to-ground
21Mx.ZG.Z_Set
(0.000~4Unn)/In
0.001
ohm
zone x of
21Mx.ZG.t_Op
0.000~10.000
0.001
delay
of
zone
of
21Mx.ZG.t_ShortDly
0.000~10.000
0.001
time delay
of
zone
of
zone
of
21Mx.ZG.En
0 or 1
(x=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-ground
21Mx.ZG.En_BlkAR
0 or 1
to block AR (x=1, 2, 3, 4, 5)
0: disable
1: enable
Impedance setting of
12
21Mx.ZP.Z_Set
(0.000~4Unn)/In
0.001
ohm
phase-to-phase
zone x of
distance
protection
(x=1, 2, 3, 4, 5)
Time
13
21Mx.ZP.t_Op
0.000~10.000
0.001
delay
phase-to-phase
of
zone
distance
of
protection
(x=1, 2, 3, 4, 5)
Short
14
21Mx.ZP.t_ShortDly
0.000~10.000
0.001
time delay
phase-to-phase
of
zone
distance
of
protection
(x=2, 3, 4, 5)
Enabling/disabling
phase-to-phase
15
21Mx.ZP.En
0 or 1
zone
distance
of
protection
(x=1, 2, 3, 4, 5)
0: disable
1: enable
16
21Mx.ZP.En_BlkAR
Enabling/disabling
0 or 1
phase-to-phase
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
to block AR (x=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
fixed
accelerate
21Mx.En_ShortDly
0 or 1
4, 5)
0: disable
1: enable
jX
A
ZZD
RZD
C
Where:
ZZD: impedance setting in forward direction
RZD: resistance setting in forward direction
: line positive-sequence characteristic angle
: the angle of directional line in the second quadrant, set by the setting [21Q.Ang_Alpha]
: the angle of directional line in the fourth quadrant, fixed at 15
3-48
3 Operation Theory
Zone 2, 3, 4, 5 can be set as reverse direction by the setting [21-x.DirMode] (x=2, 3, 4, 5). When a
fault occurs on the busbar at the back, reverse distance element is provided to clear it with definite
time delay and is used as backup protection for reverse busbar fault.
jX
C
RZD
ZZD
Where:
ZZD: impedance setting in reverse direction
RZD: resistance setting in reverse direction
: line positive-sequence characteristic angle
: the angle of directional line, set by the setting [21Q.Ang_Alpha]
: the angle of directional line, fixed at 15
: downward offset angle of the reactance line AB
For quadrilateral distance protection, the reactance line should consider downward offset angle
as shown in Figure 3.7-26 and Figure 3.7-27. According to system status, the downward offset
angle can be independently set for phase-to-ground distance element and phase-to-phase
distance element. The downward offset angle of all zones can be settable by the corresponding
settings [21Qx.ZG.RCA] and [21Qx.ZP.RCA]. (x=1, 2, 3, 4, 5). Phase-to-ground distance
protection is controlled by the fault detector based on residual current.
3-49
3 Operation Theory
21Qx.On
21.Blk
21Qx.Op
21Qx.ZG.En
21Qx.ZP.En
21Qx.ZG.Blk
21Qx.ZP.Blk
21Qx.En_ShortDly
21Qx.Blk_ShortDly
21Q1.En_Instant
Input Signal
Description
Distance protection enabling input, it is triggered from binary input or
21.En
21.Blk
21Qx.ZG.En
21Qx.ZG.Blk
21Qx.ZP.En
21Qx.ZP.Blk
21Qx.En_ShortDly
21Qx.Blk_ShortDly
21Q1.En_Instant
No.
Output Signal
(x=1, 2, 3, 4, 5)
Description
21Qx.On
21Qx.Op
3-50
3 Operation Theory
3.7.6.4 Logic
SIG
21.En
&
21.Enable
SIG
21.Blk
21.Enable
EN
[21Q1.ZG.En]
&
&
21Q1.ZG.Enable
&
SIG
21Q1.ZG.En
SIG
21Q1.ZG.Blk
EN
[21Q1.ZP.En]
SIG
21Q1.ZP.En
SIG
21Q1.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Q1.ZG.Enable
SIG
FD.Pkp
SIG
LoadEnch.St (PG)
>=1
21Q1.On
&
&
&
21Q1.ZP.Enable
>=1
&
&
SET
&
[21Q1.ZG.t_Op]
&
3I0>[FD.ROC.3I0_Set]
SIG
Flag.21Q1.ZG
SIG
21Q1.Rls_PSBR
SIG
FD.Pkp
SIG
21Q1.ZP.Enable
SIG
LoadEnch.St (PP)
SIG
Flag.21Q1.ZP
>=1
21Q1.ZG.Op
&
>=1
21Q1.Flg_PSBR
&
&
&
&
[21Q1.ZP.t_Op]
>=1
&
SIG
21Q1.En_Instant
SIG
21Q1.ZG.Op
SIG
21Q1.ZP.Op
21Q1.ZP.Op
>=1
21Q1.Op
Where:
21Q1. Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3-51
3 Operation Theory
3.7-42.
Flag.21Q1.ZG means that measured impedance by zone 1 of phase-to-ground distance protection
is within the range determined by the settings [21Q1.ZG.Z_Set] and [21Q1.ZG.R_Set].
Flag.21Q1.ZP means that measured impedance by zone 1 of phase-to-phase distance protection
is within the range determined by the settings [21Q1.ZP.Z_Set] and [21Q1.ZP.R_Set].
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
SIG
21.Enable
EN
[21Qx.ZG.En]
SIG
21Qx.ZG.En
SIG
21Qx.ZG.Blk
EN
[21Qx.ZP.En]
SIG
21Qx.ZP.En
SIG
21Qx.ZP.Blk
SIG
VTS.Alm
EN
[VTS.En_Out_VT]
SIG
21Qx.En_ShortDly
SIG
21Qx.Blk_ShortDly
EN
[21Qx.En_ShortDly]
SIG
21Qx.On
&
&
21Qx.ZG.Enable
&
>=1
21Qx.On
&
&
&
21Qx.ZP.Enable
>=1
&
&
21Qx.Enable_ShortDly
3-52
3 Operation Theory
SIG
21Qx.Enable_ShortDly
SIG
21Qx.ZG.Enable
SIG
FD.Pkp
&
&
[21Qx.ZG.t_ShortDly] 0
&
SET
3I0>[FD.ROC.3I0_Set]
SIG
LoadEnch.St (PG)
SIG
Flag.21Qx.ZG
SIG
21Qx.Rls_PSBR
SIG
LoadEnch.St (PP)
SIG
Flag.21Qx.ZP
SIG
21Qx.ZP.Enable
21Qx.ZG.Op
&
[21Qx.ZG.t_Op]
21Qx.Flg_PSBR
&
&
[21Qx.ZP.t_ShortDly] 0
&
SIG
21Qx.ZG.Op
SIG
21Qx.ZP.Op
>=1
21Qx.ZP.Op
&
[21Qx.ZP.t_Op]
FD.Pkp
>=1
&
SIG
>=1
&
>=1
21Qx.Op
Where:
x=2, 3, 4, 5
21Qx.Z.Rls_PSBR: is the signal of power swing blocking releasing signal, please refer to Figure
3.7-42.
Flag.21Qx.ZG means that measured impedance by zone x of phase-to-ground distance protection
is within the range determined by the settings [21Qx.ZG.Z_Set] and [21Qx.ZG.R_Set].
Flag.21Qx.ZP means that measured impedance by zone x of phase-to-phase distance protection
is within the range determined by the settings [21Qx.ZP.Z_Set] and [21Qx.ZP.R_Set].
3.7.6.5 Settings
Table 3.7-8 Settings of distance protection (Quad)
No.
1
Name
21Q.Ang_Alpha
Range
5~30
Step
Unit
deg
Remark
The angle of directional line
Direction option for zone x of distance
21-x.DirMode
0 or 1
protection (x=2, 3, 4, 5)
0: Forward
1: Reverse
Real component of zero-sequence
21-x.Real_K0
-4.000~4.000
0.001
21-x.Imag_K0
-4.000~4.000
0.001
Imaginary
zero-sequence
component
of
compensation
3-53
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
coefficient for zone x (x=1, 2, 3, 4, 5)
21-x.phi1_Reach
30~89
deg
21Qx.ZG.RCA
0~45
deg
reactance
offset
line
angle
for
of
zone
the
x
of
21Qx.ZG.Z_Set
(0.000~4Unn)/In
0.001
ohm
zone x of
21Qx.ZG.R_Set
(0.000~4Unn)/In
0.001
ohm
setting of
zone
x of
21Qx.ZG.t_Op
0.000~10.000
0.001
delay
of
zone
of
10
21Qx.ZG.t_ShortDly
0.000~10.000
0.001
time delay
of
zone
of
zone
of
21Qx.ZG.En
0 or 1
(x=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-ground
21Qx.ZG.En_BlkAR
0 or 1
to block AR (x=1, 2, 3, 4, 5)
0: disable
1: enable
Downward
13
21Qx.ZP.RCA
0~45
deg
reactance
offset
line
phase-to-phase
angle
for
of
zone
distance
the
x
of
protection
(x=1,2,3, 4, 5)
Impedance setting of
14
21Qx.ZP.Z_Set
(0.000~4Unn)/In
0.001
ohm
phase-to-phase
zone x of
distance
protection
(x=1, 2, 3, 4, 5)
Resistance
15
21Qx.ZP.R_Set
(0.000~4Unn)/In
0.001
ohm
setting of
phase-to-phase
zone
distance
x of
protection
(x=1, 2, 3, 4, 5)
Time
16
21Qx.ZP.t_Op
0.000~10.000
0.001
delay
phase-to-phase
of
zone
distance
of
protection
(x=1, 2, 3, 4, 5)
17
21Qx.ZP.t_ShortDly
0.000~10.000
0.001
3-54
Short
time delay
of
zone
of
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
phase-to-ground distance protection
(x=2, 3, 4, 5)
Enabling/disabling
phase-to-phase
18
21Qx.ZP.En
0 or 1
zone
distance
of
protection
(x=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
phase-to-phase
21Qx.ZP.En_BlkAR
0 or 1
to block AR (x=1, 2, 3, 4, 5)
0: disable
1: enable
Enabling/disabling
fixed
accelerate
21Qx.En_ShortDly
0 or 1
4, 5)
0: disable
1: enable
Pilot.Z_Set_B
M
EM
Pilot.Z_Rev_A
Pilot.Z_Set_A
The operation characteristic of pilot zone is same as that of zone 2, including mho and
quadrilateral characteristic.
When an internal fault occurs, distance protection at weak source end may not operate due to
small fault current. Thus, a reverse distance element is provided to coordinate with the
independent pilot distance protection to implement weak infeed logic, ensure pilot distance
protection can operate to send signal or trip in the weak end. The operation characteristic is shown
in Figure 3.7-32. The reverse weak infeed distance element is forward offset with 1/4 of the
reverse setting to enclose the origin.
3-55
3 Operation Theory
Operation characteristics of pilot reverse weak infeed element distance are shown as below.
jX
jX
21Q.Pilot.Z_Rev/4
21M.Pilot.Z_Rev/4
21Q.Pilot.R_Rev
21Q.Pilot.Z_Rev
21M.Pilot.Z_Rev
Where:
: positive-sequence characteristic angle, i.e. [21.Pilot.phi1_Reach]
: the angle of directional line, set by the setting [21Q.Ang_Alpha]
: the angle of directional line, fixed at 15
: tilted angle of the reactance line AC, fixed at 12
3.7.7.2 Logic
SIG
FD.Pkp
SIG
21.Enable
SIG
21M.Pilot.Rls_PSBR
SET
Flag.21M.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21M.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21M.Zpilot.Flag_PSBR
&
3-56
3 Operation Theory
SIG
FD.Pkp
SIG
21.Enable
SIG
21Q.Pilot.Rls_PSBR
SET
Flag.21Q.Pilot.Z (PG)
SIG
LoadEnch.St (PG)
SET
Flag.21Q.Pilot.Z (PP)
SIG
LoadEnch.St (PP)
&
&
&
ZPilotP
&
>=1
21Q.Zpilot.Flag_PSBR
&
Where:
21M.Pilot.Rls_PSBR, 21Q.Pilot.Rls_PSBR: Please refer to Figure 3.7-42.
LoadEnch.St (PG) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-ground impedance into the load area.
LoadEnch.St (PP) means that load trapezoid characteristic for distance element is enabled and
measured phase-to-phase impedance into the load area.
Flag.21Q.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21Q.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21Q.Pilot.Z_Set]. (Quad characteristic)
Flag.21M.Pilot.Z (PG) means that measured impedance by phase-to-ground distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
Flag.21M.Pilot.Z (PP) means that measured impedance by phase-to-phase distance element is
within the range determined by the setting [21M.Pilot.Z_Set]. (Mho characteristic)
3.7.7.3 Settings
Table 3.7-9 Settings of pilot distance zone
No.
Name
Range
Step
Unit
Remark
Real
21.Pilot.Real_K0
30.00~89.00
0.01
deg
component
compensation
of
zero-sequence
coefficient
for
pilot
distance protection
Imaginary component of zero-sequence
2
21.Pilot.Imag_K0
-4.000~4.000
0.001
compensation
coefficient
for
pilot
distance protection
3
21.Pilot.phi1_Reach
-4.000~4.000
21M.Pilot.Z_Set
(0.000~4Unn)/In
Phase
0.001
0.001
angle
of
positive-sequence
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
protection (Mho characteristic)
21Q.Pilot.Z_Set
(0.000~4Unn)/In
0.001
ohm
21M.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
21Q.Pilot.Z_Rev
(0.000~4Unn)/In
0.001
ohm
21Q.Pilot.R_Set
(0.000~4Unn)/In
0.001
ohm
21Q.Pilot.R_Rev
(0.000~4Unn)/In
0.001
ohm
3-58
3 Operation Theory
U
EM
EN
I
ZLine
The potential of the two machines are E M and EN respectively, and their amplitude are both
equal to E1.
2.
Taking EN as reference vector, whose initial phase angle is 0and angle velocity is . At the side
M, the initial phase angle of equivalent potential E M is (i.e., during normal operation condition,
the systems power angle is ), whose increment of the angle velocity is relative to side N, so
EN E1 cos( t )
EM E1 cos(( ) t )
Suppose the power angle between both sides of the system is
t
The equivalent system vector diagram of Figure 3.7-35 is illustrated in Figure 3.7-36.
I
U
EM
U cos
EN
U SCV
E1
E1
Where:
USCV is the voltage of oscillation center
U is the measured voltage by the device
As shown in Figure 3.7-36, the voltage of oscillation center USCV is:
3 Operation Theory
In the case that the system is in synchronous condition, =0, the voltage of oscillation center
maintains be unchanged, that is:
U SCV cos( )
2
Make calculus for the voltage of oscillation center,
d (U SCV )
E
d ( )
1 sin( )
dt
2
2
dt
The above equation describe the relationship between the voltage change rate of oscillation
center and system slip frequency
d ( )
, which indicates the voltage varation of oscillation center
dt
-1
-1
(a)
(b)
According to the above analysis, it can be shown that there is certain functional relation between
the oscillation center voltage and power angle , thus the oscillation center voltage (Ucos) can
be used to reflect the variation of power angle. Power angle varies continuously as an
electrical quantity. As a result, the oscillation center voltage varies continuously during
3-60
3 Operation Theory
out-of-step oscillation, crossing the zero point. However, sudden variation or discontinuous
change is a distinguished feature of oscillation center voltage during fault occurrence or
clearance. During synchronous oscillation, the oscillation center voltage also varies
continuously but it does not cross the zero point. Therefore, the oscillation center voltage can
be used to discriminate among out-of-step oscillation, short-circuit fault and synchronous
oscillation.
The variation range of oscillation center voltage (Ucos) can be divided into seven zones on the
variation plane, as shown in Figure 3.7-38.
From the above analysis, the variation rules of oscillation center voltage (Ucos) during
out-of-step oscillation are as follows:
1. During accelerating out-of-step condition, the variation rule of Ucos is 0 1 2 3 4 5
60
2. During decelerating out-of-step condition, the variation rule of Ucos is 0 6 5 4 3 2
10
U
-1
1
0
-1
If the oscillation center voltage varies as the above mentioned rules, the relay consider it as
out-of-step condition and issues tripping command after the time delay (i.e., the setting
[78.N_Limit]), performing separation.
The above analysis is based on the assumption that system impedance angle is 90, while in
practical system it is not, thus angle compensation is required. As shown in Figure 3.7-39, setting
the system impedance angle L in the device, the angle compensation is made to the oscillation
center voltage,
U SCV U cos( 90 L )
3-61
3 Operation Theory
I'
EM
EN
U
U cos
In order to locate the distance between the oscillation center and where the device is equipped,
setting impedance measurement element is used to confirm the operation range of separation
device, the operation characteristic of zone relay based on impedance discrimination is shown
in Figure 3.7-40.
EM
ZM
Z L ine
ZN
EN
I
U
Z Re v Relay
Z Fwd
ZN
jX
Z Fwd
Z Re v
ZM
Where:
ZM and ZN are respective system impedances.
ZFwd is the impedance from zone relay location to side-N system
3-62
3 Operation Theory
78.On
78.Blk
78.St
78.Clr_Counter
78.St_Zone
78.Op
Input Signal
78.En
78.Blk
78.Clr_Counter
No.
Description
Out-of-step protection enabling input, it is triggered from binary input or
programmable logic etc.
Out-of-step protection blocking input, it is triggered from binary input or
programmable logic etc.
Clear the counter
Output Signal
Description
78.On
78.St
78.St_Zone
78.Op
3.7.8.5 Logic
In order to prevent out-of-step protection from maloperation under normal conditions or faulty
conditions, the system will be think as oscillation only the following conditions are all met.
1.
2.
3.
3-63
3 Operation Theory
The power angle () is greater than the minimum start angle ([78.Phi_Start]).
4.
SIG
78.En
En
[78.En]
SIG
78.Blk
SIG
VTS.Alm
SIG
Ia>0.12In
SIG
Ib>0.12In
SIG
Ic>0.12In
&
&
78.On
&
t1
t2
78.St
&
SIG
&
&
||>[78.phi_Start]
SIG
U1<0.95Un
SIG
8>d/dt>0.2
SIG
SIG
&
&
Counter>[78.N_Limit]
>=1
SIG
Ucos - to +
En
[78.En_Trp]
SIG
<[78.phi_Trp]
&
78.Op
&
>=1
SIG
78.St_Zone
SIG
78.St
&
Where:
U1 is positive-sequence voltage.
t1 is the pickup time delay of discriminating oscillation, internal fixed value is 40ms
t2 is the dropoff time delay of discriminating oscillation, internal fixed value is 3s
3.7.8.6 Settings
Table 3.7-11 Settings of out-of-step protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling out-of-step protection
78.En
0 or 1
0: disable
1: enable
78.En_Trp
0 or 1
operate to trip
3-64
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
0: disable
1: enable
78.Z_Fwd
(0.000~4Unn)/In
0.001
ohm
78.Z_Rev
(0.000~4Unn)/In
0.001
ohm
78.phi1_Reach
30.00~89.00
0.01
deg
78.phi_Start
0~180
deg
78.phi_Trp
0~180.00
0.01
deg
78.N_Limit
1~20
1.
If any of the following condition is matched, FD PSBR will operate for 160ms.
Positive sequence current is lower than the setting [I_PSBR] before general fault detector element
operates.
3-65
3 Operation Theory
As shown in figure below, assuming that normal load impedance locates at position 1 and the
impedance locates at position 2 when positive-sequence current is lower than the setting
[I_PSBR], it means FD operates between point 1 and point 2 if operation condition for FD PSBR
mentioned above is fulfilled (point 3 as an example), and then FD PSBR will operate for 160ms.
[I_PSBR]
FD
Normal load
impedance
Point 1
Point 3
Point 2
2.
3 Operation Theory
If a three-phase fault occurs and FD PSBR is invalid (160ms after FD operates), neither FD PSBR
nor UF PSBR will be able to release the distance protection. Thus, SF PSBR is provided for this
case specially. This detection is based on measuring the voltage at power swing center, during
power swing, U1cos will constantly change periodically.
UOS=U1COS
Where:
: the angle between positive sequence voltage and current
U1: the positive sequence voltage
As shown in the figure below, assume system connection impedance angle of 90, current vector
will be perpendicular to the line connecting E M and EN, and have the same phase as power swing
center voltage. During normal operation of system or power swing, U1cos just reflects
positive-sequence voltage of power swing center. In case of 3-phase short circuit, U1cos is
voltage drop on arc resistor, transition resistance is arc resistance, and voltage drop on arc resistor
is less than 5%UN. In actual system, line impedance angle is not 90. Through compensation of
angle , power swing center voltage can be measured accurately. After compensation, power
swing center voltage is U1cos(90oL), where L is line impedance angle.
EM
EN
UOS
During power swing, power swing center voltage U 1cos has the following characteristics: When
electric potential phase angle difference between power supplies at two sides is 180 o, U1cos0
and change rate dU1cos/dt is the maximum. When this phase angle difference is near 0 o, power
swing center voltage change rate dU 1cos/dt is the minimum. During short circuit, U 1cos
remains unchanged and dU1cos/dt0. However, in early stage of short circuit when normal state
enters short circuit state, dU1cos/dt is very large. Therefore, use of dU 1cos/dt solely to
differentiate power swing and short circuit is not complete.
For these reasons, the method to release distance protection on condition that power swing center
voltage U1cos is less than a setting and after a short delay can be used as symmetric fault
discriminating element. This element can accurately differentiate power swing and 3-phase short
circuit fault, and constitute a complete power swing blocking scheme with other elements. The
element to open distance protection if U1cos is less than a certain setting and after a delay is
3-67
3 Operation Theory
easy to realize and has short delay, and can trip fault more quickly and accurately trip 3-phase
short circuit fault during power swing.
The criterion of SF PSBR element comprises the following two parts:
The second criterion is a backup of the first criterion allowing longer monitoring period of voltage
variation.
To reduce the time delay for SF PSBR element during power swing, the change rate of voltage at
power swing center is also used which can release SF PSBR element quickly for the fault occurred
during power swing. The typical release time is less than 60ms.
3.7.9.1 Function Block Diagram
21Mx
21Mx.En_PSBR
21Mx.Rls_PSBR
21Mx.Blk_PSBR
21M.Pilot.Rls_PSBR
21M.Pilot.En_PSBR
21M.Pilot.Blk_PSBR
21Qx
21Qx.En_PSBR
21Qx.Rls_PSBR
21Qx.Blk_PSBR
21Q.Pilot.Rls_PSBR
21Q.Pilot.En_PSBR
21Q.Pilot.Blk_PSBR
Input Signal
21Mx.En_PSBR
21Qx.En_PSBR
21Mx.Blk_PSBR
21Qx.Blk_PSBR
Description
Enabling power swing blocking releasing of zone x (Mho characteristic, x=1, 2,
3, 4, 5)
Enabling power swing blocking releasing of zone x (Quad characteristic, x=1, 2,
3, 4, 5)
Blocking power swing blocking releasing of zone x (Mho characteristic, x=1, 2,
3, 4, 5)
Blocking power swing blocking releasing of zone x (Quad characteristic, x=1, 2,
3, 4, 5)
3-68
3 Operation Theory
5
21M.Pilot.En_PSBR
21M.Pilot.Blk_PSBR
21Q.Pilot.En_PSBR
21Q.Pilot.Blk_PSBR
No.
Output Signal
21Mx.Rls_PSBR
21Qx.Rls_PSBR
21M.Pilot.Rls_PSBR
21Q.Pilot.Rls_PSBR
3.7.9.3 Logic
SIG
21Mx.En_PSBR
SIG
21Mx.Blk_PSBR
SIG
FD.Pkp
SIG
21Mx.Flg_PSBR
SIG
21Mx.Enable_PSBR
EN
[21Mx.En_PSBR]
SIG
Symmetrical |U1cos|<
&
21Mx.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
>=1
21Mx.Rls_PSBR
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Mx.Flg_PSBR
SET
I1>[21M.I_PSBR]
3s
&
&
0
SIG
160ms
>=1
FD.Pkp
3-69
3 Operation Theory
SIG
21Qx.En_PSBR
SIG
21Qx.Blk_PSBR
SIG
FD.Pkp
SIG
21Qx.Flg_PSBR
SIG
21Qx.Enable_PSBR
EN
[21Qx.En_PSBR]
SIG
Symmetrical |U1cos|<
&
21Qx.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
21Qx.Rls_PSBR
>=1
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Qx.Flg_PSBR
SET
I1>[21Q.I_PSBR]
3s
&
&
0
SIG
FD.Pkp
SIG
21M.Pilot.En_PSBR
SIG
21M.Pilot.Blk_PSBR
SIG
FD.Pkp
SIG
21M.Pilot.Flg_PSBR
SIG
21M.Pilot.Enable_PSBR
EN
[21M.Pilot.En_PSBR]
SIG
Symmetrical |U1cos|<
160ms
>=1
&
21M.Pilot.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
>=1
21M.Pilot.Rls_PSBR
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21M.Pilot.Flg_PSBR
SET
I1>[21M.I_PSBR]
3s
&
&
0
SIG
160ms
>=1
FD.Pkp
3-70
3 Operation Theory
SIG
21Q.Pilot.En_PSBR
SIG
21Q.Pilot.Blk_PSBR
SIG
FD.Pkp
SIG
21Q.Pilot.Flg_PSBR
SIG
21Q.Pilot.Enable_PSBR
EN
[21Q.Pilot.En_PSBR]
SIG
Symmetrical |U1cos|<
&
21Q.Pilot.Enable_PSBR
&
&
>=1
&
t
0ms
Unblocking for SF
21Q.Pilot.Rls_PSBR
>=1
>=1
&
SIG
Unsymmetrical |I0|+|I2|>
Unblocking for UF
SIG
21Q.Pilot.Flg_PSBR
SET
I1>[21Q.I_PSBR]
3s
&
&
0
SIG
160ms
>=1
FD.Pkp
Where:
x: 1, 2, 3, 4, 5
21Mx.Flg_PSBR: Please refer to Figure 3.7-24~Figure 3.7-25
21Qx.Flg_PSBR: Please refer to Figure 3.7-29~Figure 3.7-30
21M.Pilot.Flg_PSBR and 21Q.Pilot.Flg_PSBR: Please refer to Figure 3.7-33 and Figure 3.7-34
3.7.9.4 Settings
Table 3.7-13 Settings of PSBR
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
zone
of
21M1.En_PSBR
0 or 1
zone
of
21Q1.En_PSBR
0 or 1
21M2.En_PSBR
0 or 1
Enabling/disabling
zone
of
3-71
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
distance protection controlled by
PSBR (Mho characteristic)
0: disable
1: enable
Enabling/disabling
zone
of
21Q2.En_PSBR
0 or 1
zone
of
21M3.En_PSBR
0 or 1
zone
of
21Q3.En_PSBR
0 or 1
zone
of
21M4.En_PSBR
0 or 1
zone
of
21Q4.En_PSBR
0 or 1
zone
of
21M5.En_PSBR
0 or 1
zone
of
21Q5.En_PSBR
0 or 1
11
21M.Pilot.En_PSBR
0 or 1
characteristic)
0: disable
3-72
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
1: enable
Enabling/disabling pilot distance
zone controlled by PSBR (Quad
12
21Q.Pilot.En_PSBR
0 or 1
characteristic)
0: disable
1: enable
13
21M.I_PSBR
(0.050~30.000)In
0.001
14
21Q.I_PSBR
(0.050~30.000)In
0.001
21SOTF.On
21SOTF.Blk
21SOTF.Op
21SOTF.Op_PDF
Input Signal
21SOTF.En
21SOTF.Blk
No.
Description
Distance SOTF protection enabling input, it is triggered from binary input or
programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
21SOTF.Op
21SOTF.Op_PDF
Description
Accelerate distance protection to trip when manual closing or auto-reclosing to
fault
Accelerate distance protection to trip when another fault happened under pole
3-73
3 Operation Theory
discrepancy conditions
3
21SOTF.On
3.7.10.3 Logic
SIG
21SOTF.En
SIG
21SOTF.Blk
EN
[21SOTF.En]
&
&
21SOTF.On
Distance SOTF protection can be enabled or disabled, and can be initiated by several cases,
including manual closing signal, 3-pole reclosing, 1-pole reclosing and pole discrepancy
conditions.
1.
SIG
CB1.52b_PhA
SIG
CB1.52b_PhB
SIG
CB1.52b_PhC
SIG
FD.Pkp
EN
[SOTF.Opt_Mode_ManCls]=CBPos
EN
[SOTF.Opt_Mode_ManCls]=ManClsBI
SIG
FD.Pkp
SIG
ManCls
Set
[SOTF.Opt_Mode_ManCls]=AutoInit
SIG
Ua<[SOTF.U_Ddl]
SIG
Ub<[SOTF.U_Ddl]
SIG
Uc<[SOTF.U_Ddl]
SIG
FD.Pkp
SIG
VTS.Alm
SIG
Ia<0.06In
SIG
Ib<0.06In
SIG
Ic<0.06In
SIG
79.Close (3P)
0ms [SOTF.t_En]
SIG
79.Close (1P)
0ms [SOTF.t_En]
>=1
&
&
>=1
0
[SOTF.t_En]
&
&
>=1
&
[SOTF.t_DdL]
0ms
Dead line
&
3-74
3 Operation Theory
For double circuit breakers mode, the phase's open status corresponding to the line is invalid
unless both circuit breakers are in open position.
2.
BI
[CB1.52b_PhA]
BI
[CB2.52b_PhA]
BI
[CB1.52b_PhB]
BI
[CB2.52b_PhB]
BI
[CB1.52b_PhC]
BI
[CB2.52b_PhC]
SIG
FD.Pkp
EN
[SOTF.Opt_Mode_ManCls]=CBPos
EN
[SOTF.Opt_Mode_ManCls]=ManClsBI
SIG
FD.Pkp
SIG
ManCls
Set
[SOTF.Opt_Mode_ManCls]=AutoInit
SIG
Ua<[SOTF.U_Ddl]
SIG
Ub<[SOTF.U_Ddl]
SIG
Uc<[SOTF.U_Ddl]
SIG
FD.Pkp
&
&
>=1
&
&
&
>=1
0ms [SOTF.t_En]
&
&
>=1
&
[SOTF.t_DdL]
0ms
SIG
VTS.Alm
SIG
Ia<0.06In
SIG
Ib<0.06In
SIG
Ic<0.06In
SIG
79.Close(3P)
0ms [SOTF.t_En]
SIG
79.Close(1P)
0ms [SOTF.t_En]
Dead line
&
For accelerated tripping mode by manual closing signal, manual closing signal can be from circuit
breaker position, external binary signal of manual closing or dead line check. When the circuit
breaker is in open position while the device does not pick up, or external manual closing binary
input is energized, then manual closing signal will be kept for the setting [SOTF.t_En], which will
enable SOTF logic. When the initiation mode of SOTF protection is set as AutoInit (i.e.,
[SOTF.Opt_Mode_ManCls] is set as AutoInit), distance SOTF protection will be initiated by dead
line check. When three phases currents are all smaller than 0.06In and no fault detector element
3-75
3 Operation Theory
operates, SOTF logic will be enabled only for the setting [SOTF.t_En] if three phase voltages are
all smaller than the setting [SOTF.U_Ddl] with the time delay [SOTF.t_Ddl].
SIG
SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_ManCls]
EN
[21SOTF.Z2.En_ManCls]
SIG
21M(21Q)2.Flg_PSBR
EN
[21SOTF.Z3.En_ManCls]
SIG
21M(21Q)3.Flg_PSBR
EN
[21SOTF.Z4.En_ManCls]
SIG
21M(21Q)4.Flg_PSBR
&
&
[21SOTF.t_ManCls]
&
21SOTF.Op_ManCls
&
&
>=1
&
Figure 3.7-46 Logic diagram of distance SOTF protection by manual closing signal
SIG
FD.Pkp
SIG
21SOTF.On
EN
[21SOTF.En_3PAR]
SIG
EN
[21SOTF.Z2.En_3PAR]
SIG
21M(21Q)2.Flg_PSBR
EN
[21SOTF.Z2.En_PSBR]
SIG
21M(21Q)2.Rls_PSBR
EN
[21SOTF.Z3.En_3PAR]
&
&
SIG
21M(21Q)3.Flg_PSBR
EN
[21SOTF.Z3.En_PSBR]
SIG
21M(21Q)3.Rls_PSBR
EN
[21SOTF.Z4.En_3PAR]
SIG
21M(21Q)4.Flg_PSBR
EN
[21SOTF.Z4.En_PSBR]
SIG
21M(21Q)4.Rls_PSBR
EN
[21SOTF.En_1PAR]
SIG
PD signal
SIG
21M(21Q)2.Rls_PSBR
[21SOTF.t_3PAR]
>=1
21SOTF.Op_AR
&
&
>=1
&
&
&
>=1
>=1
&
&
>=1
&
&
[21SOTF.t_1PAR]
&
3 Operation Theory
For single-phase permanent fault, distance SOTF protection for 1-pole reclosing onto the faulty
phase will trip three-phase circuit breaker.
SIG
21SOTF.On
SIG
FD.Pkp
EN
[21SOTF.En_PDF]
SIG
21M(21Q)2.Rls_PSBR
SIG
PD signal
&
&
[21SOTF.t_PDF]
21SOTF.Op_PDF
&
&
Under pole discrepancy condition after single-phase tripping, distance SOTF protection will
accelerate to operate if another fault happens to the healthy phase.
SIG
21SOTF.Op_ManCls
>=1
21SOTF.Op
SIG
21SOTF.Op_AR
3.7.10.4 Settings
Table 3.7-15 Settings of distance SOTF protection
No.
Name
Range
Step
Unit
Remark
Time delay of enabling SOTF
protection (shared by distance
SOTF.t_En
0.000~10.000
0.001
21SOTF.En
protection
0 or 1
0: disable
1: enable
Enabling/disabling
distance
21SOTF.Z2.En_ManCls
0 or 1
SOTF
zone
of
protection
for
manual closing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z3.En_ManCls
0 or 1
SOTF
zone
of
protection
for
manual closing
1: enable
0: disable
3-77
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
distance
21SOTF.Z4.En_ManCls
0 or 1
SOTF
zone
of
protection
for
manual closing
1: enable
0: disable
Time delay of distance protection
21SOTF.t_ManCls
0.000~10.000
0.001
21SOTF.Z2.En_3PAR
0 or 1
SOTF
zone
of
protection
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z3.En_3PAR
0 or 1
SOTF
zone
of
protection
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
distance
21SOTF.Z4.En_3PAR
0 or 1
SOTF
zone
of
protection
for
3-pole reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z2.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z3.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
Enabling/disabling
zone
21SOTF.Z4.En_PSBR
SOTF
0 or 1
protection
for
3-pole
reclosing
1: enable
0: disable
13
21SOTF.t_3PAR
0.000~10.000
0.001
3-78
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
reclosing
Enabling/disabling distance SOTF
14
21SOTF.En_1PAR
0 or 1
0: disable
1: enable
Time delay of distance protection
15
21SOTF.t_1PAR
0.000~10.000
0.001
16
21SOTF.En_PDF
0 or 1
conditions
1: enable
0: disable
Time delay of distance protection
17
21SOTF.t_PDF
0.000~10.000
0.001
18
SOTF.U_Ddl
0~Unn
0.001
19
SOTF.t_Ddl
0.000~600.000
0.001
ManClsBI
CBPos
20
SOTF.Opt_Mode_ManCls
ManClsBI/CBPos:
ManClsBI/
initiated
by
CBPos
closing or CB position
AutoInit
All
detection
All: initiated by both binary input
and no voltage detection
Name
Default Value
Unit
Remark
Enabling/disabling distance SOTF protection for
21SOTF.En_ManCls
manual closing
0: disable
1: enable
Enabling/disabling distance SOTF protection for
21SOTF.En_3PAR
3-pole reclosing
0: disable
1: enable
3-79
3 Operation Theory
PCS-931
TX
RX
RX
TX
PCS-931
ST connectors
ST connectors
3-80
3 Operation Theory
TX
RX
RX
TX
PCS-931
PCS-931
FC connectors
FC connectors
Figure 3.8-2 Direct optical link up to 40km with 1310nm or up to 100km with 1550nm
Channel of 64kbits/s or 2048kbits/s via multiplexer is shown in Figure 3.8-3, Figure 3.8-4 and
Figure 3.8-5.
C37.94 (N*64kbits/s)
Multi-mode FO
Communication convertor
TX
RX
RX
TX
Interface
Link to
communicate
device
PCS-931
ST connectors
ST connectors
G.703 (64kbits/s)
MUX-64
Single-mode FO
TX
RX
RX
TX
Interface
PCS-931
FC connectors
Link to
communicate
device
FC connectors
3-81
3 Operation Theory
G.703-E1 (2048kbits/s)
MUX-2M
Single-mode FO
TX
RX
RX
TX
Interface
Link to
communicate
device
PCS-931
FC connectors
FC connectors
Data Frame
Description
Format
LocID
Ia
Ib
Ic
low
Time
FOx.Send1~FOx.Send8
Enable DIFF
CRC
Master-master mode
Slave-slave mode
3 Operation Theory
3.
Master-slave mode
One of them uses internal clock, the other uses external clock
The logic setting [FOx.En_IntClock] is used in current differential protection to select the
communication clock. The internal clock is enabled automatically when the logic setting
[FOx.En_IntClock] is set as 1. Contrarily, the external clock is enabled automatically when the
logic setting [FOx.En_IntClock] is set to 0.
If the device uses multiplex PCM channel, logic setting [FOx.En_IntClock] at both ends should be
set as 0 (Mode 2). If the device uses dedicated optical fibre channel, clock Mode 1 and Mode 3
can be used. Mode 1 is recommended in considering simplification to user, i.e. logic setting
[FOx.En_IntClock] at both ends should be set as 1.
3.8.2.3 Identity Code
In order to ensure reliability of the device when digital communication channel is applied, settings
[FO.LocID] and [FO.RmtID] are provided as identity code to distinguish uniquely the device at
remote end using same channel.
Under normal conditions, the identity code of the device at local end should be different with that at
remote end. In addition, it is recommended that the identity code of all devices, i.e., the setting
[FO.LocID], should be unique in the power grid. The setting range is from 0 to 65535. Only for loop
test, they are set as the same.
The setting [FO.LocID] of the device at an end should be the same as the setting [FO.RmtID] of
the device at opposite end and the greater [FO.LocID] between the two ends is chosen as a
master end for sampling synchronism, the smaller [FO.LocID] is slave end. If the setting [FO.LocID]
is set the same as [FO.RmtID], that implies the device in loopback testing state.
The setting [FO.LocID] is packaged in the message frame and transmitted to the remote end.
When the [FO.LocID] of the device at remote end received by local device is same to the setting
[FO.RmtID] of local device, the message received from the remote end is valid, and protection
information involved in message is read. When these settings are not matched, the message is
considered as invalid and protection information involved in message is ignored, corresponding
alarms will be issued.
3.8.2.4 Channel Statistics
The device has the function of on-line channel monitoring and channel statistics. It can produce
channel statistic report automatically at 9:00 every day and the report can be printed for operator
to check the channel quality. The monitoring contents of channel status are shown as follows, and
they can be viewed by the menu Main MenuTestProt Ch CounterChx Counter.
1.
It shows the starting time of the channel status statistics of the device at local end.
2.
3-83
3 Operation Theory
3.
It shows the calculated communication channel time delay of the device at local end now (unit: us).
The calculation is based on the assumption of same channel path for to and from remote end. The
device measures propagation delay of communication channel based on the below principle.
Side S transmits a frame of message to side M, and meanwhile records the transmitting time tss
on the basis of clock on side S. When side M receives the message, it will record receiving time
tmr of the message with its own clock, and return a frame of message to side S at next fixed
transmitting time, meanwhile data of tms-tmr is included in the frame of message. Side S will
receive the message from side M at the time tsr and obtain the data of tms-tmr.
Therefore, the propagation delay of the channel Td is obtained through calculation:
Td
(tsr t ss ) (tms t mr )
2
By using the above calculated Td, the device automatically compensate time synchronization of
sampling data at each end and transimission time lag.
T1
tss
tsr
tmr
Td
tms
"S"
"M"
T2
4.
It shows the total number of the error frames of the device at local end from starting time of
channel statistics until now. Error frame means that this frame fails in CRC check.
5.
It shows the total number of abnormal messages of the device at local end from starting time of
channel statistics until now.
6.
It shows the total number of the lost frames of the device at local end from starting time of channel
statistics until now.
3-84
3 Operation Theory
7.
FOx.N_RmtAbnor (total number of abnormal messages from the remote end of channel x)
It shows the total number of abnormal messages received from the remote end from starting time
of channel statistics until now.
8.
It shows the total number of serious error frame seconds of the device at local end from starting
time of the channel statistics until now.
9.
It shows the total number of loss synchronous of the device at local end from starting time of the
channel statistics until now.
FOx.On
FOx.Send1
FOx.Recv1
FOx.Send2
FOx.Recv2
FOx.Send3
FOx.Recv3
FOx.Send4
FOx.Recv4
FOx.Send5
FOx.Recv5
FOx.Send6
FOx.Recv6
FOx.Send7
FOx.Recv7
FOx.Send8
FOx.Recv8
FOx.Alm
FOx.Alm_ID
FOx.Alm_87L_Unmatched
Input Signal
Description
FOx.En
Enabling channel x
FOx.Send1
FOx.Send2
FOx.Send3
FOx.Send4
FOx.Send5
3-85
3 Operation Theory
7
FOx.Send6
FOx.Send7
FOx.Send8
Output Signal
Description
FOx.On
Channel x is enabled.
FOx.Recv1
FOx.Recv2
FOx.Recv3
FOx.Recv4
FOx.Recv5
FOx.Recv6
FOx.Recv7
FOx.Recv8
FOx.Alm
Channel x is abnormal
No.
10
FOx.Alm_ID
11
FOx.Alm_87L_Unmatched
3.8.5 Logic
SIG
SIG
SIG
&
&
>=1
&
10s
10s
&
SIG
FOx.Alm_87L_Unmatched
FOx.Alm
SIG
SIG
FOx.Alm
SIG
FOx.Alm_ID
SIG
FOx.En
&
FOx.Recvn
>=1
&
FOx.On
EN
FOx.En
n can be 1~8
3-86
3 Operation Theory
3.8.6 Settings
Table 3.8-2 Settings of pilot channel
No.
Name
Range
Step
Unit
Remark
FO.LocID
0-65535
FO.RmtID
0-65535
FO.Protocol
FOx.BaudRate
G.703
C37.94
C37.94
64 or 2048
kbps
FOx.Nx64k_C37.94
1-12
FOx.En_IntClock
0 or 1
0: external clock
1: internal clock
Enabling/disabling channel x
FOx.En
0 or 1
0: disable
1: enable
3 Operation Theory
The detailed channel status, including channel delay, current from the remote end and differential
current, can be displayed on the LCD.
Current differential protection comprises three elements:
IDiff IH
Equation 3.9-1
Where:
1.5UN
)
X C1L
The calculation of DPFC restraint current and differential current is phase-segregated. In these
summations, charging current is eliminated from the phase currents by the charging current
compensation function, so it is not needed to consider capacitive current during disturbance status
for current differential setting threashold.
If the charging current compensation function is disabled (the setting [87L.En_CapCurrComp] is
1.5UN
set as 0),
is not considered to calculate pickup setting. The regulation is adaptive to
X C1L
other stages of current differential protection.
Operation characteristic curve is shown as following figure.
3-88
3 Operation Theory
IDiff
k=1
k=0.75
IH
IBias
Due to high slope of DPFC percent differential protection, differential protection has higher ability
of anti-CT saturation. Meanwhile, the load current wont affect the sensitivity of DPFC differential
elements, so the sensitivity is very high even for high impedance fault under heavy load.
3.9.2.2 DPFC Current Differential Element (Stage 2)
Operation criteria:
I Diff IM
Equation 3.9-2
Where:
IM : Max([87L.I_Pkp],
1.25UN
)
X C1L
3-89
3 Operation Theory
IDiff
k=1
k=0.75
IM
IBias
When the above criterion is met, the stage 2 of DPFC current differential element will operate after
1 cycles.
3.9.2.3 Steady-state Current Differential Element (stage 1)
Operation criteria:
IDiff 0.6 IBias
IDiff IH
Equation 3.9-3
Where:
1.5UN
)
X C1L
3-90
3 Operation Theory
IDiff
k=0.6
IH
IBias
IDiff IM
Equation 3.9-4
Where:
IM : Max([87L.I_Pkp],
1.25UN
)
X C1L
3-91
3 Operation Theory
IDiff
k=0.6
IM
IBias
When the above criterion is met, the stage 2 of steady-state differential current relay will operate
after 1 cycles.
3.9.2.5 Neutral Current Differential Element
The sensitivity of steady-state differential current element is too low for the slight fault during heavy
load, and DPFC current differential element can only reflect the slight fault during heavy load, but low
for the slow changing fault due to the small change of fault component. Neutral current differential
element can be very sensitive to this kind of fault.
Operation criteria:
IDiff0 IL
Equation 3.9-5
Where:
3 Operation Theory
In these summations, charging current is eliminated from the phase currents by the charging current
compensation function. So it is not needed to consider capacitive current during disturbance status for
setting threashold
Operation characteristic curve is shown as following figure.
IDiff0
k=0.75
IL
IBias0
Due to high slope of neutral current differential protection, differential protection has higher ability
of anti-CT saturation. When the above criterion is met, the neutral current differential relay will
operate with a time delay (controlled by an internal setting, default value is 40ms).
3.9.2.6 Capacitive Current Compensation
For the long transmission line whose capacitive current is very large, in order to increase the
sensitivity of current differential element especially for an earth fault associated with high fault
resistance, capacitive current must be compensated to eliminate the effect that capacitive current
has on differential current. The traditional method of compensating capacitive current can only
compensate steady-state capacitive current. However, during the transient period, such as circuit
energization (as shown in below figure), external fault clearance, etc., there is large transient
capacitive current in the line.
3-93
3 Operation Theory
The traditional method cannot compensate the capacitive current completely, hence, a new
method is adopted to compensate transient component of capacitive current.
1.
Phase capacitive current of line can be derived from equivalent circuit. Under normal condition,
circuit energization and external fault clearance, not only steady-state component but also
transient component of capacitive current can be compensated. It can improve the sensitivity of
current differential protection.
ZL
ZL
ZL
For various system frequencies, the capacitive current which is shown in above figure can be
calculated by:
ic C
duc
dt
Equation 3.9-6
Where:
Because a part of capacitive current has been compensated by shunt reactor, reactive current IL
must be subtracted from capacitive current calculated by above equation, i.e. Equation 3.9-6.
3-94
3 Operation Theory
Lp
ua
iLa
Lf
uf
uL
ub
iLb
iL
uc
iLc
Figure 3.9-7 Equivalent circuit of shunt reactor
diL (t)
dt
Equation 3.9-7
1
LP
U (t) U (t)dt
t
t t
Equation 3.9-8
Then,
ic C
3.
duc
iL (t)
dt
Equation 3.9-9
Capacitive current is very small, the sensitivity of current differential protection can still meet the
requirement. The function, capacitive current compensation, will be disabled automatically if
differential current is smaller than 0.1In.
4.
If transient capacitive current compensation is adopted, according to Equation 3.9-6 and Equation
3.9-9, the compensated transient capactive current of each side is calculated, then the transient
differential current and restraint current after compensation is calculated, so differential protection
function can be accomplished.
3.9.2.7 CT Supervision
If CT circuit fails, an alarm will be issued with a time delay. When CT circuit failure occurs at one
end, FD and current differential protection on the end might operate. However, FD on another end
will not operate and not send any permissive signal of current differential protection. Therefore, the
current differential protection will not maloperate. Meanwhile the healthy end will issue alarm
signal [87L.FOx.Alm_Diff] which will be treated as the same as the alarm [CTS.Alm].
However, if CT circuit failure associated with internal fault or pickup due to system disturbance is
detected, the device will show two kinds of behavior.
If logic setting [87L.En_CTS_Blk] (differential protection being blocked during CT circuit failure) is
3-95
3 Operation Theory
Due to high slope of DPFC percent differential protection, differential protection has higher ability
of anti-CT saturation. For external fault as following figure, the restraint current will be able to
reflect the real quantity of system for a short time after current cross zero point and can be used as
the restraint current after CT enters into saturation status by the use of self-adaptive floating
threshold technology.
Fault-Current-SideA
10
5
0
-5
-10
20
40
60
80
100
120
140
80
100
120
140
80
100
120
140
Fault-Current-SideB
20
10
0
-10
20
40
60
Diff-Current
20
10
0
-10
20
40
60
Restraint-Current
20
CT
10
0
-10
-20
20
40
60
80
100
120
140
2.
Asynchronous method: as shown in Figure 3.9-8, there is a short time before CT is saturated
after fault current cross zero point, during the period, CT can convert fault current accurately,
so there is restraint current but no differential current, the congruent relationship between
increased differential current and increased restraint current is used to judge if there is a
internal or external fault, strong anti-saturation ability can be get according to this method.
The above methods can prevent current differential protection from mal-operation if there is more
than 1/4 cycle before CT is saturated.
3-96
3 Operation Theory
2.
The sending and receiving channels are of same route or same propagation delay (i.e. the
propagation delay of the two directions shall be equivalent).
Please refer to section 3.8 for more detail about optical pilot channel.
3.9.2.10 CT Ratio Adjust
If the ratio of CTs on two ends of the line is different, current of two ends must be corrected to one
reference value. PCS-931 regards local end as the referenced end, differential current and
restraint current can be calculated since the current of the remote end is corrected by the setting.
[87L.K_Cr_CT].
Setting principle: Suppose CT ratio, Terminal M: k M=IM1n : IM2n; Terminal N: kN=IN1n : IN2n
IM1n: primary rated current of terminal M, IM2n: secondary rated current of terminal M
IN1n: primary rated current of terminal N, IN2n: secondary rated current of terminal N
If IM1n>= IN1n
Terminal M: [87L.K_Cr_CT]=1.00
Terminal N: [87L.K_Cr_CT]=IN1n / IM1n
For example:
Terminal M: CT ratio=1250 : 5, the setting [87L.K_Cr_CT] is set as 0.5
Terminal N: CT ratio=2500 : 1, the setting [87L.K_Cr_CT] is set as 1.0
If current of terminal M is IM, current of terminal N is IN, the differential current and restraint current
calculated on terminal M is:
I Diff IM
IN
87L.K_Cr_CT
I Bias IM
IN
87L.K_Cr_CT
3-97
3 Operation Theory
87L.On
87L.FOx.En2
87L.FOx.Op
87L.FOx.Blk
87L.Op
87L.Op_A
87L.Op_B
87L.Op_C
87L.Op_DPFC1
87L.Op_DPFC2
87L.Op_Biased1
87L.Op_Biased2
87L.Op_Neutral
87L.Op_InterTrp
87L.FOx.Alm_Diff
87L.FOx.Alm_Comp
Input Signal
87L.FOx.En1
87L.FOx.En2
87L.FOx.Blk
No.
Output Signal
Description
Current differential protection enabling input 1, it is triggered from binary input
or programmable logic etc. (corresponding to channel x)
Current differential protection enabling input 2, it can be a binary inputs or a
logic link. (corresponding to channel x)
Current differential protection blocking input, it is triggered from binary input or
programmable logic etc. (corresponding to channel x)
Description
87L.On
87L.FOx.On
87L.Op
87L.Op_A
87L.Op_B
87L.Op_C
3-98
3 Operation Theory
7
87L.Op_DPFC1
87L.Op_DPFC2
87L.Op_Biased1
10
87L.Op_Biased2
11
87L.Op_Neutral
12
87L.Op_InterTrp
13
87L.FOx.Alm_Diff
14
87L.FOx.Alm_Comp
The settings [XC1] and [XC0] and differential current of the device for channel
x are mismatched.
|IDiff_Actual|<0.7|IDiff_Cal|
or
|IDiff_Cal|<0.7|IDiff_Actual|
under
normal condition.
3.9.5 Logic
3.9.5.1 Common Element
SIG
87L.FOx.En1
SIG
87L.FOx.En2
EN
[87L.En]
SIG
87L.FOx.Blk
SIG
87L.FOx.En1
SIG
87L.FOx.En2
EN
[87L.En]
SIG
&
&
FOx.Enable DIFF (Local end)
&
&
FOx.Enable DIFF (Remote end)
87L.FOx.Blk
Setting by the remote end
SIG
SIG
&
87L.FO1.On
>=1
87L.On
SIG
&
87L.FO2.On
SIG
Where:
FOx.Enable DIFF (Local end): local current differential protection is enabled corresponding to
channel x
FOx.Enable DIFF (Remote end): remote current differential protection is enabled corresponding to
channel x
3-99
3 Operation Theory
SET
IDiff>[87L.I_Pkp_CTS]
EN
[87L.En_CTS_Blk]
SIG
CT circuit failure
SIG
87L.FOx.Alm_Diff
SIG
87L.FOx.On
SET
IDiff>[87L.I_Pkp](A)
SET
IDiff>0.15IBias(A)
&
>=1
>=1
&
&
Differential condition 1 (phase A)
&
Common differential condition (phase A)
&
Differential condition 1 (phase B)
SET
IDiff>[87L.I_Pkp](B)
&
Common differential condition (phase B)
SET
IDiff>0.15IBias(B)
&
Differential condition 1 (phase C)
SET
IDiff>[87L.I_Pkp](C)
&
Common differential condition (phase C)
SET
IDiff>0.15IBias(C)
SIG
SIG
EN
[87L.En_LocDiff]
SIG
SIG
SIG
SIG
SIG
FD.Pkp
&
Differential condition 2 (phase A)
>=1
&
Differential condition 2 (phase B)
>=1
&
>=1
Where:
IDiff: differential current
IBias: restraint current
A: phase A
B: phase B
3-100
3 Operation Theory
C: phase C
DIFF permitted (phase A/B/C): current differential protection permissive signal for phase A/B/C
that received from the remote end via communication channel. Please refer to section 3.9.5.7
about the conditions to send permissive signal.
3.9.5.2 DPFC Differential Element
SIG
SIG
SIG
SIG
SIG
SIG
EN
[87L.En_DPFC1]
SIG
87L.Op_DPFC1 (phase A)
SIG
87L.Op_DPFC1 (phase B)
SIG
87L.Op_DPFC1 (phase C)
SIG
SIG
SIG
SIG
SIG
SIG
EN
[87L.En_DPFC2]
SIG
87L.Op_DPFC2 (phase A)
SIG
87L.Op_DPFC2 (phase B)
SIG
87L.Op_DPFC2 (phase C)
&
87L.Op_DPFC1 (phase A)
&
87L.Op_DPFC1 (phase B)
&
87L.Op_DPFC1 (phase C)
>=1
87L.Op_DPFC1
&
1 cycles
0ms
87L.Op_DPFC2 (phase A)
1 cycles
0ms
87L.Op_DPFC2 (phase B)
1 cycles
0ms
87L.Op_DPFC2 (phase C)
&
&
>=1
87L.Op_DPFC2
Where:
DPFC DIFF1: stage 1 of DPFC differential element
DPFC DIFF2: stage 2 of DPFC differential element
3-101
3 Operation Theory
SIG
SIG
SIG
SIG
SIG
EN
[87L.En_Biased1]
SIG
87L.Op_Biased1 (phase A)
SIG
87L.Op_Biased1 (phase B)
SIG
87L.Op_Biased1 (phase C)
SIG
SIG
SIG
SIG
SIG
SIG
EN
[87L.En_Biased2]
SIG
87L.Op_Biased2 (phase A)
SIG
87L.Op_Biased2 (phase B)
SIG
87L.Op_Biased2 (phase C)
&
87L.Op_Biased1 (phase A)
&
87L.Op_Biased1 (phase B)
&
87L.Op_Biased1 (phase C)
>=1
87L.Op_Biased1
&
1 cycles
0ms
87L.Op_Biased2 (phase A)
1 cycles
0ms
87L.Op_Biased2 (phase B)
1 cycles
0ms
87L.Op_Biased2 (phase C)
&
&
>=1
87L.Op_Biased2
Where:
Steady-state DIFF1: stage 1 of steady-state differential element
Steady-state DIFF2: stage 2 of steady-state differential element
3-102
3 Operation Theory
SIG
SIG
SIG
SIG
SIG
EN
[87L.En_Neutral]
SIG
87L.Op_Neutral (phase A)
SIG
87L.Op_Neutral (phase B)
SIG
87L.Op_Neutral (phase C)
&
t
0ms
87L.Op_Neutral (phase A)
0ms
87L.Op_Neutral (phase B)
0ms
87L.Op_Neutral (phase C)
&
&
>=1
87L.Op_Neutral
SIG
SIG
52b_PhA
SIG
SIG
SIG
52b_PhB
SIG
SIG
SIG
52b_PhC
&
&
>=1
87L.InterTrp_Pkp
&
3-103
3 Operation Theory
SIG
SIG
SIG
52b_PhA
SIG
SIG
SIG
52b_PhB
SIG
SIG
SIG
52b_PhC
EN
[87L.En_InterTrp]
SIG
87L.Op_InterTrp (phase A)
SIG
87L.Op_InterTrp (phase B)
SIG
87L.Op_InterTrp (phase C)
&
&
10ms
0ms
87L.Op_InterTrp (phase A)
10ms
0ms
87L.Op_InterTrp (phase B)
10ms
0ms
87L.Op_InterTrp (phase C)
&
&
&
&
>=1
87L.Op_InterTrp
3U0>1V
SIG
3U2>6V
SIG
UA<0.65UN
SIG
UB<0.65UN
SIG
UC<0.65UN
SIG
UAB<0.65UNN
SIG
UBC<0.65UNN
SIG
UCA<0.65UNN
SIG
VTS.Alm
SIG
4Ia<Ia_Rmt
SIG
4Ib<Ib_Rmt
SIG
4Ic<Ic_Rmt
SIG
Permissive signal
SIG
[87L.FOx.Alm_Diff]
SIG
[CTS.Alm]
>=1
>=1
>=1
&
>=1
Weak infeed logic
>=1
>=1
&
>=1
30ms
3-104
3 Operation Theory
Where:
Ia, Ib, Ic are three phases current of local end
Ia_Rmt, Ib_Rmt, Ic_Rmt are three phases current of remote end
UN is rated phase-to-ground voltage
UNN is rated phase-to-phase voltage
3.9.5.7 Send Permissive Signal
SIG
52b_PhA
SIG
52b_PhB
SIG
52b_PhC
SIG
SIG
FD.Pkp
&
>=1
&
Send permissive signal (phase A)
SIG
&
Send permissive signal (phase B)
Differential condition 1 (phase B)
SIG
&
Send permissive signal (phase C)
Differential condition 1 (phase C)
SIG
At weak infeed end, current fault detector element may not operate, weak infeed logic is used as
alternate to determine fault condition by analyzing the voltage and current signals.
3.9.5.8 Differential Protection Self-check
SIG
SIG
SIG
SIG
87L.FOx.On
SIG
>=1
&
10s
87L.FOx.Alm_Diff
&
2s
EN
10s
10s
87L.FOx.Alm_Comp
[87L.En_CapCurrComp]
Where:
FOx: channel x
3-105
3 Operation Theory
3.9.6 Settings
Table 3.9-2 Settings of current differential protection
No.
Name
Range
Step
Unit
87L.I_Pkp
(0.050~30.000)In
0.001
87L.K_Cr_CT
0.200~10.000
0.001
87L.I_Pkp_CTS
(0.050~30.000)In
0.001
87L.XC1L
(40~60000)/In
ohm
87L.XC0L
(40~60000)/In
ohm
87L.Z_LocReac
(40~60000)/In
ohm
87L.Z_LocGndReac
(40~60000)/In
ohm
87L.Z_RmtReac
(40~60000)/In
ohm
87L.Z_RmtGndReac
(40~60000)/In
ohm
Remark
Minimum pickup current setting
of current differential protection
Current ratio factor of CT
87L.En
capacitive
10
capacitive
differential
protection
0 or 1
0: disable
1: enable
Enabling/disabling stage 1 of
DPFC
11
87L.En_DPFC1
0 or 1
current
differential
element
0: disable
1: enable
Enabling/disabling stage 2 of
DPFC
12
87L.En_DPFC2
0 or 1
current
differential
element
0: disable
1: enable
Enabling/disabling stage 1 of
steady-state current differential
13
87L.En_Biased1
0 or 1
element
0: disable
1: enable
3-106
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Enabling/disabling stage 2 of
steady-state current differential
14
87L.En_Biased2
0 or 1
element
0: disable
1: enable
Enabling/disabling
15
87L.En_Neutral
neutral
0 or 1
0: disable
1: enable
Enabling/disabling inter-tripping
16
87L.En_InterTrp
element
0 or 1
0: disable
1: enable
Enabling/disabling
local
87L.En_LocDiff
local
0 or 1
protection
current
means
differential
18
87L.En_CapCurrComp
capacitive
current compensation
0 or 1
0: disable
1: enable
Enabling/disabling
differential
19
87L.En_CTS_Blk
0 or 1
protection
current
blocked
3-107
3 Operation Theory
both ends. The channel may be dedicated or multiplexed channel through optical fiber or any other
communication media. Pilot distance protection has schemes of permissive underreaching
transfer trip (PUTT), permissive overreaching transfer trip (POTT) and blocking. The device
provides duplicated pilot distance protections with dual channels. The communication media and
mode can be independent each other.
85-x.Z.En1
SIG
85-x.Z.En2
EN
[85.Z.En]
SIG
85-x.Z.Blk
&
&
85-x.Z.On
Pilot distance protection receives and sends signals via pilot channel, and the logic of receiving
signal is shown in Figure 3.10-2.
3-108
3 Operation Theory
SET
[85.Opt_PilotMode]=Blocking
&
>=1
85-x.Valid_Recv1
SIG
85-x.Recv1
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid
&
>=1
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
&
>=1
FD.Pkp
SIG
85-x.ZX.En1
SIG
85-x.ZX.En2
EN
[85.ZX.En]
SIG
85-x.ZX.Blk1
SIG
85-x.ZX.Blk2
SIG
79.Ready
SIG
Zpilot
&
&
&
85-x.ZX.On
>=1
&
[85.t_DPU_ZX]
&
0ms
85-x.Op_ZX
Zone extension uses the setting of pilot zone (ZPilot), and its operation characteristic can be Mho
3-109
3 Operation Theory
or Quad.
3.10.2.2 Permissive Underreaching Transfer Trip (PUTT)
Distance elements zone 1 (Z1) with underreaching setting and pilot zone (ZPilot) with
overreaching setting are used for this scheme. Z1 element will send permissive signal to the
remote end and release tripping after Z1 time delay expired. After receiving permissive signal with
ZPilot element pickup, a tripping signal will be released.
The signal transmission element for PUTT is set according to underreaching mode, so current
reversal need not be considered.
For PUTT, there may be a dead zone under weak power source condition. If the fault occurs
outside Z1 zone at strong power source side, Z1 at weak power supply side may not operate to trip
and transmit permissive signal, and pilot distance protection will not operate. Therefore, the
system fault can only be removed by Z2 at strong power source side with time delay.
ZPilot
Z2
Z1
EM
Fault
Z1
EN
Z2
ZPilot
Relay A
Relay B
Z1
Z1
&
&
85-x.Op_Z
85-x.Op_Z
ZPilot
ZPilot
Pilot distance protection always adopts pilot channel 1, and the logic of PUTT is shown in Figure
3.10-5.
3-110
3 Operation Theory
SIG
21M1(21Q1).Op
0ms
100ms
85-x.ExTrp
0ms
150ms
>=1
&
SIG
SET
[85.Opt_PilotMode]=PUTT
SIG
85-x.Z.On
SIG
FD.Pkp
SIG
85-x.Valid_Recv1
SIG
ZPilot
85-x.Send1
&
&
&
8ms
0ms
85-x.Op_Z
EM
Zpilot_Rev
A
Fault
EN
N
Zpilot_Rev
Z2
ZPilot
Relay A
ZPilot
&
>=1
Relay B
&
85-x.Op_Z
85-x.Op_Z
WI
>=1
ZPilot
WI
3-111
3 Operation Theory
SIG
Zpilot
SIG
85-x.ExTrp
SIG
CB open position
>=1
0ms
150ms
&
>=1
&
200ms
0ms
&
SIG
85-x.Valid_Recv1
SIG
ZPilot
&
>=1
SIG
85-x.Z.On
SIG
WI
85-x.Send1
&
&
t1
t2
&
85-x.Op_Z
&
8ms
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=POTT
0ms
Where:
t1: pickup time delay of current reversal, the setting [85.t_DPU_CR1]
t2: dropoff time delay of current reversal, the setting [85.t_DDO_CR1]
3.10.2.4 Blocking
Permissive scheme has high security, but it relies on pilot channel seriously. Pilot distance
protection will not operate when there is an internal fault with abnormal channel. Blocking scheme
could be considered as an alternative.
Blocking scheme takes use of pilot distance element Zpilot operation to terminate sending of
blocking signal. Blocking signal will be sent once fault detector picks up without pilot zone Zpilot
operation. Pilot distance protection will operate with a short time delay if pilot distance element
operates and not receiving blocking signal after timer expired.
The setting of pilot zone element Zpilot in Blocking scheme is overreaching, so current reversal
condition should be considered. However, the short time delay of pilot distance protection has an
enough margin for current reversal, that this problem has been resolved.
The short time delay must consider channel delay and with a certain margin to set. As shown in
Figure 3.10-8, an external fault happens to line MN. The fault is behind the device at M side, for
blocking scheme, the device at M side will send blocking signal to the device at N side. If channel
delay is too long, the device at side N has operated before receiving blocking signal. Hence, the
time delay of pilot distance protection adopted in blocking scheme should be set according to
channel delay.
3-112
3 Operation Theory
Blocking signal
EM
Fault
EN
For blocking scheme, pilot distance protection will operate when there is an internal fault with
abnormal channel, however, it is possible that pilot distance protection issue an undesired trip
when there is an external fault with abnormal channel.
ZPilot
EM
Zpilot_Rev
A
Fault
EN
Zpilot_Rev
ZPilot
Relay A
Relay B
FD.Pkp
&
Zpilot
&
[85.t_DPU_Blocking1]
85-x.Op_Z
85-x.Op_Z
&
FD.Pkp
&
Zpilot
[85.t_DPU_Blocking1]
3-113
3 Operation Theory
SIG
Zpilot
SIG
85-x.ExTrp
SIG
CB open position
>=1
0ms
150ms
&
&
200ms
SIG
>=1
0ms
&
85-x.Valid_Recv1
85-x.Send1
&
SIG
FwdDir_ZPilot
SIG
WI
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=Blocking
SIG
85-x.Z.On
>=1
&
[85.t_DPU_Blocking1]
85-x.Op_Z
&
Current reversal logic is only used for permissive scheme. For blocking scheme, the time delay of
pilot distance protection has enough margin for current reversal, so current reversal need not be
considered.
3.10.2.5 Unblocking
Permissive scheme will trip only when it receives permissive signal from the remote end. However,
it may not receive permissive signal from the remote end when pilot channel fails. For this case,
pilot distance protection can adopt unblocking scheme. Under normal conditions, the signaling
equipment works in the pilot frequency, and when the device operates to send permissive signal,
the signaling equipment will be switched to high frequency. While pilot channel is blocked, the
signaling equipment will receive neither pilot frequency signal nor high frequency signal. The
signaling equipment will provide a contact to the device as unblocking signal. When the device
receives unblocking signal from the signaling equipment, it will recognize channel failure, and
unblocking signal will be taken as permissive signal temporarily.
The unblocking function can only be used together with PUTT and POTT.
EN
[85.En_Unblocking1]
SIG
85-x.Unblocking1
&
&
[85.t_Unblocking1] 0ms
SIG
SET
[85.Opt_PilotCh1]
SIG
>=1
&
85-x.Unblocking1 Valid
3 Operation Theory
N
A
M
Weak
source
EN
N
A
B
EN
EM
As shown above, the device A judges a forward fault while the device B judges a reverse fault
before break D is tripped. However, the device A judges a reverse fault while the device B judges a
forward fault after breaker D is tripped. There is a competition between pickup and drop off of pilot
zones in the device A and the device B when the fault measured by the device A changes from
forward direction into reverse direction and vice versa for the device B. There may be
maloperation for the device in line A-B if the forward direction of the device B has operated but the
forward direction of the device A drops off slightly slower or the forward direction of the device B
has operated but the forward direction information of the device A is still received due to the
channel delay (the permissive signal is received).
In general, the following two methods shall be adopted to solve the problem of current reversal:
1.
The fault shall be measured by means of the reverse element of the device B. Once the
reverse element of the device B operates, the send signals and the tripping circuit will be
blocked for a period of time after a short time delay. This method can effectively solve the
problem of competition between the device A and the device B, but there shall be a
precondition. The reverse element of the device B must be in cooperation with the forward
element of the device A, i.e. in case of a fault in adjacent lines, if the forward element of the
device A operates, and the reverse element of the device B must also operate. Once the
bilateral cooperation fails, the anticipated function cannot be achieved. In addition, the
blocking time for sending signals and the tripping circuit after the reverse element of the
device B operates shall be set in combination with the channel time delay.
2.
Considering the pickup and drop off time difference of distance elements and the channel time
delay between the device A and the device B, the maloperation due to current reversal shall
be eliminated by setting the time delay. The reverse direction element of the device is not
required for this method, the channel time delay and the tripping time of adjacent breaker
shall be taken into account comprehensively.
This protection device adopts the second method to eliminate the maloperation due to current
reversal.
3-115
3 Operation Theory
SIG
&
t1
SIG
t2
t1: [85.t_DPU_CR1]
t2: [85.t_DDO_CR1]
Referring to above figure, when signal from the remote end is received without pilot forward zone
pickup, the current reversal blocking logic is enabled after t1 delay.
The time delay of t1 [85.t_DPU_CR1] shall be set the shortest possible but allowing sufficient time
for pilot forward zone pickup, generally set as 25ms.
Once the current reversal logic is enabled, the healthy line device B transfer tripping is blocked.
The logic will be disabled by either the dropoff of signal or the pickup of pilot forward zone. A time
delay t2 [85.t_DDO_CR1] is required to avoid maloperation for the case that the pilot forward zone
(or forward element of pilot directional earth-fault protection) of device B picks up before the signal
from device A drops off. Considering the channel propagation delay and the pickup and drop-off
time difference of pilot forward zone (or pilot directional earth-fault element) with margin, t2 is
generally set between 25ms~40ms.
Because the time delay of pilot distance protection has an enough margin to current reversal,
current reversal blocking only used for permissive scheme not blocking scheme.
3.10.2.7 Weak Infeed
In case of a fault in line at one end of which there is a weak power source, the fault current
supplied to the fault point from the weak power source is very small or even nil, and the
conventional distance element could not operate. The weak infeed logic combines the protection
information from the strong power source end and the electric feature of the local end to cope with
the case.
The weak infeed logic can be only applied for BOTT and POTT. The weak infeed logic has options
for echo or both echo and tripping.
ZPilot
Z1
M
EM
Zpilot_Rev
Fault
Zpilot_Rev
B
Z1
EN
ZPilot
Load
3 Operation Theory
When the weak infeed logic is enabled, distance forward and reverse element and direction
element of directional earth-fault protection do not operate with the voltage lower than the setting
[85.U_UV_WI] after the device picks up, upon receiving signal from remote end, the weak infeed
logic will echo the signal back to remote end for 200ms if the weak infeed echo is enabled, the
weak infeed end will echo signal and release tripping according to the logic.
ZPilot_Rev at weak source end must coordinate with ZPilot_Set of the remote end. The coverage
of ZPilot_Rev must exceed that of ZPilot_Set of the remote end. ZPilot_Rev only activates in the
protection calculation when the weak infeed logic is enabled. In case of the weak infeed logic not
enabled, the setting coordination is not required.
If the device does not pick up, and the weak infeed logic is enabled, upon receiving signal from
remote end with the voltage lower than the setting [85.U_UV_WI], the weak infeed logic will echo
back to remote end for 200ms. When either weak infeed echo or weak infeed tripping is enabled,
then the weak infeed logic is deemed to be enabled. During the device picking up, the weak infeed
logic is shown in Figure 3.10-15.
SIG
FD.Pkp
SIG
85-x.Valid_Recv1
SIG
SIG
SIG
SIG
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
SET
Upp<[85.U_UV_WI]
>=1
&
&
Forward direction (WI)
>=1
>=1
200ms
0ms
&
If the device does not pick up, the weak infeed logic is shown as the following figure:
SIG
EN
[85.En_WI]
SET
Up<[85.U_UV_WI]
SET
Upp<[85.U_UV_WI]
&
&
WI echo
>=1
200ms
0ms
&
For permissive scheme, the signal receive condition means that the permissive signal is received
or the unblocking signal is valid.
3-117
3 Operation Theory
3.10.2.8 CB Echo
A feature is also provided which enables fast tripping to be maintained along the whole length of
the protected line, even when one terminal is open. The device will initiate sending a pulse of
200ms permissive signal when signal receive condition is met during CB is in open position.
SIG
FD.Pkp
SIG
CB open position
SIG
85-x.Valid_Recv1
SET
[85.Opt_PilotMode]=POTT
&
&
200ms
0ms
&
Send permissive signal
&
CB Echo logic is only applied to permissive overreach mode not underreach mode, and it is
processed without the device pickup. This logic will be terminated immediately once the device
picks up.
85-x.Z.On
85-x.Z.En2
85-x.ZX.On
85-x.Z.Blk
85-x.Op_Z
85-x.Abnor_Ch1
85-x.Send1
85-x.Rcv1
85-x.SendB
85-x.RcvB
85-x.SendC
85-x.RcvC
85-x.Op_ZX
85-x.ExTrp
85-x.ZX_St
85-x.Unblocking1
85-x.ZX.En1
85-x.ZX.En2
85-x.ZX.Blk1
85-x.ZX.Blk2
79.Ready
3-118
3 Operation Theory
Input Signal
85-x.Z.En1
85-x.Z.En2
85-x.Z.Blk
85-x.Abnor_Ch1
Description
Pilot distance protection x enabling input 1, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Pilot distance protection x enabling input 2, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Pilot distance protection x blocking input, it is triggered from binary input or
programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot distance
protection x (x=1 or 2)
Input signal of receiving permissive signal via channel No.1 for pilot distance
85-x.Recv1
85-x.RecvB
85-x.RecvC
85-x.ExTrp
85-x.Unblocking1
10
85-x.ZX.En1
11
85-x.ZX.En2
12
85-x.ZX.Blk1
13
85-x.ZX.Blk2
14
79.Ready
No.
Input signal of receiving permissive signal of B-phase via channel No.1 for pilot
distance protection x (only for phase-segregated command scheme, x=1 or 2)
Input signal of receiving permissive signal of C-phase via channel No.1 for pilot
distance protection x (only for phase-segregated command scheme, x=1 or 2)
Input signal of initiating sending permissive signal from external tripping signal for
pilot distance protection x (x=1 or 2)
Unblocking signal 1 of pilot distance protection x (x=1 or 2)
Zone Extension enabling input 1 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension enabling input 2 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 1 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
Zone Extension blocking input 2 of pilot distance protection x, it is triggered from
binary input or programmable logic etc. (x=1 or 2)
AR has been ready for reclosing cycle.
Output Signal
Description
85-x.Z.On
85-x.ZX.On
85-x.Op_Z
85-x.Send1
85-x.SendB
85-x.SendC
3-119
3 Operation Theory
7
85-x.Op_ZX
85-x.ZX_St
3.10.5 Settings
Table 3.10-2 Settings of pilot distance protection
No.
Name
Range
Step
Unit
Remark
POTT
1
85.Opt_PilotMode
PUTT
Blocking
Option of
phase-segregated
85.Opt_Ch_PhSeg
signal scheme
0 or 1
phase-segregated
signal
scheme
Enabling/disabling weak infeed
3
85.En_WI
scheme
0 or 1
0: disable
1: enable
85.U_UV_WI
0~Unn
0.001
85.Z.En
pilot
distance protection
0 or 1
0: disable
1: enable
Enabling/disabling unblocking
85.En_Unblocking1
scheme
0 or 1
0: disable
1: enable
Time
85.t_DPU_Blocking1
0.000~1.000
0.001
delay
scheme
of
for
blocking
pilot
distance
protection operation
8
85.t_DDO_CR1
0.000~1.000
0.001
85.t_DPU_CR1
0.000~1.000
0.001
10
85.ZX.En
zone
extension protection
0 or 1
0: disable
1: enable
11
85.t_DPU_ZX
0.000~10.000
0.001
3-120
3 Operation Theory
Table 3.10-3 Internal settings of pilot distance protection
No.
1
Name
Default Value
85.t_Unblocking1
0.1
Unit
Remark
Pickup time delay of unblocking scheme for pilot
channel 1
Option of PLC channel for pilot channel 1
85.Opt_PilotCh1
0: phase-to-phase channel
1: phase-to-ground channel
85-x.DEF.En1
SIG
85-x.DEF.En2
EN
[85.DEF.En]
SIG
85-x.DEF.Blk
&
&
85-x.DEF.On
Pilot directional earth-fault protection comprises permissive scheme and blocking scheme. It can
share pilot channel 1 ([85.DEF.En_IndepCh]=0) with pilot distance protection, or uses independent
3-121
3 Operation Theory
[85.Opt_PilotMode]=Blocking
SIG
85-x.Recv1
&
>=1
&
SIG
85-x.Abnor_Ch1
SIG
85-x.Unblocking1 Valid
SET
[85.Opt_PilotMode]=PUTT
&
>=1
>=1
85-x.Valid_Recv_DEF
EN
[85.DEF.En_IndepCh]
SET
[85.Opt_PilotMode]=Blocking
&
&
>=1
SIG
85-x.Recv2
SIG
85-x.Abnor_Ch2
SIG
85-x.Unblocking2 Valid
&
FwdDir_ROC
&
85-x.FwdDir_DEF_Pilot
SIG
3I0>[85.DEF.3I0_Set]
SIG
RevDir_ROC
&
85-x.RevDir_DEF_Pilot
SIG
FD.ROC.Pkp
3-122
3 Operation Theory
85-x.FwdDir_DEF_Pilot
85-x.RevDir_DEF_Pilot
EM
Fault
EN
85-x.RevDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
Relay A
85-x.FwdDir_DEF_Pilot
&
&
[85.DEF.t_DPU]
85-x.Op_DEF
85-x.Op_DEF
[85.DEF.t_DPU]
85-x.FwdDir_DEF_Pilot
Relay B
For blocking scheme, pilot directional earth-fault protection will operate when there is an internal
fault with abnormal channel, however, it is possible that pilot directional earth-fault protection issue
an undesired trip when there is an external fault with abnormal channel.
0ms
SIG
85-x.ExTrp
SIG
CB open position
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SIG
85-x.FwdDir_DEF_Pilot
SIG
85-x.RevDir_DEF_Pilot
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=PUTT
SET
[85.Opt_PilotMode]=POTT
SIG
85-x.DEF.On
150ms
&
>=1
&
200ms
0ms
&
85-x.Send_DEF
&
&
&
t1
t2
&
>=1
&
&
&
[85.DEF.t_DPU]
>=1
85-x.Op_DEF
&
EN
[85.DEF.En_IndepCh]
3 Operation Theory
EM
85-x.RevDir_DEF_Pilot
Fault
EN
85-x.RevDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
Relay A
Relay B
FD.Pkp
FD.Pkp
&
85-x.RevDir_DEF_Pilot
&
&
&
85-x.FwdDir_DEF_Pilot
85-x.FwdDir_DEF_Pilot
&
&
85-x.Op_DEF
&
85-x.RevDir_DEF_Pilot
85-x.Op_DEF
[85.DEF.t_DPU]
&
[85.DEF.t_DPU]
3-124
3 Operation Theory
SIG
Trp
SIG
85-x.ExTrp
SIG
CB open position
SIG
85-x.FwdDir_DEF_Pilot
SIG
85-x.RevDir_DEF_Pilot
SIG
85-x.Valid_Recv_DEF
SIG
FD.Pkp
SET
[85.Opt_PilotMode]=Blocking
SIG
85-x.DEF.On
>=1
0ms
150ms
>=1
&
85-x.Send_DEF
&
&
&
[85.DEF.t_DPU]
85-x.Op_DEF
&
When DEF shares pilot channel 1 with pilot distance protection, time delay of pilot directional
earth-fault protection will change from the setting [85.DEF.t_DPU] to the setting
[85.t_DPU_Blocking1].
Because the time delay of pilot directional earth-fault protection has enough margin for current
reversal, so blocking scheme should not consider the current reversal condition.
3.11.2.3 Unblocking
Permissive scheme will operate only when it receives permissive signal from the remote end.
However, it may not receive permissive signal from the remote end when pilot channel fails. For
this case, pilot directional earth-fault protection can adopt unblocking scheme. Under normal
conditions, the signaling equipment works in the pilot frequency, and when the device operates to
send permissive signal, the signaling equipment will be switched to high frequency. While the
channel is blocked, the signaling equipment will receive neither pilot frequency signal nor high
frequency signal. The signaling equipment will provide a contact to the device as unblocking signal.
When the device receives unblocking signal from the signaling equipment, it will recognize
channel failure, and unblocking signal will be taken as permissive signal temporarily.
The unblocking scheme can only be used together with permissive scheme.
EN
[85.En_Unblocking2]
SIG
85-x.Unblocking2
&
&
&
[85.t_Unblocking2]
SIG
Selection of multi-phase
EN
[85.Opt_PilotCh2]
SIG
85-x.Unblocking2 Valid
0ms
>=1
3 Operation Theory
85-x.DEF.On
85-x.DEF.En2
85-x.Op_DEF
85-x.DEF.Blk
85-x.DEF_BlkAR
85-x.Abnor_Ch1
85-x.Send1
85-x.Abnor_Ch2
85-x.Send2
85-x.Rcv1
85-x.Rcv2
85-x.ExTrp
85-x.Unblocking1
85-x.Unblocking2
Input Signal
85-x.DEF.En1
85-x.DEF.En2
85-x.DEF.Blk
85-x.Abnor_Ch1
85-x.Abnor_Ch2
Description
Pilot directional earth-fault protection x enabling input 1, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x enabling input 2, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Pilot directional earth-fault protection x blocking input, it is triggered from binary
input or programmable logic etc. (x=1 or 2)
Input signal of indicating that pilot channel 1 is abnormal for pilot directional
earth-fault protection x (x=1 or 2)
Input signal of indicating that pilot channel 2 is abnormal for pilot directional
earth-fault protection x (x=1 or 2)
3-126
3 Operation Theory
Input signal of receiving permissive signal via channel 1 for pilot directional
85-x.Recv1
85-x.Recv2
85-x.ExTrp
85-x.Unblocking1
10
85-x.Unblocking2
No.
Output Signal
Description
85-x.DEF.On
85-x.Op_DEF
85-x.DEF_BlkAR
85-x.Send1
85-x.Send2
3.11.5 Settings
Table 3.11-2 Settings of pilot directional earth-fault protection
No.
Name
Range
Step
Unit
Remark
Enabling/disabling pilot directional
85.DEF.En
earth-fault protection
0 or 1
0: disable
1: enable
Enabling/disabling pilot directional
earth-fault protection operate to
block AR
85.DEF.En_BlkAR
0 or 1
for
pilot
independent
directional
earth-fault protection
3
85.DEF.En_IndepCh
0:
0 or 1
pilot
directional
earth-fault
pilot
directional
earth-fault
85.En_Unblocking2
Enabling/disabling
0 or 1
unblocking
3-127
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
channel 2
0: disable
1: enable
85.DEF.3I0_Set
(0.050~30.000)In
0.001
85.DEF.t_DPU
0.001~10.000
0.001
85.t_DPU_CR2
0.000~1.000
0.001
directional
earth-fault protection
Time
pilot
delay
pickup for
current
protection
adopts
85.t_DDO_CR2
0.000~1.000
0.001
protection
adopts
Name
Default Value
85.t_Unblocking2
Unit
0.2
Remark
Pickup time delay of unblocking scheme for pilot
channel 2
Option of PLC channel for pilot channel 2
85.Opt_PilotCh2
0: phase-to-phase channel
1: phase-to-ground channel
M
C
Fault
N
A
EN
When line LM has an earth fault, the fault currents flowing through the relay A and the relay D are
of similar magnitude in most cases. It is desirable that the fault is isolated from the power system
by tripping the circuit breaker C and circuit breaker D. Hence, the overcurrent protection of relay A
and relay D require to associate with current direction to fulfill selective tripping.
Directional earth fault protection has a time delay due to coordinate with that of downstream so it
3-128
3 Operation Theory
cannot clear the fault quickly. Pilot directional earth-fault protection, which is fulfilled by directional
earth fault element on both ends, it can maintain fast operation and achieve high sensitivity to
detect high resistance fault.
Forward direction
Reverse direction
Where:
is the setting [RCA_OC]
3-129
3 Operation Theory
2.
From above diagram can be seen, when =, P reaches to the maximum value. It is considered
as the most sensitive forward direction. Hence, is called as sensitivity angle of phase
overcurrent protection.
1.
In the event of asymmetrical fault, because phase or phase-to-phase voltage may decrease to
very low voltage whereas positive-sequence voltage does not, the polarized voltage of phase or
phase-to-phase current direction uses positive-sequence voltage to avoid wrong direction due to
too low polarized voltage. Therefore, using positive-sequence voltage as polarized voltage can
ensure that the direction determination has no dead zone for asymmetrical fault. For symmetric
fault, if positive-sequence voltage decreases to 15%Un, the device uses memorized
positive-sequence voltage as polarized voltage, the memorized positive-sequence voltage is 1.5
cycles pre-fault positive-sequence voltage.
2.
When using normal polarized voltage to calculate phase and phase-to-phase current direction,
there are total twelve direction determination algorithm including forward direction and reverse
direction.
Table 3.12-1 Direction description
Direction
Phase A
Phase B
Phase C
Phase AB
Phase BC
Phase CA
3.
Polarized Voltage
Current
Forward direction
U1a
Ia
Reverse direction
U1a
Ia
Forward direction
U1b
Ib
Reverse direction
U1b
Ib
Forward direction
U1c
Ic
Reverse direction
U1c
Ic
Forward direction
U1ab
Iab
Reverse direction
U1ab
Iab
Forward direction
U1bc
Ibc
Reverse direction
U1bc
Ibc
Forward direction
U1ca
Ica
Reverse direction
U1ca
Ica
When the symmetrical fault occurs on a power system, positive-sequence voltage may reduce to
3-130
3 Operation Theory
less than 0.15Un, the device will switch to phase or phase-to-phase current direction for
under-voltage condition. The 1.5 cycle pre-fault positive-sequence voltage is used as polarized
voltage with reverse threshold to ensure stable direction decision when three-phase voltage goes
to approximately zero due to close up fault.
At first, the threshold is forward offset before direction is determined, and the threshold will be
reversed offset after direction is determined.
3.12.2.2 Zero-sequence/Negative-sequence Current Direction
By setting the characteristic angle [RCA_ROC] and [RCA_NegOC] to determine the most
sensitive forward angle of zero-sequence current and negative-sequence current, power value is
calculated using zero-sequence current with zero-sequence voltage or negative-sequence current
with negative-sequence voltage to determine the direction of zero-sequence current and
negative-sequence current respectively in forward direction or reverse direction.
When the power value is between 0 and -0.1In, neither forward direction nor reverse direction is
considered.
jX
3U0
-180
-3I0
R
O
3I0
Reverse direction
Forward direction
3 Operation Theory
P=U[ICOS(-)]
1.
Calculating the power value using zero-sequence current (3I0) and zero-sequence voltage (3U0)
to determine the direction of zero-sequence current
According to the equation:
The zero-sequence current and the zero-sequence voltage can be gained by calculation
Zero-sequence power is: P=3U0[3I0COS(-)]
2.
Calculating the power value using negative-sequence current (3I2) and negative-sequence
voltage (3U2) to determine the direction of negative-sequence current
According to the equation:
The negative-sequence current and the negative-sequence voltage can be gained by calculation
Negative-sequence power is: P=3U2[3I2COS(-)]
3.
3-132
3 Operation Theory
is the setting [Z0_Comp], which cannot exceed the total zero-sequence impedance of
the protected line
is the setting [Z2_Comp], which cannot exceed the total negative-sequence impedance
of the protected line
Output Signal
Description
FwdDir_ROC
RevDir_ROC
FwdDir_NegOC
RevDir_NegOC
FwdDir_A
FwdDir_B
3-133
3 Operation Theory
7
FwdDir_C
RevDir_A
RevDir_B
10
RevDir_C
11
FwdDir_AB
12
FwdDir_BC
13
FwdDir_CA
14
RevDir_AB
15
RevDir_BC
16
RevDir_CA
3.12.5 Settings
Table 3.12-3 Settings of current direction
No.
Name
Range
Step
Unit
RCA_OC
30.00~89.00
0.01
deg
RCA_ROC
30.00~89.00
0.01
deg
RCA_NegOC
30.00~89.00
0.01
deg
Z0_Comp
(0.000~4Unn)/In
0.001
ohm
Z2_Comp
(0.000~4Unn)/In
0.001
ohm
Remark
The characteristic angle of directional
phase overcurrent element
The characteristic angle of directional earth
fault element
The characteristic angle of directional
negative-sequence overcurrent element
The
compensated
zero-sequence
impedance
The
compensated
negative-sequence
impedance
Four-stage phase overcurrent protection with independent logic, current and time delay
settings.
2.
3-134
3 Operation Theory
3.
Direction control element can be selected to control each stage phase overcurrent protection
with three options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of phase overcurrent protection.
3.13.2.1 Overview
Phase overcurrent protection consists of following three elements:
1.
2.
Direction control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each phase overcurrent element can individually enable the output signal from
harmonic element as a blocking input.
Equation 3.13-1
Where:
Ip is measured phase current.
[50/51Px.I_Set] is the current setting of stage x (x=1, 2, 3, or 4) of overcurrent element.
3.13.2.3 Direction Control Element
Please refer to section 3.10 for details.
3.13.2.4 Harmonic Blocking Element
When phase overcurrent protection is used to protect feeder-transformer circuits harmonic
blocking function can be selected for each stage of phase overcurrent element by configuring logic
setting [50/51Px.En_Hm2_Blk] (x=1, 2, 3 or 4) to prevent maloperation due to inrush current.
When the percentage of second harmonic component to fundamental component of any phase
current is greater than the setting [50/51P.K_Hm2], harmonic blocking element operates to block
stage x overcurrent element if corresponding logic setting [50/51Px.En_Hm2_Blk] enabled.
Operation criterion:
Equation 3.13-2
Where:
is second harmonic of phase current
3-135
3 Operation Theory
Equation 3.13-3
Where:
Iset is current setting [50/51Px.I_Set].
Tp is time multiplier setting [50/51Px.TMS].
is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Px.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.13-1 Inverse-time curve parameters
50/51Px.Opt_Curve
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
3-136
3 Operation Theory
50/51Px.Opt_Curve
Time Characteristic
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may set [50/51Px.Opt_Curve] as
UserDefine to customize the inverse-time curve characteristic with constants , K and C. (only
stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Px.tmin], then the operating time of the protection changes to the value of setting
[50/51Px.tmin] automatically.
Define-time or inverse-time phase overcurrent protection drops off instantaneously after fault
current disappears.
50/51Px.On
50/51Px.En2
50/51Px.StA
50/51Px.Blk
50/51Px.StB
50/51Px.StC
50/51Px.St
50/51Px.Op
Input Signal
50/51Px.En1
50/51Px.En2
50/51Px.Blk
No.
Description
Stage x of phase overcurrent protection enabling input 1, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection enabling input 2, it is triggered from binary
input or programmable logic etc.
Stage x of phase overcurrent protection blocking input, it is triggered from binary
input or programmable logic etc.
Output Signal
Description
50/51Px.On
50/51Px.Op
50/51Px.St
50/51Px.StA
50/51Px.StB
3-137
3 Operation Theory
6
50/51Px.StC
3.13.5 Logic
EN
[50/51Px.En]
SIG
50/51Px.En1
SIG
50/51Px.En2
SIG
50/51Px.Blk
SET
Ia>[50/51Px.I_Set]
&
&
50/51Px.On
>=1
50/51Px.St
&
50/51Px.StA
SET
Ib>[50/51Px.I_Set]
&
50/51Px.StB
SET
Ic>[50/51Px.I_Set]
&
50/51Px.StC
SET
[50/51Px.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Px.Opt_Dir]=Reverse
SIG
Reverse DIR
SIG
VTS.Alm
EN
[50/51Px.En_VTS_Blk]
SET
[50/51Px.Opt_Dir]=Non-Directional
SIG
I3P
SET
[50/51Px.En_Hm2_Blk]
SIG
50/51Px.On
SIG
FD.Pkp
SET
[50/51Px.Opt_Curve]=DefTime
&
&
>=1
>=1
&
2nd Hm Detect
&
&
&
&
[50/51Px.t_Op]
>=1
50/51Px.Op
&
SIG
Timer
t
50/51Px.St
x=1, 2, 3, 4
3-138
3 Operation Theory
3.13.6 Settings
Table 3.13-3 Settings of phase overcurrent protection
No.
Name
Range
Step
Unit
Remark
Setting
50/51P.K_Hm2
0.000~1.000
0.001
of
component
second
for
harmonic
blocking
phase
overcurrent elements
2
50/51P1.I_Set
(0.050~30.000)In
0.001
50/51P1.t_Op
0.000~20.000
0.001
50/51P1.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P1.En_BlkAR
0 or 1
50/51P1.En_VTS_Blk
0 or 1
VT circuit failure
0: disable
1: enable
Non-Directional
7
50/51P1.Opt_Dir
Forward
overcurrent protection
Reverse
50/51P1.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
DefTime
IECN
IECV
IECE
9
50/51P1.Opt_Curve
IECST
IECLT
stage
ANSIE
protection
of
phase
overcurrent
ANSIV
ANSI
ANSIM
ANSILTE
3-139
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 1 of
10
50/51P1.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection
Minimum operating time for stage 1
11
50/51P1.tmin
0.000~20.000
0.001
12
50/51P1.Alpha
0.010~5.000
for
stage
customized
0.001
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
13
50/51P1.C
0.000~20.000
for
stage
customized
0.001
of
inverse-time
characteristic
phase
overcurrent
protection
Constant
14
50/51P1.K
0.050~20.000
for
stage
customized
0.001
characteristic
of
inverse-time
phase
overcurrent
protection
15
50/51P2.I_Set
(0.050~30.000)In
0.001
16
50/51P2.t_Op
0.000~20.000
0.001
17
50/51P2.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P2.En_BlkAR
0 or 1
19
50/51P2.En_VTS_Blk
0 or 1
VT circuit failure
0: disable
1: enable
Non-Directional
20
50/51P2.Opt_Dir
Forward
overcurrent protection
Reverse
21
50/51P2.En_Hm2_Blk
0 or 1
3-140
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
blocking for stage 2 of phase
overcurrent protection
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
22
50/51P2.Opt_Curve
IECLT
ANSIE
stage
ANSIV
protection
of
phase
overcurrent
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2 of
23
50/51P2.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 2
24
50/51P2.tmin
0.000~20.000
0.001
25
50/51P3.I_Set
(0.050~30.000)In
0.001
26
50/51P3.t_Op
0.000~20.000
0.001
27
50/51P3.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P3.En_BlkAR
0 or 1
29
50/51P3.En_VTS_Blk
0 or 1
VT circuit failure
0: disable
1: enable
30
50/51P3.Opt_Dir
Non-Directional
Forward
overcurrent protection
3-141
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Reverse
Enabling/disabling second harmonic
blocking for stage 3 of phase
31
50/51P3.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
32
50/51P3.Opt_Curve
IECLT
ANSIE
stage
ANSIV
protection
of
phase
overcurrent
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 3 of
33
50/51P3.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 3
34
50/51P3.tmin
0.000~20.000
0.001
35
50/51P4.I_Set
(0.050~30.000)In
0.001
36
50/51P4.t_Op
0.000~20.000
0.001
37
50/51P4.En
overcurrent protection
0 or 1
0: disable
1: enable
Enabling/Disabling
auto-reclosing
50/51P4.En_BlkAR
0 or 1
39
50/51P4.En_VTS_Blk
0 or 1
VT circuit failure
0: disable
1: enable
3-142
3 Operation Theory
No.
Name
Range
Step
Unit
Non-Directional
40
50/51P4.Opt_Dir
Remark
Direction option for stage 4 of phase
Forward
overcurrent protection
Reverse
50/51P4.En_Hm2_Blk
0 or 1
overcurrent protection
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
42
50/51P4.Opt_Curve
IECLT
ANSIE
stage
ANSIV
protection
of
phase
overcurrent
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 4 of
43
50/51P4.TMS
0.010~200.000
0.001
inverse-time
phase
overcurrent
protection.
Minimum operating time for stage 4
44
50/51P4.tmin
0.010~20.000
0.001
Four-stage earth fault protection with independent logic, current and time delay settings.
3-143
3 Operation Theory
2.
3.
Directional element can be selected to control each stage of earth fault protection with three
options: no direction, forward direction and reverse direction.
4.
Second harmonic can be selected to block each stage of earth fault protection.
5.
Stage 2, 3, 4 of earth fault protection can enable short time delay to improve operation speed.
3.14.2.1 Overview
Earth fault protection consists of following three elements:
1.
Overcurrent element: each stage equipped with one independent overcurrent element.
2.
Directional control element: one direction control element shared by all overcurrent elements,
and each overcurrent element can individually select protection direction.
3.
Harmonic blocking element: one harmonic blocking element shared by all overcurrent
elements and each overcurrent element can individually enable the output signal of harmonic
blocking element as a blocking input.
Equation 3.14-1
Where:
3I0 is the calculated residual current.
[50/51Gx.3I0_Set] is the current setting of stage x (x=1, 2, 3, or 4) of earth fault protection.
3.14.2.3 Direction Control Element
Please refer to section 3.10 for details.
3.14.2.4 Harmonic Blocking Element
In order to prevent effects of inrush current on earth fault protection, harmonic blocking function
can be selected for each stage of earth fault element by configuring logic setting
[50/51Gx.En_Hm2_Blk] (x=1, 2, 3 or 4).
When the percentage of second harmonic component to fundamental component of residual
current is greater than the setting [50/51G.K_Hm2], harmonic blocking element operates to block
stage x of earth fault protection if corresponding logic setting [50/51Gx.En_Hm2_Blk] is enabled
Operation criterion:
Equation 3.14-2
3-144
3 Operation Theory
Where:
is second harmonic of residual current
Equation 3.14-3
Where:
Iset is residual current setting [50/51Gx.3I0_Set].
Tp is time multiplier setting [50/51Gx.TMS].
K is a constant
C is a constant.
is a constant.
3I0 is the calculated residual current.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Gx.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.14-1 Inverse-time curve parameters
50/51Gx.Opt_Curve
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
3-145
3 Operation Theory
50/51Gx.Opt_Curve
Time Characteristic
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
UserDefine
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Gx.Opt_Curve] as
UserDefine to customize the inverse-time curve characteristic, and constants K, and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Gx.tmin], then the operating time of the protection changes to the value of setting
[50/51Gx.tmin] automatically.
Define-time or inverse-time directional earth-fault protection drops off instantaneously after fault
current disappears.
50/51Gx.On
50/51Gx.En2
50/51Gx.On_ShortDly
50/51Gx.Blk
50/51Gx.St
50/51Gx.En_ShortDly
50/51Gx.Op
50/51Gx.Blk_ShortDly
Input Signal
50/51Gx.En1
50/51Gx.En2
50/51Gx.Blk
50/51Gx.En_ShortDly
50/51Gx.Blk_ShortDly
No.
Output Signal
Description
Stage x of earth fault protection enabling input 1, it is triggered from binary
input or programmable logic etc. (x=1, 2, 3, 4)
Stage x of earth fault protection enabling input 2, it is triggered from binary
input or programmable logic etc. (x=1, 2, 3, 4)
Stage x of earth fault protection blocking input, it is triggered from binary input
or programmable logic etc. (x=1, 2, 3, 4)
Short time delay for stage x of earth fault protection enabling input, it is
triggered from binary input or programmable logic etc. (x=2, 3, 4)
Short time delay for stage x of earth fault protection blocking input, it is
triggered from binary input or programmable logic etc. (x=2, 3, 4)
Description
3-146
3 Operation Theory
1
50/51Gx.On
50/51Gx.On_ShortDly
Short time delay for stage x of earth fault protection is enabled. (x=2, 3, 4)
50/51Gx.St
50/51Gx.Op
3.14.5 Logic
EN
[50/51G1.En]
SIG
50/51G1.En1
SIG
50/51G1.En2
SIG
50/51G1.Blk
SIG
FD.Pkp
SET
3I0>[50/51G1.3I0_Set]
EN
[50/51G1.En_Abnor_Blk]
SIG
No abnormal conditions
&
&
50/51G1.On
&
>=1
&
SET
[50/51G1.Opt_Dir]=Forward
&
&
&
50/51G1.St
&
SIG
Forward DIR
SET
[50/51G1.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51G1.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51G1.En_CTS_Blk]
SIG
I3P
SET
[50/51G1.En_Hm2_Blk]
SIG
50/51G1.St
>=1
&
>=1
&
>=1
2nd Hm Detect
&
&
Timer
t
>=1
&
50/51G1.Op
[50/51G1.t_Op]
SET
[50/51G1.Opt_Curve]=DefTime
3-147
3 Operation Theory
EN
[50/51Gx.En_ShortDly]
SIG
50/51Gx.En_ShortDly
SIG
50/51Gx.Blk_ShortDly
EN
[50/51Gx.En]
SIG
50/51Gx.En1
SIG
50/51Gx.En2
SIG
50/51Gx.Blk
SIG
FD.Pkp
SET
3I0>[50/51Gx.3I0_Set]
EN
[50/51Gx.En_Abnor_Blk]
SIG
No abnormal conditions
&
50/51Gx.On_ShortDly
&
&
50/51Gx.On
&
>=1
&
SET
[50/51Gx.Opt_Dir]=Forward
&
&
SIG
Forward DIR
SET
[50/51Gx.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Gx.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Gx.En_CTS_Blk]
SIG
I3P
SET
[50/51Gx.En_Hm2_Blk]
SIG
50/51Gx.St
>=1
&
>=1
&
>=1
2nd Hm Detect
&
&
Timer
t
&
SET
&
50/51Gx.St
&
>=1
[50/51Gx.t_Op]
[50/51Gx.t_ShortDly]
50/51Gx.Op
[50/51Gx.Opt_Curve]=DefTime
&
SIG
50/51Gx.On_ShortDly
x=2, 3, 4
3-148
3 Operation Theory
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR, earth
fault protection will operate. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1, the stage x of
earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 0,
earth fault protection is not controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
[50/51Gx.En_Abnor_Blk] is set as 1, the stage x of earth fault protection will be blocked. If the
logic setting [50/51Gx.En_Abnor_Blk] is set as 0, earth fault protection is not controlled by
direction element.
Abnormal condition 3: VT circuit failure. If the logic setting [50/51Gx.En_Abnor_Blk] is set as 1,
the stage x of earth fault protection will be blocked. If the logic setting [50/51Gx.En_Abnor_Blk] is
set as 0, earth fault protection is not controlled by direction element.
3.14.6 Settings
Table 3.14-3 Settings of earth fault protection
No.
Name
Range
Step
Unit
Remark
Setting
50/51G.K_Hm2
0.000~1.000
0.001
of
second
harmonic
50/51G1.3I0_Set
(0.050~30.000)In
0.001
50/51G1.t_Op
0.000~20.000
0.001
50/51G1.En
0 or 1
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 1 of earth
50/51G1.En_BlkAR
0 or 1
Non_Directional
6
50/51G1.Opt_Dir
Forward
Reverse
Enabling/disabling
second
50/51G1.En_Hm2_Blk
0 or 1
50/51G1.En_Abnor_Blk
0 or 1
3-149
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
under abnormal conditions
0: disable
1: enable
Enabling/disabling blocking for
stage 1 of earth fault protection
50/51G1.En_CTS_Blk
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
10
50/51G1.Opt_Curve
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time multiplier setting for stage 1
11
50/51G1.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
12
50/51G1.tmin
0.050~20.000
0.001
13
50/51G1.Alpha
0.010~5.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
Constant C for stage 1 of
14
50/51G1.C
0.000~20.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
Constant K for stage 1 of
15
50/51G1.K
0.050~20.000
customized
0.001
characteristic
inverse-time
earth
fault
protection
16
50/51G2.3I0_Set
(0.050~30.000)In
0.001
17
50/51G2.t_Op
0.000~20.000
0.001
3-150
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
fault protection
18
50/51G2.t_ShortDly
0.000~20.000
0.001
19
50/51G2.En
0 or 1
0: disable
1: enable
Enabling/disabling
short
time
50/51G2.En_ShortDly
0 or 1
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 2 of earth
21
50/51G2.En_BlkAR
0 or 1
Non_Directional
22
50/51G2.Opt_Dir
Forward
Reverse
Enabling/disabling
second
50/51G2.En_Hm2_Blk
0 or 1
24
50/51G2.En_Abnor_Blk
0 or 1
25
50/51G2.En_CTS_Blk
0 or 1
DefTime
IECN
IECV
26
50/51G2.Opt_Curve
IECE
IECST
IECLT
ANSIE
ANSIV
3-151
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2
27
50/51G2.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
28
50/51G2.tmin
0.050~20.000
0.001
29
50/51G3.3I0_Set
(0.050~30.000)In
0.001
30
50/51G3.t_Op
0.000~20.000
0.001
31
50/51G3.t_ShortDly
0.000~20.000
0.001
32
50/51G3.En
0 or 1
0: disable
1: enable
Enabling/disabling
short
time
50/51G3.En_ShortDly
0 or 1
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked when stage 3 of earth
34
50/51G3.En_BlkAR
0 or 1
Non_Directional
35
50/51G3.Opt_Dir
Forward
Reverse
Enabling/disabling
second
50/51G3.En_Hm2_Blk
0 or 1
37
50/51G3.En_Abnor_Blk
0 or 1
3-152
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
1: enable
Enabling/disabling blocking for
stage 3 of earth fault protection
38
50/51G3.En_CTS_Blk
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
39
50/51G3.Opt_Curve
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
50/51G3.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
41
50/51G3.tmin
0.050~20.000
0.001
42
50/51G4.3I0_Set
(0.050~30.000)In
0.001
43
50/51G4.t_Op
0.000~20.000
0.001
44
50/51G4.t_ShortDly
0.000~20.000
0.001
45
50/51G4.En
0 or 1
0: disable
1: enable
Enabling/disabling
short
time
50/51G4.En_ShortDly
0 or 1
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
47
50/51G4.En_BlkAR
0 or 1
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
0: disable
1: enable
Non_Directional
48
50/51G4.Opt_Dir
Forward
Reverse
Enabling/disabling
second
50/51G4.En_Hm2_Blk
0 or 1
50
50/51G4.En_Abnor_Blk
0 or 1
51
50/51G4.En_CTS_Blk
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
52
50/51G4.Opt_Curve
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
50/51G4.TMS
0.010~200.000
0.001
of
inverse-time
earth
fault
protection
Minimum operating time for stage
54
50/51G4.tmin
0.050~20.000
0.001
3-154
3 Operation Theory
2.
Each stage can be selected to block AR by the setting and stage 3 of negative-sequence
overcurrent protection can be selected to operate to trip or alarm.
3.
4.
5.
6.
Each stage can select independent releasing threshold based on the ratio of
negative-sequence current to positive-sequence current to prevent negative-sequence
overcurrent protection from undesired operation for three-phase fault with asymmetrical
position exchange of three-phase.
3.15.2.1 Overview
Negative-sequence overcurrent protection consists of following three elements:
1.
Fault detector: each stage is controlled by the fault detector based on negative-sequence
current. Negative-sequence overcurrent protection can operate when the fault detector based
on negative-sequence current operate and it is enabled.
2.
Overcurrent element: each stage is equipped with one independent overcurrent element.
3.
Directional control element: one direction control element is shared by all overcurrent
elements, and each overcurrent element can individually select protection direction.
4.
Ratio element: each stage is equipped with one independent ratio element (I2/I1), usually the
same setting is applied for all stages.
3-155
3 Operation Theory
Equation 3.15-1
I2/I1>[50/51Qx.I2/I1_Set]
Where:
I2 is the calculated negative-sequence current.
I1 is the calculaged positive-sequence current.
[50/51Qx.I2_Set] is the current setting of stage x (x=1, 2, 3 or 4) of negative-sequence overcurrent
protection.
3.15.2.3 Direction Control Element
Please refer to section 3.10 for details.
3.15.2.4 Characteristic Curve
All 4 stages negative-sequence overcurrent protection can be selected as definite-time or
inverse-time characteristic, and inverse-time operating time curve is as follows.
Equation 3.15-2
Where:
Iset is negative-sequence curren setting [50/51Qx.I2_Set].
Tp is time multiplier setting [50/51Qx.TMS].
K is a constant
C is a constant.
is a constant.
I2 is the calculated negative-sequence current.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50/51Qx.Opt_Curve], and parameters of available characteristics for selection are shown
in the following table.
Table 3.15-1 Inverse-time curve parameters
50/51Gx.Opt_Curve
DefTime
Time Characteristic
Definite time
3-156
3 Operation Theory
50/51Gx.Opt_Curve
Time Characteristic
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
UserDefine
Programmable User-defined
If all available curves do not comply with user application, user may set [50/51Qx.Opt_Curve] as
UserDefine to customize the inverse-time curve characteristic, and constants K, and C with
configuration tool software. (only stage 1)
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50/51Qx.tmin], then the operating time of the protection changes to the value of setting
[50/51Qx.tmin] automatically.
Define-time or inverse-time directional negative-sequence overcurrent protection drops off
instantaneously after fault current disappears.
50/51Qx.On
50/51Gx.En2
50/51Qx.St
50/51Qx.Blk
50/51Qx.Op
50/51Q4.Alm
Input Signal
50/51Qx.En1
50/51Qx.En2
Description
Stage x of negative-sequence overcurrent protection enabling input 1, it is
triggered from binary input or programmable logic etc. (x=1, 2, 3, 4)
Stage x of negative-sequence overcurrent protection enabling input 2, it is
triggered from binary input or programmable logic etc. (x=1, 2, 3, 4)
3-157
3 Operation Theory
3
No.
50/51Qx.Blk
Output Signal
Description
50/51Qx.On
50/51Qx.St
50/51Qx.Op
50/51Q4.Alm
3.15.5 Logic
EN
[50/51Qx.En]
SIG
50/51Qx.En1
SIG
50/51Qx.En2
SIG
50/51Qx.Blk
SET
I2/I1>[50/51Qx.I2/I1_Set]
SET
I2>[50/51Qx.I2_Set]
EN
[50/51Qx.En_Abnor_Blk]
SIG
No abnormal conditions
&
&
50/51Qx.On
&
>=1
&
&
&
50/51Qx.St
Timer
t
&
50/51Qx.Op
SET
[50/51Qx.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Qx.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Qx.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Qx.En_CTS_Blk]
SIG
FD.NOC.Pkp
&
>=1
&
>=1
&
x=1, 2 or 3
Abnormal condition 1: when the system is under pole disagreement condition, for 1-pole AR,
negative-sequence overcurrent protection will operate. If the logic setting [50/51Qx.En_Abnor_Blk]
is set as 1, the stage x of negative-sequence overcurrent protection will be blocked. If the logic
setting [50/51Qx.En_Abnor_Blk] is set as 0, negative-sequence overcurrent protection is not
controlled by direction element.
Abnormal condition 2: When manually closing circuit breaker, three phases of the circuit breaker
maybe not operate simultaneously, and SOTF protection should operate. If the logic setting
3-158
3 Operation Theory
[50/51Q4.En]
SIG
50/51Q4.En1
SIG
50/51Q4.En2
SIG
50/51Q4.Blk
SET
I2/I1>[50/51Q4.I2/I1_Set]
SET
I2>[50/51Q4.I2_Set]
EN
[50/51Q4.En_Abnor_Blk]
SIG
No abnormal conditions
&
&
50/51Q4.On
&
>=1
&
&
&
50/51Q4.St
&
SET
[50/51Q4.Opt_Dir]=Forward
SIG
Forward DIR
SET
[50/51Q4.Opt_Dir]=Reverse
SIG
Reverse DIR
SET
[50/51Q4.Opt_Dir]=Non_Directional
SIG
CTS.Alm
EN
[50/51Q4.En_CTS_Blk]
SIG
FD.NOC.Pkp
EN
[50/51Q4.En_Trp]
&
>=1
&
>=1
Timer
t
&
50/51Q4.Alm
&
Timer
t
&
50/51Q4.Op
3.15.6 Settings
Table 3.15-3 Settings of negative-sequence overcurrent protection
No.
Name
Range
Step
Unit
Remark
Current setting for stage 1 of
50/51Q1.I2_Set
(0.050~30.000)In
0.001
negative-sequence
overcurrent
protection
2
50/51Q1.I2/I1_Set
0.00~1.00
0.01
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
protection
Time
50/51Q1.t_Op
0.000~20.000
0.001
delay
for
stage
negative-sequence
of
overcurrent
protection
Enabling/disabling
stage 1
negative-sequence
4
50/51Q1.En
0 or 1
of
overcurrent
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked
50/51Q1.En_BlkAR
when
stage
negative-sequence
0 or 1
of
overcurrent
protection operates
0: disable
1: enable
50/51Q1.Opt_Dir
Non_Directional
Forward
negative-sequence
Reverse
protection
Enabling/disabling
overcurrent
blocking
for
stage 1 of negative-sequence
7
50/51Q1.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions
0: disable
1: enable
Enabling/disabling
blocking
for
stage 1 of negative-sequence
8
50/51Q1.En_CTS_Blk
0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
9
50/51Q1.Opt_Curve
IECLT
ANSIE
stage 1 of negative-sequence
ANSIV
overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
3-160
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
UserDefine
Time multiplier setting for stage 1
10
50/51Q1.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection
Minimum operating time for stage
11
50/51Q1.tmin
0.050~20.000
0.001
of
inverse-time
negative-sequence
overcurrent
protection
Constant for stage 1 of
12
50/51Q1.Alpha
0.010~5.000
customized
0.001
inverse-time
characteristic negative-sequence
overcurrent protection
Constant C for stage 1 of
13
50/51Q1.C
0.000~20.000
customized
0.001
inverse-time
characteristic negative-sequence
overcurrent protection
Constant K for stage 1 of
14
50/51Q1.K
0.050~20.000
customized
0.001
inverse-time
characteristic negative-sequence
overcurrent protection
Current setting for stage 2 of
15
50/51Q2.I2_Set
(0.050~30.000)In
0.001
negative-sequence
overcurrent
protection
Ratio coefficient (I2/I1) for stage 2
16
50/51Q2.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent
protection
Time
17
50/51Q2.t_Op
0.000~20.000
0.001
delay
for
stage
negative-sequence
of
overcurrent
protection
Enabling/disabling
stage 2
negative-sequence
18
50/51Q2.En
0 or 1
of
overcurrent
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked
19
50/51Q2.En_BlkAR
when
stage
negative-sequence
0 or 1
of
overcurrent
protection operates
0: disable
1: enable
20
50/51Q2.Opt_Dir
Non_Directional
Forward
negative-sequence
overcurrent
3-161
3 Operation Theory
No.
Name
Range
Step
Unit
Reverse
Remark
protection
Enabling/disabling
blocking
for
stage 2 of negative-sequence
21
50/51Q2.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions
0: disable
1: enable
Enabling/disabling
blocking
for
stage 2 of negative-sequence
22
50/51Q2.En_CTS_Blk
0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
23
50/51Q2.Opt_Curve
IECLT
ANSIE
stage 2 of negative-sequence
ANSIV
overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 2
24
50/51Q2.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection
Minimum operating time for stage
25
50/51Q2.tmin
0.050~20.000
0.001
of
inverse-time
negative-sequence
overcurrent
protection
Current setting for stage 3 of
26
50/51Q3.I2_Set
(0.050~30.000)In
0.001
negative-sequence
overcurrent
protection
Ratio coefficient (I2/I1) for stage 3
27
50/51Q3.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent
protection
Time
28
50/51Q3.t_Op
0.000~20.000
0.001
delay
for
negative-sequence
stage
of
overcurrent
protection
3-162
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
stage 3
negative-sequence
29
50/51Q3.En
0 or 1
of
overcurrent
protection
0: disable
1: enable
Enabling/Disabling auto-reclosing
blocked
30
50/51Q3.En_BlkAR
when
stage
negative-sequence
0 or 1
of
overcurrent
protection operates
0: disable
1: enable
31
50/51Q3.Opt_Dir
Non_Directional
Forward
negative-sequence
Reverse
protection
Enabling/disabling
overcurrent
blocking
for
stage 3 of negative-sequence
32
50/51Q3.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions
0: disable
1: enable
Enabling/disabling
blocking
for
stage 3 of negative-sequence
33
50/51Q3.En_CTS_Blk
0 or 1
failure conditions
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
34
50/51Q3.Opt_Curve
IECLT
ANSIE
stage 3 of negative-sequence
ANSIV
overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 3
35
50/51Q3.TMS
0.010~200.000
0.001
of
negative-sequence
inverse-time
overcurrent
protection
3-163
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Minimum operating time for stage
36
50/51Q3.tmin
0.050~20.000
0.001
of
inverse-time
negative-sequence
overcurrent
protection
Current setting for stage 4 of
37
50/51Q4.I2_Set
(0.050~30.000)In
0.001
negative-sequence
overcurrent
protection
Ratio coefficient (I2/I1) for stage 4
38
50/51Q4.I2/I1_Set
0.00~1.00
0.01
of negative-sequence overcurrent
protection
Time
39
50/51Q4.t_Op
0.000~20.000
0.001
delay
for
stage
negative-sequence
of
overcurrent
protection
Enabling/disabling
stage 4
negative-sequence
40
50/51Q4.En
0 or 1
of
overcurrent
protection
0: disable
1: enable
Enabling/Disabling stage 4 of
negative-sequence
41
50/51Q4.En_Trp
0 or 1
overcurrent
42
50/51Q4.En_BlkAR
when
stage
negative-sequence
0 or 1
of
overcurrent
protection operates
0: disable
1: enable
43
50/51Q4.Opt_Dir
Non_Directional
Forward
negative-sequence
Reverse
protection
Enabling/disabling
overcurrent
blocking
for
stage 4 of negative-sequence
44
50/51Q4.En_Abnor_Blk
overcurrent
0 or 1
protection
under
abnormal conditions
0: disable
1: enable
Enabling/disabling
blocking
for
stage 4 of negative-sequence
45
50/51Q4.En_CTS_Blk
0 or 1
3-164
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
1: enable
DefTime
IECN
IECV
IECE
IECST
46
50/51Q4.Opt_Curve
IECLT
ANSIE
stage 4 of negative-sequence
ANSIV
overcurrent protection
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage 4
47
50/51Q4.TMS
0.010~200.000
of
0.001
inverse-time
negative-sequence
overcurrent
protection
Minimum operating time for stage
48
50/51Q4.tmin
0.050~20.000
0.001
of
inverse-time
negative-sequence
overcurrent
protection
Equation 3.16-1
3-165
3 Operation Theory
Where:
Iset is current setting [50PVT.I_Set] or [50GVT.3I0_Set].
Tp is time multiplier setting [50PVT.TMS] or [50GVT.TMS].
is a constant.
K is a constant.
C is a constant.
I is measured phase current from line CT
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [50PVT.Opt_Curve] and [50GVT.Opt_Curve], and parameters of available characteristics
for selection are shown in the following table.
Table 3.16-1 Inverse-time curve parameters
[50PVT.Opt_Curve]/[50GVT.Opt_Curve]
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may set [50PVT.Opt_Curve] and
[50GVT.Opt_Curve] as UserDefine to customize the inverse-time curve characteristic with
constants , K and C.
When inverse-time characteristic is selected, if calculated operating time is less than setting
[50PVT.tmin] or [50GVT.tmin], then the operating time of the protection changes to the value of
setting [50PVT.tmin] or [50GVT.tmin] automatically.
3-166
3 Operation Theory
50PVT.On
50PVT.En2
50PVT.Op
50PVT.Blk
50PVT.St
50GVT.En1
50PVT.StA
50GVT.En2
50PVT.StB
50GVT.Blk
50PVT.StC
50GVT.On
50GVT.Op
50GVT.St
Input Signal
50PVT.En1
50PVT.En2
50PVT.Blk
50GVT.En1
50GVT.En2
50GVT.Blk
No.
Description
Phase overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Phase overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 1, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure enabling input 2, it is triggered
from binary input or programmable logic etc.
Ground overcurrent protection for VT circuit failure blocking input, it is triggered
from binary input or programmable logic etc.
Output Signal
Description
50PVT.On
50PVT.Op
50PVT.St
50PVT.StA
50PVT.StB
50PVT.StC
50GVT.On
50GVT.Op
50GVT.St
3-167
3 Operation Theory
3.16.5 Logic
SIG
50PVT.En1
SIG
50PVT.En2
EN
[50PVT.En]
SIG
50PVT.Blk
&
&
50PVT.On
&
>=1
[50PVT.t_Op]
&
SIG
FD.Pkp
SIG
VTS.Alm
SET
Ia>[50PVT.I_Set]
0ms
50PVT.Op
50PVT.St
&
50PVT.StA
&
50PVT.StB
SET
Ib>[50PVT.I_Set]
&
50PVT.StC
SET
Ic>[50PVT.I_Set]
&
Timer
t
>=1
&
50PVT.Op
[50PVT.t_Op]
SET
[50PVT.Opt_Curve]=DefTime
SIG
50GVT.En1
SIG
50GVT.En2
EN
[50GVT.En]
SIG
50GVT.Blk
SIG
FD.Pkp
SET
3I0>[50GVT.3I0_Set]
SIG
FD.ROC.Pkp
SIG
VTS.Alm
&
&
50GVT.On
&
&
50GVT.St
&
&
Timer
t
>=1
&
50GVT.Op
[50GVT.t_Op]
SET
[50GVT.Opt_Curve]=DefTime
3-168
3 Operation Theory
3.16.6 Settings
Table 3.16-3 Settings of overcurrent protection for VT circuit failure
No.
1
Name
50PVT.I_Set
Range
Step
Unit
(0.050~30.000)In
0.001
Remark
Current setting of phase overcurrent
protection when VT circuit failure
Ttime delay of definite-time phase
50PVT.t_Op
0.000~10.000
0.001
phase
50PVT.En
0 or 1
circuit failure
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
4
50PVT.Opt_Curve
ANSIE
inverse-time
ANSIV
phase
overcurrent
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time
5
50PVT.TMS
0.010~200.000
0.001
multiplier
inverse-time
setting
phase
for
overcurrent
50PVT.tmin
0.000~20.000
0.001
operating
inverse-time
phase
time
for
overcurrent
50PVT.Alpha
0.010~5.000
0.001
for
customized
50PVT.C
0.000~20.000
0.001
for
customized
50PVT.K
0.050~20.000
0.001
Constant
for
customized
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
overcurrent protection when VT
circuit failure
Current
10
50GVT.3I0_Set
(0.050~30.000)In
0.001
setting
of
ground
11
50GVT.t_Op
0.000~10.000
0.001
ground
50GVT.En
0 or 1
circuit failure
0: disable
1: enable
DefTime
IECN
IECV
IECE
IECST
IECLT
13
50GVT.Opt_Curve
ANSIE
inverse-time
ANSIV
ground
overcurrent
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Time
14
50GVT.TMS
0.010~200.000
0.001
multiplier
inverse-time
setting
ground
for
overcurrent
50GVT.tmin
0.000~20.000
0.001
operating
inverse-time
ground
time
for
overcurrent
50GVT.Alpha
0.010~5.000
0.001
for
customized
17
50GVT.C
0.000~20.000
0.001
for
customized
18
50GVT.K
0.050~20.000
0.001
3-170
Constant
for
customized
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
overcurrent protection when VT
circuit failure
50PSOTF.On
50PSOTF.En2
50PSOTF.Op
50PSOTF.Blk
50PSOTF.St
Input Signal
50PSOTF.En1
50PSOTF.En2
50PSOTF.Blk
No.
Description
Phase current SOTF protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Phase current SOTF protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Phase current SOTF protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
50PSOTF.On
50PSOTF.Op
3-171
3 Operation Theory
3
50PSOTF.St
3.17.5 Logic
SIG 3-pole reclosing signal
>=1
>=1
SET Ib>[50PSOTF.I_Set]
SET Ic>[50PSOTF.I_Set]
SET Ua<[50PSOTF.Up_Set]
>=1
SET Ub<[50PSOTF.Up_Set]
&
SET Uc<[50PSOTF.Up_Set]
EN
[50PSOTF.En_Up_UV]
SET Uab<[50PSOTF.Upp_Set]
>=1
>=1
SET Ubc<[50PSOTF.Upp_Set]
&
&
>=1
>=1
SET Uca<[50PSOTF.Upp_Set]
EN
[50PSOTF.En_Upp_UV]
SET U2>[50PSOTF.U2_Set]
EN
&
[50PSOTF.En_U2_OV]
SET U2>[50PSOTF.3U0_Set]
EN
&
&
[50PSOTF.En_3U0_OV]
>=1
>=1
EN
[50PSOTF.En_Up_UV]
EN
[50PSOTF.En_Upp_UV]
50PSOTF.St
&
[50PSOTF.t_Op]
SIG FD.Pkp
SIG 50PSOTF.En1
0ms
50PSOTF.Op
&
SIG 50PSOTF.En2
&
SIG 50PSOTF.Blk
EN
50PSOTF.On
[50PSOTF.En]
3.17.6 Settings
Table 3.17-2 Settings of phase current SOTF protection
No.
Name
Range
Step
Unit
50PSOTF.I_Set
(0.050~30.000)In
0.001
50PSOTF.t_Op
0.000~10.000
0.001
3-172
Remark
Current setting of phase current
SOTF protection
Time delay for phase current
SOTF protection
PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
50PSOTF.Up_Set
(0~1) Un
0.001
50PSOTF.Upp_Set
(0~1) Un
0.001
Remark
Voltage
setting
50PSOTF.U2_Set
(0~1) Un
0.001
phase
for
setting
for
negative-sequence overvoltage
supervision logic
Voltage
50PSOTF.3U0_Set
(0~1) Un
0.001
setting
zero-sequence
for
overvoltage
supervision logic
Enabling/disabling
7
50PSOTF.En
phase
0 or 1
0: disable
1: enable
Enabling/disabling
phase
50PSOTF.En_Up_UV
for
0 or 1
phase
current
SOTF
protection
0: disable
1: enable
Enabling/disabling phase-phase
undervoltage supervision logic
50PSOTF.En_Upp_UV
for
0 or 1
phase
current
SOTF
protection
0: disable
1: enable
Enabling/disabling
negative-sequence overvoltage
10
50PSOTF.En_U2_OV
supervision
0 or 1
logic
for
phase
11
50PSOTF.En_3U0_OV
0 or 1
zero-sequence
overvoltage
supervision
for
logic
phase
3 Operation Theory
existing fault. This is especially critical if the line in the remote station is grounded, since earth fault
protection would not clear the fault until their time delays had elapsed. In this situation, however,
the fastest possible clearance is desired.
Residual current SOTF (switch onto fault) protection is a complementary function to earth fault
protection. With residual current SOTF protection, a fast trip is achieved for a fault on the line,
when the line is being energized. It shall be responsive to all types of earth faults anywhere within
the protected line, and it shall be enabled for the setting [SOTF.t_En] when the circuit is energized
either manually or via an auto-reclosing system.
50GSOTF.On
50GSOTF.En2
50GSOTF.Op
50GSOTF.Blk
50GSOTF.St
Input Signal
50GSOTF.En1
50GSOTF.En2
50GSOTF.Blk
No.
Output Signal
Description
Residual current SOTF protection enabling input 1, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection enabling input 2, it is triggered from binary input
or programmable logic etc.
Residual current SOTF protection blocking input, it is triggered from binary input
or programmable logic etc.
Description
50GSOTF.On
50GSOTF.Op
50GSOTF.St
3-174
3 Operation Theory
3.18.5 Logic
EN
[50GSOTF.En_Hm2_Blk]
SIG
3-pole AR signal
SIG
SET
3I0>[50GSOTF.3I0_Set]
>=1
&
FD.ROC.Pkp
SIG
1-pole AR signal
SIG
50GSOTF.En1
50GSOTF.En2
SIG
50GSOTF.Blk
EN
[50GSOTF.En]
0ms
&
>=1
50GSOTF.Op
&
SIG
SIG
[50GSOTF.t_Op_3P]
[50GSOTF.t_Op_1P]
0ms
>=1
50GSOTF.St
&
&
50GSOTF.On
3.18.6 Settings
Table 3.18-2 Settings of residual current SOTF protection
No.
1
Name
50GSOTF.3I0_Set
Range
Step
Unit
(0.050~30.000)In
0.001
Remark
Current
setting
of
residual
50GSOTF.t_Op_3P
0.000~10.000
0.001
50GSOTF.t_Op_1P
0.000~10.000
0.001
50GSOTF.En
residual
0 or 1
0: disable
1: enable
Enabling/disabling
current
50GSOTF.En_Hm2_Blk
0 or 1
SOTF
residual
protection
blocked by harmonic
0: disable
1: enable
3 Operation Theory
Three stages phase overvoltage protection with independent logic, voltage and time delay
settings.
2.
3.
4.
1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[59Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [59Px.Opt_Up/Upp] is
set to 1, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is greater than any enabled stage voltage setting,
the stage protection picks up and operates after delay, which will drop off instantaneously when
fault voltage disappears.
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]
Equation 3.19-1
or
Ua>[59Px.U_Set] & Ub>[59Px.U_Set] & Uc>[59Px.U_Set]
3-176
Equation 3.19-2
3 Operation Theory
Where:
U_max is the maximum value among three phase-voltage.
Ua, Ub, Uc are three phase voltages.
[59Px.U_Set] is the setting of stage x (x=1, 2, 3) overvoltage protection.
When [59Px.Opt_1P/3P] is set as 1, 1-out-of-3 logic (Equation 3.19-1) is selected as operation
criterion, and when set as 0, 3-out-of-3 logic (Equation 3.19-2) is selected.
Two operation criteria of definite-time overvoltage protection are shown as follows, which of them
is applied depending on the logic setting [59Px.Opt_1P/3P].
U_max>[ 59Px.U_Set]
Equation 3.19-3
or
Uab>[59Px.U_Set] & Ubc>[59Px.U_Set] & Uca>[59Px.U_Set]
Equation 3.19-4
Characteristic Curve
Equation 3.19-5
Where:
Uset is the voltage setting [59Px.U_Set] (x=1, 2, 3).
Tp is time multiplier setting [59Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
Operating characteristic of overvoltage protection, can be chosen from definite-time characteristic
and 12 inverse-time characteristics by setting the logic setting [59Px.Opt_Curve]. The parameters
of each characteristic are listed in the following table.
3-177
3 Operation Theory
Table 3.19-1 Inverse-time curve parameters
59Px.Opt_Curve
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[59Px.tmin], then the operating time changes to the value of setting [59Px.tmin] automatically.
Define-time or inverse-time phase overvoltage protection drops off instantaneously when
measured voltage is lower than reset voltage.
3.19.1.3 Function Block Diagram
59Px
59Px.En1
59Px.On
59Px.En2
59Px.St
59Px.Blk
59Px.St1
59Px.St2
59Px.St3
59Px.Op
59Px.Alm
59Px.Op_InitTT
Input Signal
59Px.En1
59Px.En2
Description
Stage x of overvoltage protection enabling input 1, it is triggered from binary input
or programmable logic etc. (x=1, 2, 3)
Stage x of overvoltage protection enabling input 2, it is triggered from binary input
3-178
3 Operation Theory
or programmable logic etc. (x=1, 2, 3)
3
59Px.Blk
No.
Output Signal
Description
59Px.On
59Px.Op
59Px.St
59Px.St1
59Px.St2
59Px.St3
59Px.Op_InitTT
59Px.Alm
3.19.1.5 Logic
EN
[59Px.En]
SIG
59Px.En1
SIG
59Px.En2
SIG
59Px.Blk
BI
[52b_PhA]
BI
[52b_PhB]
BI
[52b_PhC]
EN
[59Px.En_52b_TT]
EN
[59Px.En_TT]
EN
[59Px.En_Alm]
SIG
FD.Pkp
SIG
59Px.On
EN
[59Px.Opt_Up/Upp]
&
&
59Px.On
&
&
&
>=1
59Px.Op_InitTT
&
&
&
&
>=1
SET
Timer
t
t
UA>[59Px.U_Set]
&
&
&
SET
UAB>[59Px.U_Set]
&
&
>=1
SET
Timer
t
&
UB>[59Px.U_Set]
59Px.Op
&
SET
&
UBC>[59Px.U_Set]
>=1
&
&
>=1
SET
UC>[59Px.U_Set]
Timer
t
>=1
&
SET
59Px.Alm
&
>=1
59Px.St
UCA>[59Px.U_Set]
59Px.St1
59Px.St2
EN
[59Px.Opt_1P/3P]
59Px.St3
x=1, 2, 3
3-179
3 Operation Theory
3.19.1.6 Settings
Table 3.19-3 Settings of overvoltage protection
No.
Name
Range
Step
Unit
59Px.U_Set
Un~2Unn
0.001
59Px.t_Op
0.000~30.000
0.001
Remark
Voltage setting for stage x of overvoltage
protection (x=1, 2, 3)
Time delay for stage x of overvoltage
protection (x=1, 2, 3)
Enabling/disabling stage x of overvoltage
59Px.En
protection (x=1, 2, 3)
0 or 1
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
59Px.Opt_1P/3P
mode (x=1, 2, 3)
0 or 1
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option of phase-to-phase voltage or phase
59Px.Opt_Up/Upp
voltage (x=1, 2, 3)
0 or 1
0: phase voltage
1: phase-to-phase voltage
Enabling/disabling stage x of overvoltage
59Px.En_Alm
0 or 1
0: disable
1: enable
Enabling/disabling transfer trip controlled
by CB open position for stage x of
59Px.En_52b_TT
0 or 1
59Px.En_TT
0 or 1
(x=1, 2, 3)
0: disable
1: enable
DefTime
IECN
IECV
IECE
9
59Px.Opt_Curve
IECST
IECLT
ANSIE
ANSIV
ANSI
ANSIM
3-180
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage x of
10
59Px.TMS
0.010~200.000
0.001
11
59Px.tmin
0.050~20.000
0.001
59Q.On
59Q.En2
59Q.Op
59Q.Blk
59Q.St
Input Signal
59Q.En1
59Q.En2
59Q.Blk
No.
Description
Negative-sequence overvoltage protection enabling input 1, it is triggered from
binary input or programmable logic etc.
Negative-sequence overvoltage protection enabling input 2, it is triggered from
binary input or programmable logic etc.
Negative-sequence overvoltage protection blocking input, it is triggered from
binary input or programmable logic etc.
Output Signal
Description
59Q.On
59Q.Op
59Q.St
3-181
3 Operation Theory
3.19.2.4 Logic
SIG
59Q.En1
SIG
59Q.En2
EN
[59Q.En]
SIG
59Q.Blk
&
&
59Q.On
[59Q.t_Op]
&
59Q.Op
59Q.St
SET
U2>[59Q.U_Set]
3.19.2.5 Settings
Table 3.19-5 Settings of negative-sequence overvoltage protection
No.
Name
Range
Step
Unit
59Q.U_Set
0~Un
0.001
59Q.t_Op
0.000~30.000
0.001
Remark
Voltage setting for negative-sequence
overvoltage protection
Time
delay
for
overvoltage protection
Enabling/disabling
59Q.En
negative-sequence
negative-sequence
overvoltage protection
0 or 1
0: disable
1: enable
Three-stage residual overvoltage protection with independent logic, voltage and time delay
settings.
2.
3.
3-182
3 Operation Theory
1. Operation Criterion
3U0> [59Gx.3U0_Set]
Equation 3.19-6
Where:
3U0 is calculated residual voltage.
[59Gx.3U0_Set] is the voltage setting of stage x (x=1, 2 or 3) of residual overvoltage protection.
If residual voltage is greater than the setting of any stage enabled residual overvoltage protection,
the stage residual overvoltage protection will operate after time delay and the stage protection will
drop off instantaneously after fault voltage disappears.
2. Time Curve
Stage 1 of residual overvoltage protection is definite-time characteristic and can perform
instantaneous operation with the corresponding time delay being set as 0. Stage 2 and 3 can be
selected as definite-time or inverse-time characteristic, and inverse-time operating time curve is as
follows.
Equation 3.19-7
Where:
Uset is residual voltage setting [59Gx.3U0_Set].
Tp is time setting [59Gx.TMS].
K and C are constants.
is a constant.
U is actual measured residual voltage.
The user can select the operating characteristic from various inverse-time characteristic curves by
setting [59Gx.Opt_Curve], and parameters of available characteristics for selection are shown in
the following table.
Table 3.19-6 Inverse-time curve parameters of residual overvoltage protection
59Gx.Opt_Curve (x=2 or 3)
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
3-183
3 Operation Theory
59Gx.Opt_Curve (x=2 or 3)
Time Characteristic
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
UserDefine
Programmable user-defined
If all available curves do not comply with user application, user may configure setting
[59Gx.Opt_Curve] to UserDefine to customize the inverse-time curve characteristic, and
constants K, and C.
3.19.3.3 Function Block Diagram
59G
59Gx.En1
59Gx.On
59Gx.En2
59Gx.St
59Gx.Blk
59Gx.Op
59G3.Alm
Signal
59Gx.En1
59Gx.En2
59Gx.Blk
No.
Signal
Description
Stage x of residual overvoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc. (x=1, 2, 3)
Stage x of residual overvoltage protection enabling input 2, it is triggered from binary
input or programmable logic etc. (x=1, 2, 3)
Stage x of overvoltage protection blocking input, it is triggered from binary input or
programmable logic etc. (x=1, 2, 3)
Description
59G x.On
59G x.Op
59Gx.St
59G3.Alm
3-184
3 Operation Theory
3.19.3.5 Logic
EN
[59G1.En]
SIG
59G1.En1
SIG
59G1.En2
SIG
59G1.Blk
SET
3U0>[59G1.3U0_Set]
&
&
59G1.On
&
59G1.St
[59G1.t_Op]
59G1.Op
[59G2.En]
SIG
59G2.En1
SIG
59G2.En2
SIG
59G2.Blk
SET
3U0>[59G2.3U0_Set]
&
&
59G2.On
&
59G2.St
Timer
t
&
>=1
59G2.Op
&
[59G2.t_Op]
SET
[59G2.Opt_Curve]=DefTime
[59G3.En]
SIG
59G3.En1
SIG
59G3.En2
SIG
59G3.Blk
SET
3U0>[59G3.3U0_Set]
&
&
59G3.On
&
59G3.St
&
Timer
t
t
>=1
&
[59G3.t_Op]
SET
[59G3.Opt_Curve]=DefTime
EN
[59G3.En_Trp]
&
59G3.Op
&
59G3.Alm
3-185
3 Operation Theory
3.19.3.6 Settings
Table 3.19-8 Settings of residual overvoltage protection
No.
Name
Range
Step
Unit
59G1.3U0_Set
2.000~200.000
0.001
59G1.t_Op
0.000~3600.000
0.001
Remark
Voltage setting of stage 1 of residual
overvoltage protection.
Time delay of stage 1 of residual
overvoltage protection.
Enabling/disabling stage 1 of residual
59G1.En
overvoltage protection.
0 or 1
0: disable
1: enable
59G2.3U0_Set
2.0000~200.000
0.001
59G2.t_Op
0.000~3600.000
0.001
59G2.tmin
0.000~20.000
0.001
59G2.TMS
0.050~3.200
0.001
59G2.K
0.000~120.000
0.001
inverse-time
characteristic
residual
overvoltage protection
Constant C for stage 2 of customized
9
59G2.C
0.000~20.000
0.001
inverse-time
characteristic
residual
overvoltage protection
Constant for stage 2 of customized
10
59G2.Alpha
0.020~5.000
0.001
inverse-time
characteristic
residual
overvoltage protection
DefTime
IECN
IECV
IECE
IECST
IECLT
11
59G2.Opt_Curve
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
12
59G2.En
0 or 1
3-186
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
overvoltage protection.
0: disable
1: enable
13
59G3.3U0_Set
2.0000~200.000
0.001
14
59G3.t_Op
0.000~3600.000
0.001
15
59G3.tmin
0.000~20.000
0.001
16
59G3.TMS
0.050~3.200
0.001
17
59G3.K
0.000~120.000
0.001
inverse-time
characteristic
residual
overvoltage protection
Constant C for stage 3 of customized
18
59G3.C
0.000~20.000
0.001
inverse-time
characteristic
residual
overvoltage protection
Constant for stage 3 of customized
19
59G3.Alpha
0.020~5.000
0.001
inverse-time
characteristic
residual
overvoltage protection
DefTime
IECN
IECV
IECE
IECST
IECLT
20
59G3.Opt_Curve
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
Enabling/disabling stage 3 of residual
21
59G3.En
overvoltage protection.
0 or 1
0: disable
1: enable
Enabling/disabling stage 3 of residual
22
59G3.En_Trp
0 or 1
0: disable
1: enable
3-187
3 Operation Theory
Three stages phase undervoltage protection with independent logic, voltage and time delay
settings.
2.
3.
4.
1-out-of-3 or 3-out-of-3 logic can be selected for protection criterion. (1-out-of-3 means any
of three phase voltages, 3-out-of-3 means all three phase voltages)
1.
Operation Criterion
Users can select phase voltage or phase-to-phase voltage for the protection calculation. If setting
[27Px.Opt_Up/Upp] is set to 0, phase voltage criterion is selected and if [27Px.Opt_Up/Upp] is
set to 1, phase-to-phase voltage criterion is selected.
When phase voltage or phase-to-phase voltage is less than any enabled stage voltage setting, the
stage protection picks up and operates after delay, which will drop off instantaneously when fault
voltage disappears.
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_1P/3P].
U_min<[ 27Px.U_Set]
Equation 3.19-8
or
Ua<[ 27Px.U_Set] & Ub<[27Px.U_Set] & Uc<[27Px.U_Set]
Equation 3.19-9
Where:
U_min is the minimum value among three phase voltages.
Ua, Ub and Uc are three phase voltages.
[27Px.U_Set] is the setting of stage x (x=1, 2, 3) undervoltage protection.
3-188
3 Operation Theory
Two operation criteria of definite-time undervoltage protection are shown as follows, which of them
is applied depending on the logic setting [27Px.Opt_Up/Upp].
U_min<[ 27Px.U_Set]
Equation 3.19-10
or
Uab<[27Px.U_Set] & Ubc<[27Px.U_Set] & Uca<[27Px.U_Set]
Equation 3.19-11
Where:
U_min is the minimum value among three phase-to-phase voltages.
Uab, Ubc and Uca are three phase-to-phase voltages.
[27Px.U_Set] is the setting of stage x (x =1, 2, 3) undervoltage protection.
When the setting [27Px.Opt_1P/3P] is set as 1, 1-out-of-3 logic (Equation 3.19-10) is selected
as operation criterion, and when it is set as 0, 3-out-of-3 logic (Equation 3.19-11) is selected.
2.
Characteristic Curve
Equation 3.19-12
Where:
Uset is the setting [27Px.U_Set] (x=1, 2, 3).
Tp is time multiplier setting [27Px.TMS].
K is a constant.
C is a constant.
is a constant.
U is the measured voltage
Operating characteristic of undervoltage protection can be chosen from definite-time characteristic
and twelve inverse-time characteristics by setting the logic setting [27Px.Opt_Curve]. The
parameters of each characteristic are listed in the following table.
3-189
3 Operation Theory
Table 3.19-9 Inverse-time curve parameters of phase undervoltage protection
27Px.Opt_Curve
Time Characteristic
DefTime
Definite time
IECN
0.14
0.02
IECV
13.5
1.0
IECE
80.0
2.0
IECST
0.05
0.04
IECLT
120.0
1.0
ANSIE
28.2
2.0
0.1217
ANSIV
19.61
2.0
0.491
ANSI
ANSI Inverse
0.0086
0.02
0.0185
ANSIM
0.0515
0.02
0.114
ANSILTE
64.07
2.0
0.25
ANSILTV
28.55
2.0
0.712
ANSILT
0.086
0.02
0.185
When inverse-time characteristic is selected, if calculated operating time is less than setting
[27Px.tmin], then the operating time changes to the value of setting [27Px.tmin] automatically.
Define-time or inverse-time phase under voltage protection drops off instantaneously when
measured voltage is higher than reset voltage.
3.19.4.3 Function Block Diagram
27Px
27Px.En1
27Px.On
27Px.En2
27Px.Alm
27Px.Blk
27Px.Op
27Px.St
27Px.St1
27Px.St2
27Px.St3
27Px.U_Absent
Input Signal
27Px.En1
27Px.En2
Description
Stage x of undervoltage protection enabling input 1, it is triggered from binary
input or programmable logic etc. (x=1, 2, 3)
Stage x of undervoltage protection enabling input 2, it is triggered from binary
3-190
3 Operation Theory
input or programmable logic etc. (x=1, 2, 3)
3
No.
27Px.Blk
Output Signal
Description
27Px.On
27Px.Op
27Px.Alm
27Px.St
27Px.St1
27Px.St2
27Px.St3
27Px.U_Absent
3.19.4.5 Logic
In order to prevent undervoltage protection from undesired operation, after the device powered on,
if any phase current is greater than 0.06In or circuit breaker is in closed posion, undervoltage
protection will be in service with a time delay of 100ms when the corresponding phase voltage is
greater than 0.1Un. Otherwise, undervoltage protection will be blocked by the signal
27Px.U_Absent
Through settings these logic settings [27Px.En_FD_Ctrl], [27Px.En_Curr_Ctrl] and
[27Px.En_VTS_Blk], undervoltage protection optionally can be controlled by FD element reflecting
current (including DPFC current element and residual current element), current condition and VT
circuit failure
When the setting [27Px.En_FD_Ctrl] is set as 1, undervoltage protection will be blocked if FD
element reflecting current does not operate.
When the setting [27Px.En_Curr_Ctrl] is set as 1, undervoltage protection will be blocked if
current condition (>0.06In) is not met.
When the setting [27Px.En_VTS_Blk] is set as 1, undervoltage protection will be blocked if VT
circuit fails.
If any phase of circuit breaker is open (binary input of normal close contact of breaker is energized)
and the corresponding phase current is smaller than 0.06In, undervoltage protection will be
blocked.
3-191
3 Operation Theory
SIG
VTS.Alm
SIG
VTS.Inst
En
[27Px.En_VTS_Blk]
En
[27Px.En_FD_Ctrl]
SIG
FD.Pkp
SIG
CB Open
SIG
27Px.U_Absent
>=1
&
&
>=1
Block UV
>=1
3-192
3 Operation Theory
EN
[27Px.En]
SIG
27Px.En1
SIG
27Px.En2
SIG
27Px.Blk
SIG
Ia>0.06In
&
&
27Px.On
>=1
UV_PhA_Curr_Rls
SIG
Ib>0.06In
>=1
UV_PhB_Curr_Rls
SIG
Ic>0.06In
>=1
UV_PhC_Curr_Rls
&
>=1
UV_PhAB_Curr_Rls
&
>=1
UV_PhBC_Curr_Rls
&
>=1
UV_PhCA_Curr_Rls
EN
27Px.En_Curr_Ctrl
EN
[27Px.En_Alm]
SET
[27P1.Opt_1P/3P]
SIG
27Px.On
SIG
Block UV
SET
[27Px.Opt_Up/Upp]
&
SIG
UV_PhA_Curr_Rls
SET
UA<[27Px.U_Set]
SIG
UV_PhB_Curr_Rls
SET
UAB<[27Px.U_Set]
&
>=1
Timer
t
&
&
&
&
SIG
SET
UV_PhC_Curr_Rls
&
>=1
&
Timer
t
27Px.Op
UB<[27Px.U_Set]
&
&
SIG
>=1
UV_PhAB_Curr_Rls
27Px.Alm
&
SET
UBC<[27Px.U_Set]
>=1
&
SIG
UV_PhBC_Curr_Rls
SET
UC<[27Px.U_Set]
&
>=1
Timer
t
t
27Px.St1
&
SIG
UV_PhCA_Curr_Rls
SET
UCA<[27Px.U_Set]
27Px.St2
27Px.St3
>=1
27Px.St
3 Operation Theory
x=1, 2, 3
3.19.4.6 Settings
Table 3.19-11 Settings of undervoltage protection
No.
Name
Range
Step
Unit
27Px.U_Set
0~Unn
0.001
27Px.t_Op
0.000~30.000
0.001
Remark
Voltage setting for stage x of undervoltage
protection (x=1, 2, 3)
Time delay for stage x of undervoltage
protection (x=1, 2, 3)
Enabling/disabling stage x of undervoltage
27Px.En
protection (x=1, 2, 3)
0 or 1
0: disable
1: enable
Enabling/disabling stage x of undervoltage
protection controlled by
27Px.En_FD_Ctrl
0 or 1
FD element
27Px.En_Curr_Ctrl
0 or 1
(x=1, 2, 3)
0: disable
1: enable
Enabling/disabling stage x of undervoltage
protection controlled by VT circuit failure
27Px.En_VTS_Blk
0 or 1
(x=1, 2, 3)
0: disable
1: enable
Option of 1-out-of-3 mode or 3-out-of-3
mode
27Px.Opt_1P/3P
0 or 1
for
stage
of
undervoltage
protection (x=1, 2, 3)
0: 3-out-of-3 mode
1: 1-out-of-3 mode
Option
of
voltage
criterion
adopting
27Px.Opt_Up/Upp
0 or 1
27Px.En_Alm
0 or 1
0: disable
1: enable
10
27Px.Opt_Curve
DefTime
3-194
3 Operation Theory
No.
Name
Range
Step
Unit
IECN
Remark
of undervoltage protection (x=1, 2, 3)
IECV
IECE
IECST
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
Time multiplier setting for stage x of
11
27Px.TMS
0.010~200.000
0.001
12
27Px.tmin
0.050~20.000
0.001
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
Equation 3.20-1
3-195
3 Operation Theory
Where:
f is system frequency.
[81O.OFx.f_Set] is the frequency setting of stage x (x=1, 2, 3, or 4) of overfrequency protection.
3.20.1.3 Function Block Diagram
81O.OFx
81O.En1
81O.OFx.On
81O.En2
81O.St
81O.Blk
81O.OFx.Op
Input Signal
81O.En1
81O.En2
81O.Blk
No.
Description
Overfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Overfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Overfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
81O.OFx.On
81O.OFx.Op
81O.St
3.20.1.5 Logic
SIG
81O.En1
SIG
81O.En2
EN
[81O.OF1.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF1.On
&
1
&
50ms
0ms
81O.St1
&
SET
f>[81O.OF1.f_Set]
EN
[81O.OF1.En]
[81O.OF1.t_Op]
&
0ms
81O.OF1.Op
3 Operation Theory
SIG
81O.En1
SIG
81O.En2
EN
[81O.OF2.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF2.On
&
1
&
50ms
0ms
81O.St2
&
SET
f>[81O.OF2.f_Set]
EN
[81O.OF2.En]
[81O.OF2.t_Op]
&
0ms
81O.OF2.Op
81O.En1
SIG
81O.En2
EN
[81O.OF3.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF3.On
&
1
&
50ms
0ms
81O.St3
&
SET
f>[81O.OF3.f_Set]
EN
[81O.OF3.En]
[81O.OF3.t_Op]
&
0ms
81O.OF3.Op
81O.En1
SIG
81O.En2
EN
[81O.OF4.En]
SIG
81O.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f40 or f65
OTH
f>[81O.f_Pkp]
&
&
81O.OF4.On
&
1
&
50ms
0ms
81O.St4
&
SET
f>[81O.OF4.f_Set]
EN
[81O.OF4.En]
[81O.OF4.t_Op]
&
0ms
81O.OF4.Op
3-197
3 Operation Theory
SIG
81O.St1
SIG
81O.St2
SIG
81O.St3
SIG
81O.St4
1
81O.St
3.20.1.6 Settings
Table 3.20-2 Settings of overfrequency protection
No.
Name
Range
Step
Unit
81O.f_Pkp
50.000~65.000 (Hz)
0.001
Hz
81O.OF1.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF1.t_Op
0.050~20.000 (s)
0.001
Remark
Frequency
pickup
81O.OF1.En
for
overfrequency protection
Frequency setting for stage 1 of
overfrequency protection
Time
delay
for
stage
of
of
overfrequency protection
Enabling/disabling
setting
stage
overfrequency protection
0 or 1
0: disable
1: enable
81O.OF2.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF2.t_Op
0.050~20.000 (s)
0.001
delay
for
81O.OF2.En
of
of
overfrequency protection
Enabling/disabling
stage
stage
overfrequency protection
0 or 1
0: disable
1: enable
81O.OF3.f_Set
50.000~65.000 (Hz)
0.001
Hz
81O.OF3.t_Op
0.050~20.000 (s)
0.001
delay
for
81O.OF3.En
of
of
overfrequency protection
Enabling/disabling
10
stage
stage
overfrequency protection
0 or 1
0: disable
1: enable
11
81O.OF4.f_Set
50.000~65.000 (Hz)
0.001
Hz
12
81O.OF4.t_Op
0.050~20.000 (s)
0.001
13
81O.OF4.En
0 or 1
delay
for
Enabling/disabling
3-198
stage
of
of
overfrequency protection
stage
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
overfrequency protection
0: disable
1: enable
If the positive voltage U1<0.15Un, the calculation of protection is not carried out and the output
relay will be blocked.
2.
If df/dt[81U.df/dt_Blk], the calculation of protection is not carried out and the output relay will
be blocked. The blocking element will not be released automatically until the system frequency
recovers to be less than the setting [81U.f_Pkp].
3.
Equation 3.20-2
Where:
f is system frequency.
[81U.UFx.f_Set] is the frequency settings of stage x (x=1, 2, 3 or 4) of underfrequency protection.
The equation of df/dt blocking function is as follows.
df/dt[81U.df/dt_Blk]
Equation 3.20-3
Where:
df/dt is the frequency slip speed and the time step (i.e. dt) for the calucation is equal to 5 cycle.
[81U.df/dt_Blk] is the setting of df/dt blocking underfrequency protection.
3-199
3 Operation Theory
Underfrequency protection can be blocked by the frequency slip speed (df/dt). If the logic setting
[81U.UFx.En_df/dt_Blk] (x=1, 2, 3 or 4) is set as 1, when Equation 3.20-2 and Equation 3.20-3
are met, it is decided that a fault occurred and the corresponding stage underfrequency protection
is blocked at the same time for the purpose of waiting for operation of other related protection. The
blocking signal will not reset until the system frequency recovers, i.e. the system frequency is
greater than the setting [81U.f_Pkp]. If the logic setting is set as 0, when Equation 3.20-2 and
Equation 3.20-3 are met, the stage underfrequency protection will be released to operate.
3.20.2.3 Function Block Diagram
81U.UFx
81U.En1
81U.UFx.On
81U.En2
81U.St
81U.Blk
81U.UFx.Op
Input Signal
81U.En1
81U.En2
81U.Blk
No.
Description
Underfrequency protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Underfrequency protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Underfrequency protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
81U.UFx.On
81U.UFx.Op
81U.St
3-200
3 Operation Theory
3.20.2.5 Logic
SIG
81U.En1
SIG
81U.En2
EN
[81U.UF1.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF1.On
&
&
1
0ms
81U.St1
&
[81U.UF1.t_Op]
EN
81U.UF1.En_df/dt_Blk
SET
f<[81U.UF1.f_Set]
EN
[81U.UF1.En]
0ms
81U.UF1.Op
&
81U.En1
SIG
81U.En2
EN
[81U.UF2.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF2.On
&
&
1
0ms
81U.St2
&
[81U.UF2.t_Op]
EN
81U.UF2.En_df/dt_Blk
SET
f<[81U.UF2.f_Set]
EN
[81U.UF2.En]
0ms
81U.UF2.Op
&
3-201
3 Operation Theory
SIG
81U.En1
SIG
81U.En2
EN
[81U.UF3.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF3.On
&
&
1
0ms
81U.St3
&
[81U.UF3.t_Op]
EN
81U.UF3.En_df/dt_Blk
SET
f<[81U.UF3.f_Set]
EN
[81U.UF3.En]
0ms
81U.UF3.Op
&
81U.En1
SIG
81U.En2
EN
[81U.UF4.En]
SIG
81U.Blk
SIG
FD.Pkp
OTH
U1<0.15Un
SIG
f<40 or f>65
OTH
f<[81U.f_Pkp]
50ms
SET
-df/dt>[81U.df/dt_Blk]
>=1
&
&
81U.UF4.On
&
&
1
0ms
81U.St4
&
[81U.UF4.t_Op]
EN
81U.UF4.En_df/dt_Blk
SET
f<[81U.UF4.f_Set]
EN
[81U.UF4.En]
0ms
81U.UF4.Op
&
3-202
3 Operation Theory
SIG
81U.St1
SIG
81U.St2
SIG
81U.St3
SIG
81U.St4
>=1
>=1
81U.St
>=1
3.20.2.6 Settings
Table 3.20-4 Settings of underfrequency protection
No.
Name
Range
Step
Unit
81U.f_Pkp
45.000~60.000
0.01
Hz
81U.df/dt_Blk
0.200~20.000
0.01
Hz/s
81U.UF1.f_Set
45.000~60.000
0.001
Hz
81U.UF1.t_Op
0.050~30.000
0.01
Remark
Frequency
pickup
81U.UF1.En
for
underfrequency protection
Rate
of
frequency
change
for
delay
for
stage
of
of
underfrequency protection
Enabling/disabling
setting
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
81U.UF1.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
81U.UF2.f_Set
45.000~60.000
0.001
Hz
81U.UF2.t_Op
0.050~30.000
0.01
delay
for
81U.UF2.En
of
of
underfrequency protection
Enabling/disabling
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
10
81U.UF2.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
11
81U.UF3.f_Set
45.000~60.000
0.001
Hz
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
underfrequency protection
12
81U.UF3.t_Op
0.050~30.000
0.01
Time
delay
for
81U.UF3.En
of
of
underfrequency protection
Enabling/disabling
13
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
14
81U.UF3.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
15
81U.UF4.f_Set
45.000~60.000
0.001
Hz
16
81U.UF4.t_Op
0.050~30.000
0.01
delay
for
81U.UF4.En
of
of
underfrequency protection
Enabling/disabling
17
stage
stage
underfrequency protection
0 or 1
0: disable
1: enable
Enabling/disabling rate of frequency
change
18
81U.UF4.En_df/dt_Blk
0 or 1
to
block
stage
of
underfrequency protection
0: disable
1: enable
3-204
3 Operation Theory
protection for CB1 and CB2 respectively. Both breaker failure protections have the
same logic.The difference is that the prefix CBx. is added to all signals and settings for
circuit breaker No.x (x=1 or 2).
3-205
3 Operation Theory
CBx.50BF.On
CBx.50BF.ExTrp3P_GT
CBx.50BF.Op_ReTrpA
CBx.50BF.ExTrp_WOI
CBx.50BF.Op_ReTrpB
CBx.50BF.ExTrpA
CBx.50BF.Op_ReTrpC
CBx.50BF.ExTrpB
CBx.50BF.Op_ReTrp3P
CBx.50BF.ExTrpC
CBx.50BF.Op_t1
CBx.50BF.En
CBx.50BF.Op_t2
CBx.50BF.Blk
Input Signal
Description
CBx.50BF.ExTrp3P_L
CBx.50BF.ExTrp3P_GT
CBx.50BF.ExTrpA
CBx.50BF.ExTrpB
CBx.50BF.ExTrpC
CBx.50BF.ExTrp_WOI
CBx.50BF.En
CBx.50BF.Blk
input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
No.
Output Signal
Description
CBx.50BF.On
CBx.50BF.Op_ReTrpA
CBx.50BF.Op_ReTrpB
CBx.50BF.Op_ReTrpC
CBx.50BF.Op_ReTrp3P
CBx.50BF.Op_t1
CBx.50BF.Op_t2
3-206
3 Operation Theory
3.21.5 Logic
SIG
CBx.50BF.En
EN
[CBx.50BF.En]
SIG
CBx.50BF.Blk
SIG
CBx.50BF.On
SIG
FD.Pkp
EN
[CBx.50BF.En_ReTrp]
EN
[CBx.50BF.En_3I0_1P]
SET
3I0>[CBx.50BF.3I0_Set]
SIG
CBx.BFI_A
BI
[CBx.50BF.ExTrpA]
SET
IA>[CBx.50BF.I_Set]
SIG
CBx.BFI_B
BI
[CBx.50BF.ExTrpB]
SET
IB>[CBx.50BF.I_Set]
SIG
CBx.BFI_C
&
CBx.50BF.On
&
>=1
&
>=1
&
>=1
&
>=1
&
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpA
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpB
[CBx.50BF.t_ReTrp] 0ms
CBx.50BF.Op_ReTrpC
&
&
BI
[CBx.50BF.ExTrpC]
SET
IC>[CBx.50BF.I_Set]
SIG
CBx.BFI_3P
BI
>=1
>=1
>=1
&
&
[CBx.50BF.ExTrp3P_L]
>=1
[CBx.50BF.t_ReTrp] 0ms
>=1
BI
[CBx.50BF.ExTrp3P_GT]
BI
[CBx.50BF.ExTrp_WOI]
EN
[CBx.50BF.En_3I0_3P]
SET
3I0>[CBx.50BF.3I0_Set]
EN
[CBx.50BF.En_I2_3P]
SET
I2>[CBx.50BF.I2_Set]
EN
[CBx.50BF.En_CB_Ctrl]
BI
[CBx.52b_PhA]
BI
[CBx.52b_PhB]
BI
[CBx.52b_PhC]
SIG
CBx.50BF.On
SIG
FD.Pkp
>=1
[CBx.50BF.Op_ReTrp3P]
&
&
&
&
&
>=1
>=1
[CBx.50BF.t1_Op]
0ms
CBx.50BF.Op_t1
[CBx.50BF.t2_Op]
0ms
CBx.50BF.Op_t2
&
&
&
&
3-207
3 Operation Theory
3.21.6 Settings
Table 3.21-2 Settings of breaker failure protection
No.
Name
Range
Step
Unit
Remark
Current setting of phase current
criterion for BFP
CBx.50BF.I_Set
(0.050~30.000 )In
0.001
CBx.50BF.3I0_Set
(0.050~30.000 )In
0.001
CBx.50BF.I2_Set
(0.050~30.000 )In
0.001
CBx.50BF.t_ReTrp
0.000~10.000
0.001
CBx.50BF.t1_Op
0.000~10.000
0.001
CBx.50BF.t2_Op
0.000~10.000
0.001
CBx.50BF.En
0 or 1
CBx.50BF.En_ReTrp
0 or 1
CBx.50BF.En_3I0_1P
0 or 1
10
CBx.50BF.En_3I0_3P
0 or 1
11
CBx.50BF.En_I2_3P
0 or 1
12
CBx.50BF.En_CB_Ctrl
0 or 1
3-208
3 Operation Theory
Two stages for alarm purpose and two stages for trip purpose
The device provides a thermal overload model which is based on the IEC60255-8 standard. The
thermal overload formulas are shown as below.
1.
2.
Where:
T = Time to operate (in seconds)
3 Operation Theory
ln = Natural logarithm
The characteristic curve of thermal overload model is shown in Figure 3.22-1.
Refer to IEC60255-8
Ip
P=
IB
P = 0.0
P = 0.6
P = 0.8
P = 0.9
kIB
The hot start characteristic is adopted in the device. The calculation is carried out at zero of Ip, so
users need not to set the value of Ip.
Tripping outputs of the protection is controlled by current, even if the thermal accumulation value is
greater than the setting for tripping, the protection drops off instantaneously when current
disappears. Alarm outputs of the protection is not controlled by current, and only if the thermal
accumulation value is greater than the setting for alarm, alarm output contacts, which can be
connected to block the auto-reclosure, will operate.
49.On
49.En
49.St
49.Blk
49-1.Alm
49-1.Op
49-2.Alm
49-2.Op
Input Signal
49.Clr_Cmd
Description
Input signal of clear thermal accumulation value
3-210
3 Operation Theory
2
49.En
49.Blk
No.
Output Signal
Description
49.On
49.St
49-1.Op
49-2.Op
49-1.Alm
49-2.Alm
3.22.5 Logic
SIG
49.En
SIG
49.Blk
EN
[49-1.En_Trp]
EN
[49-1.En_Alm]
SIG
FD.Pkp
&
&
49.On
>=1
&
49.St
&
Timer
t
49-1.Op
t
SIG
I3P
&
SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
Timer
t
49-1.Alm
3-211
3 Operation Theory
SIG
49.En
SIG
49.Blk
EN
[49-2.En_Trp]
EN
[49-2.En_Alm]
SIG
FD.Pkp
&
&
49.On
>=1
&
49.St
Timer
t
&
49-2.Op
t
I3P
SIG
Timer
t
&
SET
[49.Ib_Set]
BI
[49.Clr_Cmd]
49-2.Alm
3.22.6 Settings
Table 3.22-2 Settings of thermal overload protection
No.
Name
Range
Step
Unit
49-1.K
1.000~3.000
0.001
49-2.K
1.000~3.000
0.001
49.Ib_Set
(0.050~30.000 )In
0.001
49.Tau
0.100~100.000
0.001
min
49-1.En_Alm
0 or 1
49-1.En_Trp
0 or 1
49-2.En_Alm
0 or 1
3-212
Remark
The factor setting for stage 1 of
thermal overload protection which
is associated to the thermal state
formula
The factor setting for stage 2 of
thermal overload protection which
is associated to the thermal state
formula
The reference current setting of the
thermal overload protection
The time constant setting of the
IDMT overload protection
Enabling/disabling stage 1 of
thermal overload protection for
alarm purpose
0: disable
1: enable
Enabling/disabling stage 1 of
thermal overload protection for trip
purpose
0: disable
1: enable
Enabling/disabling stage 2 of
thermal overload protection for
alarm purpose
0: disable
1: enable
3 Operation Theory
No.
Name
49-2.En_Trp
Range
Step
Unit
Remark
Enabling/disabling stage 2 of
thermal overload protection for trip
purpose
0: disable
1: enable
0 or 1
CT2
Bus
Bus
To the device
Line
Line
I 1 I 2 [87STB.I_Pkp]
I I
1
2 [87STB.Slop e] I 1 I 2
3-213
3 Operation Theory
Where:
I 1 I 2 are secondary phase currents corresponding to both circuit breakers, are formed by
phase A, B, C
3.23.2.2 Differential Current Alarm
Under normal conditions, when stub differential protection is enabled, the device will issue the
alarm signal [87STB.Alm_Diff] with the time delay if the following operation criterion is met.
I 1 I 2 [87STB.I_Al m]
I I
1
2 0.15 I 1 I 2
87STB.On
87STB.En2
87STB.On_Local
87STB.Blk
87STB.Op
87STB.89b_DS
87STB.St
87STB.89b_DS_Rmt
87STB.StA
87STB.StB
87STB.StC
87STB.Alm_Diff
87STB.Alm_89b_DS
3-214
3 Operation Theory
Input Signal
87STB.En1
87STB.En2
87STB.Blk
87STB.89b_DS
Description
Stub differential protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Stub differential protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Stub differential protection blocking input, it is triggered from binary input or
programmable logic etc.
Normally closed auxiliary contact of line disconnector
Normally closed auxiliary contact of line disconnector in remote end
87STB.89b_DS_Rmt
No.
Output Signal
Description
Stub differential protection is enabled. (Based on disconnector position signal
87STB.On
87STB.On_Local
87STB.Op
87STB.St
87STB.StA
87STB.StB
87STB.StC
87STB.Alm_Diff
87STB.Alm_89b_DS
3.23.5 Logic
Based on calculating vector summation of currents from dual CTs, the logic scheme of stub
differential protection is shown as Figure 3.23-2.
3-215
3 Operation Theory
SIG
Idiff>0.06In
SIG
87STB.89b_DS
SIG
87STB.En1
SIG
87STB.En2
EN
[87STB.En]
SIG
87STB.Blk
SIG
Enable 87STB
SIG
87STB.89b_DS
&
10s
10s
87STB.Alm_89b_DS
&
&
Enable 87STB
&
87STB.On_Local
>=1
&
SIG
87STB.89b_DS_Rmt
SET
Idiffa>[87STB.I_Alm]
SET
IdiffA>0.15IBiasA
SET
Idiffb>[87STB.I_Alm]
87STB.On
&
&
&
>=1
&
&
10s
SET
IdiffB>0.15IBiasB
SET
Idiffc>[87STB.I_Alm]
SET
IdiffC>0.15IBiasC
En
[87STB.En_Alm]
SIG
87STB.Alm_Diff
SIG
87STB.En_CTS_Blk
SET
Idiffa>[87STB.I_Pkp]
SET
IdiffA>[87STB.Slope]IBiasA
SET
Idiffb>[87STB.I_Pkp]
SET
IdiffB>[87STB.Slope]IBiasB
SET
Idiffc>[87STB.I_Pkp]
SET
IdiffC>[87STB.Slope]IBiasC
10s
87STB.Alm_Diff
&
&
>=1
>=1
87STB.St
[87STB.t_Op]
87STB.Op
&
87STB.StA
&
&
87STB.StB
&
&
87STB.StC
&
3.23.6 Settings
Table 3.23-2 Settings of stub differential protection
No.
1
Name
87STB.I_Pkp
Range
Step
Unit
(0.050~30.000)In
0.001
3-216
Remark
Pickup current setting of stub
differential protection
PCS-931 Line Differential Relay
Date: 2015-10-22
3 Operation Theory
No.
Name
Range
Step
Unit
A
87STB.I_ Alm
(0.050~30.000)In
0.001
87STB.Slope
0.5~1
0.001
87STB.t_Op
0.000~10.000
0.001
Remark
Current
setting
of
differential
current
differential
current alarm
Slope
of
protection
s
87STB.En
protection
0 or 1
1: enable
0: disable
Enabling/disabling
87STB.En_Alm
differential
0 or 1
1: enable
0: disable
Enabling/disabling stub differential
protection controlled by CT circuit
87STB.En_CTS_Blk
0 or 1
failure
1: enable
0: disable
3 Operation Theory
initiate dead zone protection), if overcurrent element for dead zone protection operates, then
corresponding circuit breaker is tripped and three phases normally closed contact of the circuit
breaker are energized, dead zone protection will operate to trip adjacent circuit breaker after a
time delay.
CBx.50DZ.On
CBx.50DZ.En2
CBx.50DZ.Op
CBx.50DZ.Blk
CBx.50DZ.St
CBx.50DZ.Init
Input Signal
Description
CBx.50DZ.En1
Dead zone protection enabling input 1, it can be binary inputs or logic link.
CBx.50DZ.En2
Dead zone protection enabling input 2, it can be binary inputs or logic link.
CBx.50DZ.Blk
CBx.50DZ.Init
No.
Dead zone protection blocking input, such as function blocking binary input. When
the input is 1, dead zone protection is reset and time delay is cleared.
Initiation signal input of the dead zone protection.
Output Signal
Description
CBx.50DZ.On
CBx.50DZ.St
CBx.50DZ.Op
3-218
3 Operation Theory
3.24.5 Logic
EN
[CBx.50DZ.En]
SIG
CBx.50DZ.En1
SIG
CBx.50DZ.En2
SIG
CBx.50DZ.Blk
&
&
CBx.50DZ.On
&
CBx.50DZ.St
&
[CBx.50DZ.t_Op]
SIG
FD.Pkp
SIG
CBx.52b_PhA
SIG
CBx.52b_PhB
SIG
CBx.52b_PhC
SET
Ia > [CBx.50DZ.I_Set]
SET
Ib > [CBx.50DZ.I_Set]
SET
Ic > [CBx.50DZ.I_Set]
SIG
CBx.50DZ.Init
SIG
CBx.Trp
0ms
CBx.50DZ.Op
&
>=1
&
>=1
3.24.6 Settings
Table 3.24-2 Settings of dead zone protection
No.
Name
Range
Step
Unit
Remark
Current
CBx.50DZ.I_Set
(0.050~30.000)In
0.001
setting
for
dead
zone
CBx.50DZ.t_Op
0.000~10.000
0.001
CBx.50DZ.En
0 or 1
dead
zone
protection.
1: enable
0: disable
3 Operation Theory
Pole discrepancy protection is required to operate before the operation of these overcurrent
elements.
NOTICE!
For double circuit breakers mode, the device will provide indenpendent pole
discrepancy protection for CB1 and CB2 respectively. Both pole discrepancy
protections have the same logic.The difference is that the prefix CBx. is added to all
signals and settings for circuit breaker No.x (x=1 or 2).
CBx.62PD.On
CBx.62PD.En2
CBx.62PD.Op
CBx.62PD.Blk
CBx.62PD.St
Input Signal
CBx.62PD.En1
CBx.62PD.En2
CBx.62PD.Blk
No.
Description
Pole discrepancy protection enabling input 1, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection enabling input 2, it is triggered from binary input or
programmable logic etc.
Pole discrepancy protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
CBx.62PD.On
CBx.62PD.Op
CBx.62PD.St
3.25.5 Logic
Phase-segregated circuit breaker auxiliary contacts are connected to the device. When the state
of three phase-segregated circuit breaker auxiliary contacts are inconsistent, pole discrepancy
protection will be started and initiate output after a time delay [CBx.62PD.t_Op].
3-220
3 Operation Theory
Pole discrepancy protection can be blocked by external input signal [62PD.Blk]. In general, this
input signal is usually from the output of 1-pole AR initiation, so as to prevent pole discrepancy
protection from operation during 1-pole AR initiation.
SIG
CBx.62PD.En1
SIG
CBx.62PD.En2
EN
[CBx.62PD.En]
SIG
CBx.62PD.Blk
SIG
FD.Pkp
&
&
62PD.On
&
EN
[CBx.62PD.En_3I0/I2_Ctrl]
SET
3I0>[CBx.62PD.3I0_Set]
SET
I2>[CBx.62PD.I2_Set]
BI
[CBx.52b_PhA]
>=1
>=1
&
&
SIG
CBx.Ia<0.06In
BI
[CBx.52b_PhB]
SIG
CBx.Ib<0.06In
BI
[CBx.52b_PhC]
SIG
CBx.Ic<0.06In
&
62PD.St
[62PD.t_Op]
&
0ms
62PD.Op
&
>=1
&
The signal CBx.62PD.In_PD is input signal of pole discrepancy status, which is always from PD
signal of circuit breaker position supervison module. When the states of three auxiliary contacts of
phase-segregate circuit breaker are inconsistent, the signal is energized.
3.25.6 Settings
Table 3.25-2 Settings of pole discrepancy protection
No.
Name
Range
Step
Unit
CBx.62PD.3I0_Set
(0.050~30.000 )In
0.001
CBx.62PD.I2_Set
(0.050~30.000 )In
0.001
CBx.62PD.t_Op
0.000~600.000
0.001
CBx.62PD.En
0 or 1
Remark
Current setting of residual
current
criterion
for
pole
discrepancy protection
Current
setting
of
negative-sequence
current
criterion for pole discrepancy
protection
Time delay of pole discrepancy
protection
Enabling/disabling
pole
discrepancy protection
0: disable
3-221
3 Operation Theory
No.
Name
CBx.62PD.En_3I0/I2_Ctrl
Range
Step
Unit
Remark
1: enable
Enabling/disabling
residual
current
criterion
and
negative-sequence
current
criterion for pole discrepancy
protection
0: disable
1: enable
0 or 1
3-222
3 Operation Theory
46BC.On
46BC.En2
46BC.St
46BC.Blk
46BC.Op
46BC.Alm
Input Signal
46BC.En1
46BC.En2
46BC.Blk
No.
Description
Enable broken conductor protection input 1, it is triggered from binary input or
programmable logic etc.
Enable broken conductor protection input 2, it is triggered from binary input or
programmable logic etc.
Broken conductor protection blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
Description
46BC.On
46BC.St
46BC.Op
46BC.Alm
3.26.5 Logic
SIG
[46BC.En1]
SIG
[46BC.En2]
SIG
[46BC.Blk]
&
&
46BC.On
46BC.St
&
[46BC.t_Op] 0ms
SET
Ia>[46BC.I_Min]
>=1
SET
Ib>[46BC.I_Min]
SET
Ic>[46BC.I_Min]
SET
SET
&
I2/I1>[46BC.I2/I1_Set]
46BC.Op
[46BC.En_Trp]
&
46BC.Alm
SET
[46BC.En_Alm]
3 Operation Theory
3.26.6 Settings
Table 3.26-2 Settings of broken conductor protection
No.
Name
Range
Step
Unit
Remark
Ratio
46BC.I2/I1_Set
0.20~1.00
0.001
setting
(negative-sequence
46BC.t_Op
0.000~600.000
0.001
46BC.I_Min
(0.050~30.000)In
0.001
Time
delay
of
broken
conductor
protection
Minimum operation current of broken
conductor protection
Enabling/disabling broken conductor
46BC.En_Trp
0 or 1
0: disable
1: enable
Enabling/disabling broken conductor
46BC.En_Alm
0 or 1
0: disable
1: enable
3 Operation Theory
different. During testing in the primary side of the generator unit, the active power absorbed by the
generator can be measured by the device.
When the device is equipped with power plant side, reverse power is negative value, and reverse
power is positive value when it is equipped with substation side.
The operation criterion:
[32R.Opt_Dir]=Reverse AND P<-[32Rx.P_Set]
or
[32R.Opt_Dir]=Forward AND P>[32Rx.P_Set]
P1
32Rx.Blk
32Rx.On
32Rx.St
32Rx.Op
32R1.Alm
Input Signal
32Rx.En
32Rx.Blk
No.
Description
Enable stage x of reverse power protection input 1, it is triggered from binary
input or programmable logic etc. (x=1, 2)
Stage x of reverse power protection blocking input, it is triggered from binary
input or programmable logic etc. (x=1, 2)
Output Signal
Description
P1
32Rx.On
32Rx.St
32Rx.Op
32R1.Alm
3-225
3 Operation Theory
3.27.5 Logic
SIG
32R1.En
SIG
32R1.Blk
EN
[32R1.En_Alm]
EN
[32R1.En_Trp]
SIG
32R1.On
SET
[32R.Opt_Dir]=Reverse
SIG
P1<-[32R1.P_Set]
&
&
SET
[32R.Opt_Dir]=Forward
SIG
P1>[32R1.P_Set]
32R1.On
>=1
&
&
32R1.St
>=1
&
&
EN
[32R1.t_Alm]
0s
32R1.Alm
[32R1.t_Trp]
0s
32R1.Op
[32R1.En_Alm]
&
EN
[32R1.En_Trp]
32R2.En
SIG
32R2.Blk
EN
[32R2.En_Trp]
SIG
32R2.On
SET
[32R.Opt_Dir]=Reverse
SIG
P1<-[32R2.P_Set]
SET
[32R.Opt_Dir]=Forward
SIG
P1>[32R2.P_Set]
&
&
32R2.On
&
32R2.St
&
>=1
&
&
[32R2.t_Trp]
EN
0s
32R2.Op
[32R2.En_Trp]
When stage 2 of reverse power protection is used as sequential tripping reverse power protection,
it can be selectable to be controlled by position contact of steam valve and circuit breaker
3-226
3 Operation Theory
3.27.6 Settings
Table 3.27-2 Settings of broken conductor protection
No.
Name
Range
Step
Unit
Remark
Power setting of stage 1 of reverse
32R1.P_Set
(0.100~50.000)In
0.01
power protection
It should be greater 0.5 times the
measured value of reverse power.
32R1.t_Alm
0.100~3000.000
0.01
32R1.t_Trp
0.100~3000.000
0.01
32R1.En_Trp
0 or 1
0: disable
1: enable
Enabling/disabling stage 1 of reverse
32R1.En_Alm
0 or 1
0: disable
1: enable
Power setting of stage 2 of reverse
32R2.P_Set
(0.100~50.000)In
0.01
power protection
It should be greater 0.5 times the
measured value of reverse power.
32R2.t_Trp
0.100~3000.000
0.01
32R2.En_Trp
0 or 1
0: disable
1: enable
32R.Opt_Dir
The
Forward
directionality
direction
Reverse
or
option
reverse
(forward
direction)
of
3.28 Synchrocheck
3.28.1 General Application
The purpose of synchrocheck is to ensure two systems are synchronism before they are going to
be connected.
When two asynchronous systems are connected together, due to phase difference between the
two systems, larger impact will be led to the system during closing. Thus auto-reclosing and
manual closing are applied with the synchrocheck to avoid this situation and maintain the system
stability. The synchrocheck includes synchronism check and dead charge check.
3-227
3 Operation Theory
NOTICE!
For double circuit breakers mode, the device will provide indenpendent synchrocheck
function for CB1 and CB2 respectively. Both synchrocheck functions have the same
logic.The difference is that the prefix CBx. is added to all signals and settings for
circuit breaker No.x (x=1 or 2).
CBx.Usyn
When both line and busbar are live, the synchronism check element operates if voltage difference,
phase angle difference and frequency difference are all within their setting values.
1.
CBx.Usyn[CBx.25.U_Lv]
CBx.Uref[CBx.25.U_Lv]
[CBx.25.U_Diff]|CBx.Usyn-CBx.Uref|
2.
CBx.UsynCBx.Urefcos0
3-228
3 Operation Theory
CBx.UsynCBx.Urefsin([CBx.25.phi_Diff])CBx.UsynCBx.Uref|sin|
Where,
is phase difference between Usyn and Uref
3.
|f(CBx.Usyn)-f(CBx.Uref)|[CBx.25.f_Diff]
If frequency check is disabled (i.e. [CBx.25.En_fDiffChk] is set as 0), a detected maximum slip
cycle can also be determined by the following equation based on phase difference setting and the
synchronism check time setting:
f =[CBx.25.phi_Diff]/(180[CBx.25.t_SynChk])
Where:
f is slip cycle
If frequency check is enabled (i.e. [CBx.25.En_fDiffChk] is set as 1), [CBx.25.t_SynChk] can be
set to be a very small value (default value is 50ms).
This function module supports voltage switching. In general, voltage switching is fulfilled by
external circuit, and the busbar arrangement should be determined, including three options, single
busbar arrangement, double busbars arrangement and 1 breakers arrangement, if using this
module to fulfill voltage switching.
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on.
UB1: it connects with single synchronism voltage (from line or busbar).
UL2: it connects with single synchronism voltage (from the other line of the same diameter in 1
breakers arrangement). When voltage switching is available, it is only used by 1 breakers
arrangement.
UB2: it connects with single synchronism voltage (from busbar). When voltage switching is
available, it is only used by double busbars arrangement and 1 breakers arrangement.
The reference voltage (Uref) is determined to use phase voltage or phase-to-phase voltage (UL1)
from three-phase protection voltages and by the setting [CBx.25.Opt_Source_UL1].
The synchronism voltage (Usyn) always connects with UB1 if not adopting voltage switching. It
connects with one of UB1, UL2 and UB2 according to the result of voltage switching if adopting
voltage switching.
3.28.2.1 Single Busbar Arrangement
Voltage selection function is not required for this busbar arrangement, the connection of the
voltage signals and respective VT MCB auxiliary contacts to the device is shown in the Figure
3.28-2 and Figure 3.28-3.
3-229
3 Operation Theory
1.
UL1
Ua
CB
Ub
Uc
25.MCB_VT_UL1
UB1
25.MCB_VT_UB1
Line
2.
CB
UB1
25.MCB_VT_UB1
UL1
Ua
Ub
Uc
25.MCB_VT_UL1
Line
In the figures, the setting [CBx.VTS.En_LineVT] is used to determine protection voltage signals
(Ua, Ub, Uc) from line VT or bus VT according to the condition.
3-230
3 Operation Theory
B1D B2D
UB1
25.MCB_VT_UB1
UB2
25.MCB_VT_UB2
25.NC_UB1DS
25.NO_UB1DS
CB
25.NC_UB2DS
25.NO_UB2DS
UL1
Ua
Ub
Line
Uc
25.MCB_VT_UL1
For double busbars arrangement, selection of appropriate voltage signals from Bus 1 and Bus 2
for synchronizing are required. Line VT signal is taken as reference to check synchronizing with
the voltage after voltage selection function. Selection approach is as follows.
For the disconnector positions, the normally open (NO) and normally closed (NC) contacts of the
disconnector for bus 1 and bus 2 are required to determine the disconnector open and closed
positions. The voltage selection logic is as follows.
25.NC_UB1DS
BI
25.NO_UB1DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
&
&
BI
CBx.UB1_Sel
CBx.UB2_Sel
&
CBx.Alm_Invalid_Sel
UB1
CBx.Usyn
UB2
3-231
3 Operation Theory
After acquiring the disconnector open and closed positions of double busbars, use the following
logic to acquire the feeder voltage of double busbars.
DS2 CLOSED
DS2 OPEN
DS1 CLOSED
DS1 OPEN
UB1
25.MCB_VT_UB1
25.NC_UB1DS
B1D
25.NO_UB1DS
UL1
Ua
Line 1
Ub
Uc
25.MCB_VT_UL1
L1D
25.NC_UL1DS
25.NO_UL1DS
Line 2
UL2
25.MCB_VT_UL2
25.NC_UL2DS
25.NO_UL2DS
L2D
25.NC_UB2DS
25.NO_UB2DS
UB2
25.MCB_VT_UB2
B2D
Bus2
Figure 3.28-6 Voltage connection for one and a half breakers arrangement
3-232
3 Operation Theory
For the circuit breaker at bus side (take bus breaker of bus 1 as an example), the device acquires
the disconnector open and closed positions of two feeders and bus 2. The voltage selection logic
is as follows.
BI
25.NC_UL1DS
&
CBx.UL1_Sel
BI
25.NO_UL1DS
BI
25.NC_UL2DS
BI
25.NO_UL2DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
&
CBx.UL2_Sel
&
&
CBx.UB2_Sel
&
&
CBx.Alm_Invalid_Sel
UL1
CBx.Uref
UL2
UB2
UB1
CBx.Usyn
Figure 3.28-7 Voltage selection for one and a half breakers arrangement
For the tie breaker, the device acquires the disconnector open and closed positions of two feeders
and two busbars. Either Line 1 VT or Bus 1 VT signal is selected as reference voltage to check
synchronizing with the selected voltage between Line 2 VT and Bus 2 VT. The voltage selection
logic is as follows.
3-233
3 Operation Theory
BI
25.NC_UL1DS
&
CBx.UL1_Sel
BI
25.NO_UL1DS
BI
25.NC_UB1DS
BI
25.NO_UB1DS
&
CBx.UB1_Sel
&
&
UL1
CBx.Uref
UB1
BI
25.NC_UL2DS
BI
25.NO_UL2DS
BI
25.NC_UB2DS
BI
25.NO_UB2DS
&
CBx.UL2_Sel
&
CBx.UB2_Sel
&
>=1
&
UL2
CBx.Alm_Invalid_Sel
CBx.Usyn
UB2
Figure 3.28-8 Voltage selection for one and a half breakers arrangement
When the voltage selection fails (including VT circuit failure and MCB failure), the device will issue
the corresponding failure signal. If the voltage selection is invalid (CBx.Alm_Invalid_Sel=1), keep
original selection and without switchover.
In order to simplify description, one of the two voltages used in the synchrocheck (synchronism check
and dead charge check) which obtained after voltage selection function is regarded as line voltage,
and another is bus voltage.
3.28.2.4 Synchronism Voltage Circuit Failure Supervision
If synchronism voltage and reference voltage are used for auto-reclosing with synchronism or
dead line or busbar check, the VT circuit of synchronism voltage and reference voltage are
monitored.
Under normal conditions, the circuit breaker is in closed position but the synchronism voltage is
lower than the setting [CBx.25.U_Lv], it means that synchronism voltage circuit fails and an alarm
[CBx.25.Alm_VTS_Usyn] or [CBx.25.Alm_VTS_Uref] will be issued with a time delay of 10s. If
MCB of synchronism voltage or reference voltage is open, an alarm [CBx.25.Alm_VTS_Usyn] or
[CBx.25.Alm_VTS_Uref] will be issued instantaneously. After synchronism voltage reverted to
normal condition, the alarm will be reset automatically with a time delay of 10s. When synchronism
voltage circuit failure is detected, dead check in auto-reclosing logic will be disabled. If the logic
setting [CBx.25.En_NoChk] is set as 1, synchronism voltage circuit failure supervision will be
3-234
3 Operation Theory
disabled.
SIG
FD.Pkp
SIG
CBx.79.Inprog
SIG
CBx.Uref<[CBx.25.U_Lv]
SIG
25.MCB_VT_Uref
SIG
CBx.25.On_SynChk
SIG
CBx.25.On_DdL_DdB
SIG
CBx.25.On_DdL_LvB
SIG
CBx.25.On_LvL_DdB
SIG
CBx.25.Blk_VTS_UL
>=1
&
10s
10s
>=1
&
CBx.25.Alm_VTS_Uref
>=1
>=1
&
FD.Pkp
SIG
CBx.79.Inprog
SIG
CBx.Usyn<[CBx.25.U_Lv]
SIG
25.MCB_VT_Usyn
SIG
CBx.25.On_SynChk
SIG
CBx.25.On_DdL_DdB
SIG
CBx.25.On_DdL_LvB
SIG
CBx.25.On_LvL_DdB
SIG
CBx.25.Blk_VTS_UB
>=1
&
10s
10s
>=1
&
CBx.25.Alm_VTS_Usyn
>=1
>=1
&
As shown in Figure 3.28-9 and Figure 3.28-10, 25.MCB_VT_Uref is MCB signal corresponding to
reference voltage after switching and 25.MCB_VT_Usyn is MCB signal corresponding to
synchronism voltage after switching.
3-235
3 Operation Theory
CBx.UL1_Sel
CBx.25.Blk_SynChk
CBx.UL2_Sel
CBx.25.Blk_DdChk
CBx.UB1_Sel
CBx.25.Start_Chk
CBx.UB2_Sel
CBx.25.Start_3PLvChk
CBx.25.Sel_SynChk
CBx.Alm_Invalid_Sel
CBx.25.Ok_fDiffChk
CBx.25.Sel_DdL_DdB
CBx.25.Ok_UDiffChk
CBx.25.Sel_DdL_LvB
CBx.25.Ok_phiDiffChk
CBx.25.Sel_LvL_DdB
CBx.25.Ok_DdL_DdB
CBx.25.Sel_NoChk
CBx.25.Ok_DdL_LvB
CBx.25.Blk_VTS_Uref
CBx.25.Ok_LvL_DdB
CBx.25.Blk_VTS_Usyn
CBx.25.Chk_LvL
25.MCB_VT_UL1
CBx.25.Chk_DdL
25.MCB_VT_UL2
CBx.25.Chk_LvB
25.MCB_VT_UB1
CBx.25.Chk_DdB
25.MCB_VT_UB2
CBx.25.Ok_DdChk
25.NC_UL1DS
CBx.25.Ok_SynChk
25.NO_UL1DS
CBx.25.Ok_Chk
25.NC_UB1DS
CBx.25.Ok_3PLvChk
25.NO_UB1DS
CBx.25.Alm_VTS_Uref
25.NC_UL2DS
CBx.25.Alm_VTS_Usyn
25.NO_UL2DS
CBx.25.f_Ref
25.NC_UB2DS
CBx.25.f_Syn
25.NO_UB2DS
CBx.25.U_Diff
CBx.25.f_Diff
CBx.25.Phi_Diff
3-236
3 Operation Theory
Input Signal
Description
CBx.25.Blk_Chk
CBx.25.Blk_SynChk
CBx.25.Blk_DdChk
CBx.25.Start_Chk
CBx.25.Start_3PLvChk
CBx.25.Sel_ SynChk
CBx.25.Sel_DdL_DdB
CBx.25.Sel_DdL_LvB
CBx.25.Sel_ LvL_DdB
10
CBx.25.Sel_ NoChk
No check is selected.
11
CBx.25.Blk_VTS_Usyn
12
CBx.25.Blk_VTS_Uref
13
25.MCB_VT_UL1
14
25.MCB_VT_UL2
15
25.MCB_VT_UB1
16
25.MCB_VT_UB2
17
25.NC_UL1DS
18
25.NO_UL1DS
19
25.NC_UB1DS
20
25.NO_UB1DS
21
25.NC_UL2DS
22
25.NO_UL2DS
23
25.NC_UB2DS
24
25.NO_UB2DS
No.
Output Signal
Description
CBx.UL1_Sel
CBx.UL2_Sel
CBx.UB1_Sel
CBx.UB2_Sel
CBx.Alm_Invalid_Sel
CBx.25.Ok_fDiffChk
CBx.25.Ok_UDiffChk
CBx.25.Ok_phiDiffChk
3-237
3 Operation Theory
9
CBx.25.Ok_DdL_DdB
10
CBx.25.Ok_DdL_LvB
11
CBx.25.Ok_LvL_DdB
12
CBx.25.Chk_LvL
13
CBx.25.Chk_DdL
14
CBx.25.Chk_LvB
15
CBx.25.Chk_DdB
16
CBx.25.Ok_DdChk
17
CBx.25.Ok_SynChk
18
CBx.25.Ok_Chk
19
CBx.25.Ok_3PLvChk
20
CBx.25.Alm_VTS_Uref
21
CBx.25.Alm_VTS_Usyn
22
CBx.25.f_Ref
23
CBx.25.f_Syn
24
CBx.25.U_Diff
25
CBx.25.f_Diff
26
CBx.25.phi_Diff
3.28.5 Logic
3.28.5.1 Synchronism Check Logic
The frequency difference, voltage difference, and phase difference of voltages from both sides of
the circuit breaker are calculated in the device, they are used as input conditions of the
synchronism check. When the synchronism check function is enabled and the voltages of both
ends meets the requirements of the voltage difference, phase difference, and frequency difference,
and there is no synchronism check blocking signal, it is regarded that the synchronism check
conditions are met.
Synchronism check logic is usually used for 3-pole AR, and 1-pole AR usually adopts no check
logic. However, the circuit breaker at local end can not reclosed unless the circuit breaker at
remote end is reclosed successfully. In order to meet this requirement, live three-phase check can
be used for 1-pole AR, determined by the setting [CBx.25.En_3PLvChk], ensure that three-phase
voltages is restored to normal at local end after the circuit breaker at remote end is reclosed.
Synchrocheck mode can be determined by the setting [CBx.25.SetOpt] or external signal. As
shown in Figure 3.28-11, when the setting [CBx.25.SetOpt] is set as 1, synchrocheck mode is
determined by the setting. Otherwise, synchrocheck mode is determined by external signal.
3-238
3 Operation Theory
1
EN
[CBx.25.En_SynChk]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_DdB]
SIG
CBx.25.Sel_SynChk
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_LvL_DdB]
SIG
CBx.25.Sel_LvL_DdB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_DdL_LvB]
CBx.25.On_SynChk
0
1
CBx.25.On_DdL_DdB
0
1
CBx.25.On_LvL_DdB
0
1
CBx.25.On_DdL_LvB
SIG
CBx.25.Sel_DdL_LvB
EN
[CBx.25.SetOpt]
EN
[CBx.25.En_NoChk]
SIG
CBx.25.Sel_NoChk
EN
[CBx.25.SetOpt]
1
CBx.25.On_NoChk
0
[CBx.25.En_3PLvChk]
>=1
SIG CBx.Uref.a>[CBx.25.U_Lv]
&
SIG CBx.Uref.b>[CBx.25.U_Lv]
SIG CBx.Uref.c>[CBx.25.U_Lv]
&
200ms
SIG CBx.25.Start_3PLvChk
SIG CBx.25.Blk_Chk
0ms
CBx.25.Ok_3PLvChk
>=1
&
SIG CBx.25.Blk_SynChk
&
SIG CBx.25.On_SynChk
SIG CBx.25.Start_Chk
SIG CBx.Usyn>[CBx.25.U_Lv]
SIG CBx.Uref>[CBx.25.U_Lv]
&
&
50ms
0ms
&
[CBx.25.t_SynChk]
0ms
CBx.25.Ok_SynChk
SIG CBx.25.Ok_UdiffChk
SIG CBx.25.Ok_phiDiffChk
SIG CBx.25.Ok_fDiffChk
3-239
3 Operation Theory
CBx.25.Blk_Chk
SIG
CBx.25.Blk_DdChk
>=1
&
&
[CBx.25.t_DdChk]
>=1
SIG
CBx.25.Start_Chk
SIG
CBx.25.On_DdL_DdB
SIG
CBx.Uref<[CBx.25.U_Dd]
SIG
CBx.Usyn<[CBx.25.U_Dd]
SIG
CBx.25.On_DdL_LvB
SIG
CBx.Uref<[CBx.25.U_Dd]
SIG
CBx.Usyn>[CBx.25.U_Lv]
SIG
CBx.25.On_LvL_DdB
SIG
CBx.Uref>[CBx.25.U_Lv]
SIG
CBx.Usyn<[CBx.25.U_Dd]
SIG
CBx.25.Alm_VTS_Usyn
SIG
CBx.25.Alm_VTS_Uref
0ms
CBx.25.Ok_DdChk
&
CBx.25.Ok_DdL_DdB
&
&
CBx.25.Ok_DdL_LvB
&
&
CBx.25.Ok_LvL_DdB
&
>=1
SIG
CBx.25.Ok_SynChk
SIG
CBx.25.On_NoChk
SIG
CBx.25.Ok_DdChk
>=1
CBx.25.Ok_Chk
3.28.6 Settings
Table 3.28-2 Synchrocheck settings
No.
Name
CBx.25.Opt_Source_UL1
Range
Step
Ua
Unit
Remark
Voltage selecting mode of line 1.
3-240
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Ub
Uc
Uab
Ubc
Uca
Ua
Ub
2
CBx.25.Opt_Source_UB1
Uc
Uab
Ubc
Uca
Ua
Ub
3
CBx.25.Opt_Source_UL2
Uc
Uab
Ubc
Uca
Ua
Ub
4
CBx.25.Opt_Source_UB2
Uc
Uab
Ubc
Uca
of
circuit
breaker
NoVoltSel
DblBusOneCB:
DblBusOneCB
3/2BusCB
3/2BusCB:
3/2TieCB
CBx.CBConfigMode
bus
one
side
circuit
circuit
breakers
3/2TieCB:
line
side
circuit
CBx.25.U_Dd
0.05Un~0.8Un
0.001
CBx.25.U_Lv
0.5Un~Un
0.001
3-241
3 Operation Theory
No.
Name
Range
CBx.25.K_Usyn
0.20-5.00
CBx.25.phi_Diff
0~ 89
Step
Unit
Remark
Compensation
coefficient
synchronism voltage
1
deg
Phase
difference
CBx.25.phi_Comp
0~359
deg
limit
of
10
for
difference
for
phase
between
two
synchronism voltages
11
CBx.25.f_Diff
0.02~1.00
0.01
Hz
12
CBx.25.U_Diff
0.02Un~0.8Un
13
CBx.25.t_DdChk
0.010~25.000
14
CBx.25.t_SynChk
0.010~25.000
difference
CBx.25.En_fDiffChk
of
delay
to
confirm
15
limit
frequency
difference check
0 or 1
0: disable
1: enable
Synchrocheck mode selection
16
CBx.25.SetOpt
0, 1
17
CBx.25.En_SynChk
check
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
18
CBx.25.En_DdL_DdB
0 or 1
0: disable
1: enable
Enabling/disabling dead line and
19
CBx.25.En_DdL_LvB
0 or 1
0: disable
1: enable
Enabling/disabling live line and
20
CBx.25.En_LvL_DdB
0 or 1
0: disable
1: enable
Enabling/disabling AR without
21
CBx.25.En_NoChk
any check
0 or 1
0: disable
1: enable
22
CBx.25.En_3PLvChk
0 or 1
Enabling/disabling
3-242
live
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
three-phase check of line
0: disable
1: enable
3-243
3 Operation Theory
3-244
3 Operation Theory
CBx.79.On
CBx.79.Blk
CBx.79.Off
CBx.79.Sel_1PAR
CBx.79.Close
CBx.79.Sel_3PAR
CBx.79.Ready
CBx.79.Sel_1P/3PAR
CBx.79.AR_Blkd
CBx.79.Trp
CBx.79.Active
CBx.79.Trp3P
CBx.79.Inprog
CBx.79.TrpA
CBx.79.Inprog_1P
CBx.79.TrpB
CBx.79.Inprog_3P
CBx.79.TrpC
CBx.79.Inprog_3PS1
CBx.79.LockOut
CBx.79.Inprog_3PS2
CBx.79.PLC_Lost
CBx.79.Inprog_3PS3
CBx.79.WaitMaster
CBx.79.Inprog_3PS4
CBx.79.CB_Healthy
CBx.79.WaitToSlave
CBx.79.Clr_Counter
CBx.79.Perm_Trp1P
CBx.79.Ok_Chk
CBx.79.Perm_Trp3P
CBx.79.Ok_3PLvChk
CBx.79.Rcls_Status
CBx.79.Fail_Rcls
CBx.79.Succ_Rcls
CBx.79.Fail_Chk
CBx.79.Mode_1PAR
CBx.79.Mode_3PAR
CBx.79.Mode_1/3PAR
Input Signal
CBx.79.En
CBx.79.Blk
Description
Binary input for enabling AR. If the logic setting [79.En_ExtCtrl]=1,
enabling AR will be controlled by the external signal via binary input
Binary input for disabling AR. If the logic setting [79.En_ExtCtrl]=1,
disabling AR will be controlled by the external input
3-245
3 Operation Theory
Input signal for selecting 1-pole AR mode of corresponding circuit
CBx.79.Sel_1PAR
CBx.79.Sel_3PAR
CBx.79.Sel_1P/3PAR
CBx.79.Trp
CBx.79.Trp3P
CBx.79.TrpA
CBx.79.TrpB
10
CBx.79.TrpC
breaker
Input signal for selecting 3-pole AR mode of corresponding circuit
breaker
Input signal for selecting 1/3-pole AR mode of corresponding circuit
breaker
CBx.79.LockOut
12
CBx.79.PLC_Lost
13
CBx.79.WaitMaster
14
CBx.79.CB_Healthy
15
CBx.79.Clr_Counter
16
CBx.79.Ok_Chk
17
CBx.79.Ok_3PLvChk
No.
Input signal of indicating the alarm signal that signal channel is lost
Input signal of waiting for reclosing permissive signal from master
AR (when reclosing multiple circuit breakers)
The input for indicating whether circuit breaker has enough energy to
perform the close function
Output Signal
Description
CBx.79.On
CBx.79.Off
CBx.79.Close
CBx.79.Ready
CBx.79.AR_Blkd
CBx.79.Active
CBx.79.Inprog
CBx.79.Inprog_1P
CBx.79.Inprog_3P
10
CBx.79.Inprog_3PS1
11
CBx.79.Inprog_3PS2
12
CBx.79.Inprog_3PS3
13
CBx.79.Inprog_3PS4
14
CBx.79.WaitToSlave
15
CBx.79.Perm_Trp1P
16
CBx.79.Perm_Trp3P
17
CBx.79.Rcls_Status
3-246
3 Operation Theory
0: AR is ready.
1: AR is in progress.
2: AR is successful.
18
CBx.79.Fail_Rcls
Auto-reclosing fails
19
CBx.79.Succ_Rcls
Auto-reclosing is successful
20
CBx.79.Fail_Chk
21
CBx.79.Mode_1PAR
22
CBx.79.Mode_3PAR
23
CBx.79.Mode_1/3PAR
24
CBx.79.N_Total_Rcls
25
CBx.79.N_1PS1
26
CBx.79.N_3PS1
27
CBx.79.N_3PS2
28
CBx.79.N_3PS3
29
CBx.79.N_3PS4
3.29.5 Logic
3.29.5.1 AR Ready
For the first reclosing of multi-shot AR, AR mode can be 1-pole AR or 3-pole AR, however, the
selection is valid only to the first reclosing, after that it can only be 3-pole AR. When logic setting
[CBx.79.SetOpt] is set as 1, AR mode is determined by logic settings. When logic setting
[CBx.79.SetOpt] is set as 0, AR mode is determined by external signal via binary inputs.
An auto-reclosure must be ready to operate before performing reclosing. The output signal
[CBx.79.Ready] means that the auto-reclosure can perform at least one time of reclosing function,
i.e., breaker open-close-open.
When the device is energized or after the settings are modified, AR can not be ready unless the
following conditions are met:
1.
AR function is enabled.
2.
The circuit breaker is ready, such as, normal storage energy and no low pressure signal.
3.
The duration of the circuit breaker in closed position before fault occurrence is not less than
the setting [CBx.79.t_CBClsd].
4.
After the auto-reclosure operates, the auto-reclosure must reset, i.e., [CBx.79.Active]=0, in
addition to the above conditions for reclosing again.
When there is a fault on an overhead line, the concerned circuit breakers will be tripped normally.
After fault is cleared, the tripping command will drop off immediately. In case the circuit breaker is
in failure, etc., and the tripping signal of the circuit breaker maintains and in excess of the time
delay [CBx.79.t_PersistTrp], AR will be blocked, as shown in Figure 3.29-1.
3-247
3 Operation Theory
SIG
SIG
CBx.79.LockOut
SIG
1-pole AR Initiation
SIG
EN
[CBx.79.En_PDF_Blk]
SIG
CBx.79.Sel_1PAR
EN
[CBx.79.N_Rcls]=1
SIG
SIG
Phase A open
SIG
Phase B open
[CBx.79.t_PersistTrp]
0ms
>=1
0ms [CBx.79.t_DDO_BlkAR]
[CBx.79.t_SecFault] 0ms
>=1
CBx.79.AR_Blkd
&
&
&
>=1
&
&
>=1
&
SIG
Phase C open
The input signal [CBx.79.CB_Healthy] must be energized before auto-reclosure gets ready.
Because most circuit breakers can finish one complete process: open-closed-open, it is necessary
that circuit breaker has enough energy before reclosing. When the time delay of AR is exhausted,
AR will be blocked if the input signal [CBx.79.CB_Healthy] is still not energized within time delay
[CBx.79.t_CBReady]. If this function is not required, the input signal [CBx.79.CB_Healthy] can be
not to configure, and its state will be thought as 1 by default.
In orde to block AR reliably even if the signal of manually open circuit breaker not connected to the
input of blocking AR, when the circuit breaker is open by manually and there is CB position input
under normal conditions, AR will be blocked with the time delay of 100ms if AR is not initated and
no any trip signal.
When auto-reclosure is blocked, auto-reclosing failure, synchrocheck failure or last shot is
reached, or when the internal blocking condition of AR is met (such as, zone 3 of distance
protection operates, the device operates for multi-phase fault, three-phase fault and so on. These
flags of blocking AR have been configured in the device, additional configuration is not required.),
auto-reclosure will be discharged immediately and next auto-reclosing will be disabled.
When the input signal [CBx.79.LockOut] is energized, auto-reclosure will be blocked immediately.
The blocking flag of AR will be also controlled by the internal blocking condition of AR. When the
blocking flag of AR is valid, auto-reclosure will be blocked immediately. The logic of AR ready is
shown in Figure 3.29-2.
3-248
3 Operation Theory
>=1
SIG
3 CB closed
[CBx.79.t_CBClsd]
SIG
CBx.79.Active
>=1
SIG
100ms
&
&
&
100ms
SIG
CBx.79.Inprog
SIG
[CBx.79.CB_Healthy]
0ms
SIG
CBx.79.AR_Blkd
>=1
SIG
CBx.TRP.BlkAR
SIG
CBx.79.Fail_Rcls
SIG
CBx.79.Fail_Chk
SIG
EN
[CBx.79.En]
EN
[CBx.79.En_ExtCtrl]
SIG
CBx.79.En
SIG
CBx.79.Blk
[CBx.79.t_CBReady]
CBx.79.Ready
&
>=1
&
>=1
&
>=1
CBx.79.On
&
&
When a fault occurs under pole disagreement condition, blocking AR can be enabled or disabled.
The time delay [CBx.79.t_SecFault] is used to discriminate another fault which begins after 1-pole
AR initiated. AR will be blocked if another fault happens after this time delay if the logic setting
[CBx.79.En_PDF_Blk] is set as 1, and 3-pole AR will be initiated if [CBx.79.En_PDF_Blk] is set
as 1.
AR will be blocked immediately once the blocking condition of AR appears, but the blocking
condition of AR will drop off with a time delay [CBx.79.t_DDO_BlkAR] after blocking signal
disappears.
When one-shot and 1-pole AR is enabled, auto-reclosure will be blocked immediately if there are
binary inputs of multi-phase CB position is energized.
When any protection element operates to trip, the device will output a signal [CBx.79.Active] until
AR drop off (Reset Command). Any tripping signal can be from external protection device or
internal protection element.
AR function can be enabled by internal logic settings of AR mode or external signal via binary
inputs in addition to internal logic setting [CBx.79.En]. When logic setting [CBx.79.En_ExtCtrl] is
set as 1, AR enable are determined by external signal via binary inputs and logic settings. When
logic setting [CBx.79.En_ExtCtrl] set as 0, AR enable are determined only by logic settings.
3-249
3 Operation Theory
For one-shot reclosing, if 1-pole AR mode is selected, auto-reclosure will reset when there is
three-phase tripping signal or input signal of multi-phase open position.
SIG
CBx.79.On
SIG
CBx.79.Mode_3PAR
SIG
CBx.79.Ready
SIG
CBx.79.Trp
SIG
CBx.79.Trp3P
SIG
CBx.79.TrpA
SIG
CBx.79.TrpB
SIG
CBx.79.TrpC
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
Logic
CBx.79.Perm_Trp3P
CBx.79.Perm_Trp1P
When AR is enabled, the device will output the signal [CBx.79.Perm_Trp3P] if AR is not ready, or
AR mode is set as 3-Pole AR, or another fault occurs after the circuit breaker is open.
3.29.5.2 AR Initiation
AR mode can be selected by external signal via binary inputs or internal logic settings. If the logic
setting [CBx.79.SetOpt] set as 1, AR mode is determined by the internal logic settings. If the logic
settings [CBx.79.SetOpt] set as 0, AR mode is determined by the external inputs.
1.
AR can be initiated by tripping signal of line protection, and the tripping signal may be from internal
trip signal or external trip signal.
When selecting 1-pole AR or 1/3-pole AR, line single-phase fault will trigger 1-pole AR. When AR
is ready to reclosing (CBx.79.Ready=1) and the single-phase tripping command is received, this
single-phase tripping command will be kept in the device, and 1-pole AR will be initiated after the
single-phase tripping command drops off. The single-phase tripping command kept in the device
will be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is
shown in Figure 3.29-4.
3-250
3 Operation Theory
SIG
Reset Command
&
>=1
SIG
Single-phase Trip
&
&
SIG
CBx.79.Ready
1-pole AR Initiation
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
When selecting 3-pole AR or 1/3-pole AR, three-phase tripping will trigger 3-pole AR. When AR is
ready to reclosing (CBx.79.Ready=1) and the three-phase tripping command is received, this
three-phase tripping command will be kept in the device, and 3-pole AR will be initiated after the
three-phase tripping command drops off. The three-phase tripping command kept in the device will
be cleared after the completion of auto-reclosing sequence (Reset Command). Its logic is shown
in Figure 3.29-5.
SIG
Reset Command
&
>=1
SIG
Three-phase Trip
&
&
SIG
CBx.79.Ready
3-pole AR Initiation
SIG
CBx.79.Sel_3PAR
SIG
CBx.79.Sel_1P/3PAR
>=1
2.
AR initiated by CB state
A logic setting [CBx.79.En_CBInit] is available for selection that AR is initiated by CB state. Under
normal conditions, when AR is ready to reclosing (CBx.79.Ready=1), AR will be initiated if circuit
breaker is open and corresponding phase current is nil. AR initiated by CB state can be divided
into initiating 1-pole AR and 3-pole AR, their logics are shown in Figure 3.29-6 and Figure 3.29-7
respectively. Usually normally closed contact of circuit breaker is used to reflect CB state.
3-251
3 Operation Theory
SIG
Phase A open
SIG
Phase B open
>=1
&
&
SIG
Phase C open
EN
[CBx.79.En_CBInit]
SIG
CBx.79.Ready
SIG
CBx.79.Sel_1PAR
SIG
CBx.79.Sel_1P/3PAR
&
&
1-pole AR Initiation
>=1
SIG
Phase A open
SIG
Phase B open
SIG
Phase C open
EN
[CBx.79.En_CBInit]
&
&
&
3-pole AR Initiation
SIG
CBx.79.Ready
EN
[CBx.79.Sel_3PAR]
EN
[CBx.79.Sel_1P/3PAR]
>=1
3.29.5.3 AR Reclosing
After AR is initiated, the device will output the initiating contact of AR. For 1-pole AR, in order to
prevent pole discrepancy protection from maloperation under pole discrepancy conditions, the
contact of 1-pole AR initiation can be used to block pole discrepancy protection.
When the dead time delay of AR expires after AR is initiated, as for 1-pole AR, when the setting
[CBx.25.En_3PLvChk] is set as 0, the result of synchronism check will not be judged, and
reclosing command will be output directly. When the setting [CBx.25.En_3PLvChk] is set as 1,
the reclosing is not permissible unless live three-phase check is met. As far as the 3-pole AR, if the
synchronism check is enabled, the release of reclosing command shall be subject to the result of
synchronism check. After the dead time delay of AR expires, if the synchronism check is still
unsuccessful within the time delay [CBx.79.t_wait_Chk], the signal of synchronism check failure
(CBx.79.Fail_Syn) will be output and the AR will be blocked. If 3-pole AR with no-check is enabled,
the condition of synchronism check success (CBx.25.Ok_Chk) will always be established. And the
signal of synchronism check success (CBx.25.Ok_Chk) from the synchronism check logic can be
applied by auto-reclosing function inside the device or external auto-reclosure device.
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3 Operation Theory
CBx.79.Inprog_1P
SIG
1-pole AR Initiation
SIG
3-pole AR Initiation
>=1
CBx.79.Inprog
CBx.79.Inprog_3P
SIG
1-pole AR Initiation
[CBx.79.t_Dd_1PS1]
0ms
&
>=1
AR Pulse
&
SIG
CBx.79.Ok_3PLvChk
SIG
3-pole AR Initiation
[CBx.79.t_Dd_3PS1]
0ms
&
>=1
[CBx.79.t_Wait_Chk] 0ms
&
SIG
CBx.79.Fail_Chk
CBx.79.Ok_Chk
In the process of channel abnormality, an internal fault occurs on the transmission line, backup
protection at both ends of line will operate to trip the circuit breaker of each end. The operation
time of backup protection at both ends of the line is possibly non-accordant, whilst the time delay
of AR needs to consider the arc-extinguishing and insulation recovery ability for transient fault, so
the time delay of AR shall be considered comprehensively according to the operation time of the
device at both ends. When the communication channel of main protection is abnormal (input
signal [CBx.79.PLC_Lost] is energized), and the logic setting [CBx.79.En_AddDly] is set as 1,
then the dead time delay of AR shall be equal to the original dead time delay of AR plus the extra
time delay [CBx.79.t_AddDly], so as to ensure the recovery of insulation intensity of fault point
when reclosing after transient fault. This extra time delay [CBx.79.t_AddDly] is only valid for the
first shot AR.
>=1
SIG
SIG
CBx.79.PLC_Lost
SIG
CBx.79.Active
EN
[CBx.79.En_AddDly]
&
&
&
Extend AR time
Reclosing pulse length may be set through the setting [CBx.79.t_PW_AR]. For the circuit breaker
without anti-pump interlock, a logic setting [CBx.79.En_CutPulse] is available to control the
reclosing pulse. When this function is enabled, if the device operates to trip during reclosing, the
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3 Operation Theory
reclosing pulse will drop off immediately, so as to prevent multi-shot reclosing onto fault. After the
reclosing command is issued, AR will drop off with time delay [CBx.79.t_Reclaim], and can carry
out next reclosing.
SIG
SIG
WaitMasterValid
&
0ms
50ms
0ms
[CBx.79.t_PW_AR]
AR Pulse
SIG
Single-phase Trip
SIG
Three-phase Trip
EN
[CBx.79.En_CutPulse]
>=1
CBx.79.AR_Out
&
>=1
&
>=1
&
SIG
[CBx.79.t_Reclaim]
CBx.79.AR_Out
0ms
Reset Command
The reclaim timer defines a time from the issue of the reclosing command, after which the
reclosing function resets. Should a new trip occur during this time, it is treated as a continuation of
the first fault. The reclaim timer is started when the CB closing command is given.
SIG
1-pole AR Initiation
>=1
0ms
SIG
3-pole AR Initiation
SIG
CBx.79.Fail_Rcls
SET
[CBx.79.Opt_Priority]=High
[CBx.79.t_Fail]
>=1
&
CBx.79.WaitToSlave
If any protection element operates to trip when AR is enabled ([CBx.79.On]=1) and AR is not
ready ([CBx.79.Ready]=0), the device will output the signal (CBx.79.Fail_Rcls).
2.
For one-shot AR, if the tripping command is received again within reclaim time after the
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3 Operation Theory
For multi-shot AR, if the reclosing times are equal to the setting value of AR number and the
tripping command is received again after the last reclosing pulse is issued, the reclosing shall
be considered as unsuccessful.
4.
SET
[CBx.79.Opt_Priority]=Low
SIG
CBx.79.WaitMaster
SIG
CBx.79.On
SIG
CBx.79.Ready
SIG
SIG
SIG
CBx.79.Inprog
SIG
CBx.79.AR_Blkd
SIG
WaitMasterValid
&
WaitMaster Valid
&
&
>=1
0ms
200ms
>=1
CBx.79.Fail_Rcls
&
&
[CBx.79.t_WaitMaster]
0ms
>=1
&
SIG
AR Pulse
SIG
3 CB closed
EN
[CBx.79.En_FailCheck]
[CBx.79.t_Fail] 0ms
&
&
&
CBx.79.Succ_Rcls
0ms [CBx.79.t_Fail]
After unsuccessful AR is confirmed, AR will be blocked. AR will not enter into the ready state
unless the circuit breaker position drops off , and can only begin to enter into the ready state again
after the circuit breaker is closed.
3.29.5.5 Reclosing Numbers Control
The device may be set up into one-shot or multi-shot AR. Through the setting [CBx.79.N_Rcls],
the maximum number of reclosing attempts may be set up to 4 times. Generally, only one-shot AR
is selected. Some corresponding settings may be hidden if one-shot AR is selected.
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3 Operation Theory
1.
1-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1-pole AR mode, 1-pole AR will be
initiated only for single-phase fault and respective faulty phase selected, otherwise, AR will be
blocked. For single-phase transient fault on the line, line protection device will operate to trip and
1-pole AR is initiated. After the dead time delay for 1-pole AR is expired, the device will send
reclosing pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to
ready for the next reclosing. For permanent fault, the device will operate to trip again after the
reclosing is performed, and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1-pole AR mode, the
first reclosing is 1-pole AR, and the subsequent reclosing can only be 3-pole AR. For single-phase
transient fault on the line, line protection device will operate to trip and then 1-pole AR is initiated.
After the dead time delay of the first reclosing is expired, the device will send reclosing pulse, and
then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and then 3-pole AR is initiated. At this time, the time delay applies the setting [CBx.79.t_Dd_3PS2].
After the time delay is expired, if the reclosing condition is met, the device will send reclosing pulse.
The sequence is repeated until the reclosing is successful or the maximum permit reclosing
number [CBx.79.N_Rcls] is reached. If the first fault is multi-phase fault, the device operates to trip
three-phase and initiate 3-pole AR. At this time, the time delay applies the setting
[CBx.79.t_Dd_3PS1]. For the possible reclosing times of 3-pole AR in 1-pole AR mode, please
refer to Table 3.29-2.
2.
3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 3-pole AR mode, line protection
device will operate to trip when a transient fault occurs on the line and 3-pole AR will be initiated.
After the dead time delay for 3-pole AR is expired, the device will send reclosing pulse, and then
the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for the next
reclosing. For permanent fault, the device will operate to trip again after the reclosing is performed,
and the device will output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and 3-pole AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached.
3.
1/3-pole AR
[CBx.79.N_Rcls]=1 means one-shot reclosing. For one-shot 1/3-pole AR mode, line protection
device will operate to trip when a transient fault occurs on the line and 1-pole AR will be initiated
for single-phase fault and 3-pole AR will be initiated for multi-phase fault. After respective dead
time delay for AR is expired, the device will send reclosing pulse, and then the auto-reclosure will
3-256
3 Operation Theory
drop off after the time delay [CBx.79.t_Reclaim] to ready for the next reclosing. For permanent
fault, the device will operate to trip again after the reclosing is performed, and the device will
output the signal of reclosing failure [CBx.79.Fail_Rcls].
[CBx.79.N_Rcls]>1 means multi-shot reclosing. For multi-shot reclosing in 1/3-pole AR mode, line
protection device will operate to trip when a transient fault occurs on the line and AR will be
initiated. After the dead time delay of the first reclosing is expired, the device will send reclosing
pulse, and then the auto-reclosure will drop off after the time delay [CBx.79.t_Reclaim] to ready for
the next reclosing. For permanent fault, the device will operate to trip again after the reclosing is
performed, and then 3-pole AR is initiated after the tripping contact drops off. After the time delay
for AR is expired, the device will send reclosing pulse. The sequence is repeated until the
reclosing is successful or the maximum permit reclosing number [CBx.79.N_Rcls] is reached. For
the possible reclosing times of 3-pole AR in 1/3-pole AR mode, please refer to Table 3.29-2.
The table below shows the number of reclose attempts with respect to the settings and AR modes.
Table 3.29-2 Reclosing number
Setting Value
1-pole AR
3-pole AR
1/3-pole AR
N-1AR
N-3AR
N-1AR
N-3AR
N-1AR
N-3AR
Duplicated protection configurations are normally applied for UHV lines. If reclosing function is
integrated within line protections, the auto-reclosing function can be enabled in any or both of the
line protections without coordination.
If both sets of reclosing functions are enabled, when one of them first recloses onto a permanent
fault, the other will block the reclosing pulse according to the latest condition of the faulty phase.
For one-shot AR mode, if the current is detected in the faulty phase, AR will be blocked
immediately to prevent the circuit breaker from repetitive reclosing. For multi-shot AR mode, if the
current is detected in the faulty phase, the current reclosing pulse will be blocked and go into the
next reclosing pulse logic automatically. If the maximum permitted reclosing number
[CBx.79.N_Rcls] is reached, the auto-reclosure will drop off after the time delay
[CBx.79.t_Reclaim].
For one-shot or multi-shot AR, there is a corresponding reclosing counter at each stage. After
reclosing pulse is sent, the corresponding reclosing counter will plus 1 and the reclosing counter
may be cleared by the submenu Clear Counter. If the circuit breaker is reclosed by other
devices during AR initiation, the auto-reclosure will go into the next reclosing pulse logic.
3-257
3 Operation Theory
Fault
Trip
CB 52b
Open
[CBx.79.t_Reclaim]
CBx.79.t_Reclaim
CBx.79.Active
CBx.79.Inprog
[CBx.79.t_Dd_1PS1]
CBx.79.Inprog_1P
[CBx.79.t_Dd_1PS1]
CBx.79.Ok_Chk
AR Out
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P
CBx.79.Fail_Rcls
Time
Signal
Fault
Trip
52b
Open
Open
[CBx.79.t_Reclaim]
CBx.79.t_Reclaim
CBx.79.Active
CBx.79.Inprog
CBx.79.Inprog_1P
CBx.79.Inprog_3PS2
[CBx.79.t_Dd_1PS1]
[CBx.79.t_Dd_3PS2]
CBx.79.Ok_Chk
AR Out
[CBx.79.t_PW_AR]
[CBx.79.t_PW_AR]
CBx.79.Perm_Trp3P
CBx.79.Fail_Rcls
200ms
Time
3-258
3 Operation Theory
3.29.6 Settings
Table 3.29-3 Auto-reclosing settings
No.
Name
Range
Step
Unit
Remark
Maximum
CBx.79.N_Rcls
1~4
CBx.79.t_Dd_1PS1
0.000~600.000
0.001
CBx.79.t_Dd_3PS1
0.000~600.000
0.001
CBx.79.t_Dd_3PS2
0.000~600.000
0.001
CBx.79.t_Dd_3PS3
0.000~600.000
0.001
CBx.79.t_Dd_3PS4
0.000~600.000
0.001
CBx.79.t_CBClsd
0.000~600.000
0.001
number
of
reclosing
attempts
Dead time of first shot 1-pole
reclosing
Dead time of first shot 3-pole
reclosing
Dead time of second shot 3-pole
reclosing
Dead time of third shot 3-pole
reclosing
Dead time of fourth shot 3-pole
reclosing
Time delay of circuit breaker in
closed position before reclosing
Time delay to wait for CB healthy,
and begin to timing when the input
CBx.79.t_CBReady
0.000~600.000
0.001
signal
[79.CB_Healthy]
de-energized
and
if
it
is
is
not
CBx.79.t_Wait_Chk
0.000~600.000
0.001
10
CBx.79.t_Fail
0.000~600.000
0.001
change
to
conform
reclosing
successful
11
CBx.79.t_PW_AR
0.000~600.000
0.001
12
CBx.79.t_Reclaim
0.000~600.000
0.001
Reclaim time of AR
13
CBx.79.t_PersistTrp
0.000~600.000
0.001
14
CBx.79.t_DDO_BlkAR
0.000~600.000
0.001
when
blocking
signal
for
AR
15
CBx.79.t_AddDly
0.000~600.000
0.001
16
CBx.79.t_WaitMaster
0.000~600.000
0.001
17
CBx.79.t_SecFault
0.000~600.000
0.001
Additional
time
delay
for
auto-reclosing
Maximum wait time for reclosing
permissive signal from master AR
Time delay of discriminating another
fault, and begin to times after 1-pole
3-259
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
AR initiated, 3-pole AR will be
initiated if another fault happens
during this time delay. AR will be
blocked if another fault happens
after that.
Enabling/disabling
auto-reclosing
CBx.79.En_PDF_Blk
0 or 1
19
CBx.79.En_AddDly
auto-reclosing
0 or 1
0: disable
1: enable
Enabling/disabling adjust the length
20
CBx.79.En_CutPulse
of reclosing pulse
0 or 1
0: disable
1: enable
Enabling/disabling confirm whether
AR is successful by checking CB
21
CBx.79.En_FailCheck
0 or 1
state
0: disable
1: enable
Enabling/disabling auto-reclosing
22
CBx.79.En
0 or 1
0: disable
1: enable
Enabling/disabling AR by external
input signal besides logic setting
23
CBx.79.En_ExtCtrl
[79.En]
0 or 1
24
CBx.79.En_CBInit
0 or 1
0: disable
1: enable
Option of AR priority
None: single-breaker arrangement
25
CBx.79.Opt_Priority
None, High or
Low
arrangement
Low: slave AR of multi-breaker
arrangement
26
CBx.79.SetOpt
0 or 1
3-260
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
1: select AR mode by internal logic
settings
0: select AR mode by external input
signals
Enabling/disabling 1-pole AR mode
27
CBx.79.En_1PAR
0 or 1
0: disable
1: enable
Enabling/disabling 3-pole AR mode
28
CBx.79.En_3PAR
0 or 1
0: disable
1: enable
Enabling/disabling
29
CBx.79.En_1P/3PAR
1/3-pole
AR
mode
0 or 1
0: disable
1: enable
TT.Alm
TT.En
TT.Op
TT.Blk
TT.On
Input Signal
Description
TT.Init
TT.En
Transfer trip enabling input, it is triggered from binary input or programmable logic
3-261
3 Operation Theory
etc.
3
Transfer trip blocking input, it is triggered from binary input or programmable logic
TT.Blk
No.
etc.
Output Signal
Description
TT.Alm
TT.Op
TT.On
3.30.5 Logic
SIG
TT.En
SIG
TT.Blk
&
TT.On
4s
BI
[TT.Init]
SIG
TT.Alm
EN
[TT.En_FD_Ctrl]
SIG
FD.Pkp
BI
[TT.Init]
10s
TT.Alm
&
TT.Op
>=1
3.30.6 Settings
Table 3.30-2 Settings of transfer trip
No.
1
Name
TT.t_Op
TT.En_FD_Ctrl
Range
Step
Unit
0.000~600.000
0.001
Remark
Time delay of transfer trip
Transfer trip controlled by local fault detector
element
0: not controlled by local fault detector
element
1: controlled by local fault detector element
0 or 1
3 Operation Theory
settings, only the setting [En_Trp3P] will be added the prefix CBx. for circuit breaker
No.x, which means that both circuit breakers corresponding to the same line protection
can be set different trip mode.
CBx.TrpA
CBx.TRP.Blk
CBx.TrpB
CBx.TrpC
CBx.PrepTrp3P
CBx.Trp
CBx.Trp3P
CBx.BFI_A
CBx.BFI_B
CBx.BFI_C
CBx.BFI
CBx.Trp3P_PSFail
CBx.TRP.BlkAR
CBx.TRP.On
Input Signal
Description
Trip enabling input, it is triggered from binary input or programmable
CBx.TRP.En
logic etc.
Trip blocking input, it is triggered from binary input or programmable
CBx.TRP.Blk
logic etc.
A, phase B, phase C)
CBx.PrepTrp3P
3-263
3 Operation Theory
kind of faults.
5
No.
Output Signal
Description
CBx.TRP.On
CBx.TrpA
CBx.TrpB
CBx.TrpC
CBx.Trp
CBx.Trp3P
CBx.BFI_A
CBx.BFI_B
CBx.BFI_ C
10
CBx.BFI
11
CBx.Trp3P_PSFail
12
CBx.TRP.BlkAR
Blocking auto-reclosing
3.31.5 Logic
After tripping signal is issued, the tripping pulse will be kept as same as the setting [t_Dwell_Trp] at
least. When the time delay is expired, for phase-segregated tripping, the tripping signal will drop
off immediately if the faulty current of corresponding phase is less than 0.06In (In is secondary
rated current), otherwise the tripping signal will be always kept until the faulty current of
corresponding phase is less than 0.06In. For three-phase tripping, the tripping signal will drop off
immediately if three-phase currents are all less than 0.06In, otherwise the tripping signal will be
always kept until three-phase currents are all less than 0.06In.
3-264
3 Operation Theory
&
&
&
&
>=1
&
>=1
&
>=1
&
CBx.TRP.On
SIG CBx.TRP.Blk
&
>=1
>=1
&
EN
[CBX.En_3PTrp]
SIG CBx.Trp
SIG Line tripping element
&
&
&
&
>=1
>=1
CBx.Trp3P_PSFail
>=1
&
200ms
0ms
&
[t_Dwell_Trp]
&
[t_Dwell_Trp]
&
[t_Dwell_Trp]
&
CBx.TrpA
SIG Ia<0.06In
SIG CBx.TrpB
&
CBx.TrpB
SIG Ib<0.06In
SIG CBx.TrpC
&
CBx.TrpC
SIG Ic<0.06In
SIG
CBx.TrpA
SIG
CBx.TrpB
SIG
CBx.TrpC
>=1
CBx.Trp
3-265
3 Operation Theory
SIG
CBx.TrpA
SIG
CBx.TrpB
SIG
CBx.TrpC
>=1
CBx.Trp3P
>=1
&
CBx.BFI
&
CBx.BFI_A
SIG
CBx.TrpA
&
CBx.BFI_B
SIG
CBx.TrpB
&
CBx.BFI_C
SIG
CBx.TrpC
3-266
3 Operation Theory
SIG
85-1.Op_DEF
SIG
85-2.Op_DEF
EN
[85.DEF.En_BlkAR]
SIG
78.Op
SIG
Yx.ZP.Op
>=1
&
&
>=1
>=1
>=1
EN
[Yx.ZP.En_BlkAR]
SIG
Yx.ZG.Op
EN
[Yx.ZG.En_BlkAR]
SIG
50/51Pm.Op
EN
[50/51Pm.En_BlkAR]
SIG
50/51Gm.Op
EN
[50/51Gm.En_BlkAR]
SIG
50/51Qm.Op
EN
[50/51Qm.En_BlkAR]
SIG
50PVT.Op
SIG
50GVT.Op
SIG
46BC.Op
SIG
81O.OFx.Op
SIG
81U.UFx.Op
SIG
TT.Op
SIG
CBx.50BF.Op_t1
SIG
CBx.50BF.Op_t2
SIG
CBx.50DZ.Op
SIG
49-1.Op
SIG
49-2.Op
SIG
50STB.Op
SIG
32R2.Op
SIG
32R1.Op
SIG
CBx.62PD.Op
SIG
59Pz.Op
SIG
59Gz.Op
SIG
59Q.Op
SIG
27Pz.Op
EN
En_MPF_Blk_AR
SIG
Multi-phase fault
EN
En_3PF_Blk_AR
SIG
Three-phase fault
EN
En_PhSF_Blk_AR
SIG
SIG
21SOTF.Op
SIG
50PSOTF.Op
SIG
50GSOTF.Op
SIG
&
&
&
>=1
&
>=1
>=1
>=1
>=1
>=1
>=1
>=1
>=1
CBx.BlkAR
>=1
>=1
>=1
&
&
>=1
&
>=1
>=1
&
3 Operation Theory
3.31.6 Settings
Table 3.31-2 Settings of trip logic
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
En_MPF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling
En_3PF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling
3
En_PhSF_Blk_AR
auto-reclosing
blocked
0 or 1
0: disable
1: enable
Enabling/disabling three-phase tripping mode
4
CBx.En_Trp3P
0 or 1
0: disable
1: enable
The dwell time of tripping command, empirical
value is 0.04
t_Dwell_Trp
0.000~10.000
0.001
3-268
3 Operation Theory
2.
Only current protection functions are enabled and VT is not connected to the device.
VTS.En
VTNS
VTNS.En
VTS.Alm
VTS.Blk
VTNS.Alm
VTNS.Blk
VTS.MCB_VT
Input Signal
VTS.En
VTS.Blk
Description
VT supervision enabling input, it is triggered from binary input or programmable
logic etc.
VT supervision blocking input, it is triggered from binary input or programmable
3-269
3 Operation Theory
logic etc.
VT neutral point supervision enabling input, it is triggered from binary input or
VTNS.En
VTNS.Blk
VTS.MCB_VT
No.
Output Signal
Description
VTS.Alm
VTNS.Alm
3.32.5 Logic
&
SIG
FD.Pkp
SIG
79.Inprog
SIG
3U0>0.08Unn
SIG
U1<0.3Unn
EN
[VTS.En_LineVT]
SIG
52b_3P
EN
[VTS.En_Out_VT]
>=1
>=1
&
>=1
&
[VTS.t_DPU] [VTS.t_DDO]
BI
&
>=1
>=1
&
VTS.Alm
[VTS.MCB_VT]
EN
[VTS.En]
SIG
[VTS.En]
SIG
[VTS.Blk]
&
&
SIG
FD.Pkp
SIG
79.Inprog
>=1
If the signal [FD.Pkp] or [79.Inprog] operates,
then circuit of time delay will be interrupted.
OTH
U03>0.2Unn
&
>=1
[VTS.t_DPU]
EN
[VTS.En_Out_VT]
EN
[VTS.En]
SIG
[VTNS.En]
SIG
[VTNS.Blk]
[VTS.t_DDO]
&
VTNS.Alm
&
3-270
3 Operation Theory
Where:
Unn: rated phase-to-phase voltage
U03: third harmonic amplitude of neutral point residual voltage
If there is already a VTS alarm before FD operated, VTS will continue to block distance protection,
that is VTS will be latched when FD operates.
3.32.6 Settings
Table 3.32-2 VTS settings
No.
Name
Range
Step
Unit
Remark
VTS.t_DPU
0.200~100.000
0.001
VTS.t_DDO
0.200~100.000
0.001
VTS.En_Out_VT
0: disable
0 or 1
VTS.En_LineVT
0 or 1
1: line VT
0: busbar VT
Alarm function of VT circuit supervision
VTS.En
0 or 1
1: enable
0: disable
3 Operation Theory
CBx.CTS.Alm
CBx.CTS.Blk
Input Signal
CBx.CTS.En
CBx.CTS.Blk
No.
1
Description
CT circuit supervision enabling input, it is triggered from binary input or
programmable logic etc.
CT circuit supervision blocking input, it is triggered from binary input or
programmable logic etc.
Output Signal
CBx.CTS.Alm
Description
Alarm signal to indicate CT circuit fails
3.33.5 Logic
SIG
CBx.CTS.En
SIG
CBx.CTS.Blk
SIG
3I0>0.1In
SIG
3U0<3V
SIG
IA<0.06In
SIG
IB<0.06In
SIG
IC<0.06In
&
&
10s
10s
CBx.CTS.Alm
&
>=1
3 Operation Theory
PCS-Explorer.
NOTICE!
For double circuit breakers mode, the device will provide independent control and
synchrocheck function of manual closing for CB1 and CB2 respectively. Both control
and synchrocheck for manual closing functions have the same logic.The difference is
that the prefix CBx. is added to all signals and settings for circuit breaker No.x (x=1 or
2).
3-273
3 Operation Theory
EN
[MCBrd.CBx.25.En_SynChk]
MCBrd.CBx.25.On_SynChk
SIG
MCBrd.CBx.25.Sel_SynChk
EN
[MCBrd.CBx.25.SetOpt]
EN
[MCBrd.CBx.25.En_NoChk]
SIG
MCBrd.CBx.25.Sel_NoChk
EN
[MCBrd.CBx.25.SetOpt]
1
MCBrd.CBx.25.On_NoChk
0
SIG CSWI01.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI01.En_Cls_Blk]
SIG CSWI01.CILO.EnCls
SIG CSWI01.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
&
[CSWI01.t_PW_Cls]
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl
0ms
CSWI01.Op_Cls
>=1
&
SIG BIinput.LocCtrl
SIG CSWI01.ManSynCls
>=1
SIG CSWI01.Cmd_LocCtrl
SIG MCBrd.CB1.25.On_SynChk
>=1
SIG MCBrd.CB1.25.Ok_Chk
SIG MCBrd.CB1.Alm_VTS
&
&
&
EN
[MCBrd.CB1.En_Alm_VTS]
EN
[MCBrd.CB1.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB1.En_Alm_VTS]
&
&
SIG MCBrd.CB1.Alm_VTS
EN
[MCBrd.CB1.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB1.25.En_LvL_DdB]
EN
[MCBrd.CB1.25.En_DdL_LvB]
EN
[MCBrd.CB1.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB1.25.Ok_Chk
SIG MCBrd.CB1.25.On_NoChk
3 Operation Theory
SIG CSWI02.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI02.En_Cls_Blk]
SIG CSWI02.CILO.EnCls
SIG CSWI02.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
&
[CSWI02.t_PW_Cls]
SIG CSWI02.Cmd_RmtCtrl
SIG CSWI02.LocCtrl
0ms
CSWI02.Op_Cls
>=1
&
SIG BIinput.LocCtrl
SIG CSWI02.ManSynCls
>=1
SIG CSWI02.Cmd_LocCtrl
SIG MCBrd.CB2.25.On_SynChk
>=1
SIG MCBrd.CB2.25.Ok_Chk
SIG MCBrd.CB2.Alm_VTS
&
&
&
EN
[MCBrd.CB2.En_Alm_VTS]
EN
[MCBrd.CB2.25.En_VTS_Blk_SynChk]
EN
[MCBrd.CB2.En_Alm_VTS]
&
&
SIG MCBrd.CB2.Alm_VTS
EN
[MCBrd.CB2.25.En_VTS_Blk_DdChk]
EN
[MCBrd.CB2.25.En_LvL_DdB]
EN
[MCBrd.CB2.25.En_DdL_LvB]
EN
[MCBrd.CB2.25.En_DdL_DdB]
>=1
&
>=1
>=1
SIG MCBrd.CB2.25.Ok_Chk
SIG MCBrd.CB2.25.On_NoChk
As shown in Figure 3.34-3, for double circuit breakers application, both the first closing command
CSWI01.Op_Cls and the second closing command CSWI02.Op_Cls, which are controlled by
synchrocheck logic, can be used for CB closing, otherwise, the logic of the second closing
command CSWI02.Op_Cls should comply with Figure 3.34-4.
After receiving a closing command, this device will continuously check whether the 2 voltages
(Incoming voltage and reference voltage) involved in synchronism check (or dead check) can meet
the criteria. Within the duration of [MCBrd.CBx.25.t_Wait_Chk], if the synchronism check (or dead
check) criteria are not met, the signal MCBrd.CBx.25.Ok_Chk will be set as 0; if the
synchronism check (or dead check) criteria are met, the signal MCBrd.CBx.25.Ok_Chk will be
set as 1.
3-275
3 Operation Theory
When any of the following criteria is fulfilled, an alarm signal [MCBrd.CBx.Alm_VTS] will be issued
with a time delay of 1.25s, and drop off with a time delay of 10s after three phases voltage restored
to normal. The alarm signal will block the closing command for circuit breaker.
1.
2.
The positive-sequence voltage is smaller than 30V, and any phase current is greater than
0.04In.
SIG
CSWIxx.CILO.Disable
SIG
BIinput.CILO.Disable
EN
[CSWIxx.En_Cls_Blk]
SIG
CSWIxx.CILO.EnCls
SIG
CSWIxx.RmtCtrl
SIG
BIinput.RmtCtrl
SIG
CSWIxx.Cmd_RmtCtrl
SIG
CSWIxx.LocCtrl
SIG
BIinput.LocCtrl
SIG
CSWIxx.Cmd_LocCtrl
>=1
>=1
&
[CSWIxx.t_PW_Cls]
0ms
[CSWIxx.Op_Cls]
>=1
&
>=1
>=1
&
Access the menu Local CmdControl to issue control command locally, and this signal
CSWIxx.Cmd_LocCtrl will be set as 1. Remote control commands from SCADA/CC can be
transmitted via IEC 60870-5-103 protocol or IEC 61850 protocol, and this signal
CSWIxx.Cmd_RmtCtrl will be set as 1.
SIG CSWI01.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI01.En_Opn_Blk]
&
[CSWI01.t_PW_Opn]
SIG CSWI01.CILO.EnOpn
SIG CSWI01.RmtCtrl
0ms
CSWI01.Op_Opn
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWI01.Cmd_RmtCtrl
SIG CSWI01.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWI01.ManOpn
>=1
SIG CSWI01.Cmd_LocCtrl
3-276
3 Operation Theory
SIG CSWI02.CILO.Disable
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWI02.En_Opn_Blk]
&
[CSWI02.t_PW_Opn]
0ms
CSWI02.Op_Opn
0ms
CSWIxx.Op_Opn
SIG CSWI02.CILO.EnOpn
SIG CSWI02.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWI02.Cmd_RmtCtrl
SIG CSWI02.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWI02.ManOpn
>=1
SIG CSWI02.Cmd_LocCtrl
>=1
SIG BIinput.CILO.Disable
>=1
EN
[CSWIxx.En_Opn_Blk]
&
[CSWIxx.t_PW_Opn]
SIG CSWIxx.CILO.EnOpn
SIG CSWIxx.RmtCtrl
>=1
&
SIG BIinput.RmtCtrl
>=1
SIG CSWIxx.Cmd_RmtCtrl
SIG CSWIxx.LocCtrl
>=1
&
SIG BIinput.LocCtrl
SIG CSWIxx.Cmd_LocCtrl
The control output fulfills signal output circuit, and opens or closes circuit breaker, disconnector
and earth switch according to the control command. Object manipulation strictly performs three
steps: selection, check and excute, and perform output relay check, to ensure that the remote
control can be excuted safely and reliably.
When logic interlock is enabled, the device can receive the programmable interlock logic. The
device can automatically initiate the interlock logic to determine whether to allow control
operations. The device provides corresponding settings ([CSWIxx.En_Opn_Blk] and
[CSWIxx.En_Cls_Blk]) for each control object. When they are set as 1, the interlock function of
the corresponding control object is enabled. The interlock logic can be configured by using
3-277
3 Operation Theory
PCS-Explorer, and downloaded to the device via the Ethernet port. If the interlock function is
enabled, but it is not configured the interlock logic, the result of the logic output is 0.
The control record is a file which is used to store remote control command records of this device
circularly. If the record number is to 256, the storage area of the control record will be full. If this
device has received a new remote command, this device will delete the oldest remote control
record, and then store the latest remote control record.
There are 10 configuration pages corresponding to 10 control outputs in totall respectively. Each
configuration page can finish some signals configuration, including remote control, local control,
disable interlock blocking, and so on.
In order to conveniently configure control output, the same output signals, including
BIinput.RmtCtrl, BIinput.LocCtrl and BIinput.CILO.Disable, are available after processing
binary signals internally, as shown in figure below.
3-278
3 Operation Theory
Remot
Local
CSWIxx.
BIinput.
CSWIxx.
BIinput.
RmtCtrl
RmtCtrl
LocCtrl
LocCtrl
Control Mode
For remote control or local control, they can be configured by either of CSWIxx.RmtCtrl and
BIinput.RmtCtrl, or either of CSWIxx.LocCtrl and BIinput.LocCtrl.
2. Synchrocheck
Three synchrocheck modes are designed for CB closing: no check mode, dead check mode and
synchronism check mode, if any one of the condition of three synchrocheck modes satisfied, then
synchrocheck signal MCBrd.CBx.25.Ok_Chk will be asserted.
The synchronism check function measures the conditions across the circuit breaker and compares
them with the corresponding settings. The output is only given if all measured quantities are
simultaneously within their set limits. Compared to the synchronism check for auto-reclosing, an
additional criterion is applied to check the rate of frequency change (df/dt) between both sides of
the CB.
When the following four conditions are all met, the synchronism check is successful.
3-279
3 Operation Theory
1) Phase angle difference between incoming voltage and reference voltage is less than the
setting [MCBrd.CBx.25.phi_Diff]
2) Frequency difference between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.f_Diff]
3) Voltage difference between between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.U_Diff]
4) Rate of frequency change between incoming voltage and reference voltage is less than
[MCBrd.CBx.25.df/dt]
The dead check function measures the amplitude of line voltage and bus voltage at both sides of
the circuit breaker, and then compare them with the live check setting [MCBrd.CBx.25.U_Lv] and
the dead check setting [MCBrd.CBx.25.U_Dd]. The dead check is successful when the measured
quantities comply with the criteria.
When this device is set to work in no check mode and receives a closing command, CB will be
closed without synchronism check and dead check.
Synchrocheck for manual closing also supports voltage switching. In general, voltage switching is
fulfilled by external circuit ([CBx.CBConfigMode]=NoVoltSel). If using this module to fulfill voltage
switching, the busbar arrangement should be determined by the setting [CBx.CBConfigMode],
including:
Analog input defines four voltage inputs, UL1, UB1, UL2, UB2, and their usage are as follow:
UL1: it connects with three-phase protection voltages (from line or busbar), which mainly are used
by distance protection, voltage protection and so on. According to the voltage switching result,
synchrocheck logic choose one voltage to be used for synchrocheck function, synchrocheck
function requires to judgment the phase identification information of the voltage, which is
determined by the setting [MCBrd.CBx.25.Opt_Source_UL1]. If voltage switching function is not
used, the reference voltage will be selected from UL1 fixedly.
UB1: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UB1]. If voltage switching function is not used, UB1 will be taken as
the synchronism voltage.
UL2: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UL2]. When voltage switching is available, it is only available for 1
breakers arrangement, it is fixedly connected to the voltage of the other line of the same diameter
in 1 breakers arrangement.
3-280
3 Operation Theory
UB2: according to the voltage switching result, synchrocheck logic determined whether the voltage
is used for synchrocheck function. Synchrocheck function requires to judgment the phase
identification information of the voltage, which is determined by the setting
[MCBrd.CBx.25.Opt_Source_UB2]. When voltage switching is available, it is connected to
synchronism voltage for double busbars arrangement or 1 breakers arrangement.
Synchrocheck for manual closing supports voltage switching function, and the switching logic is as
same as that of synchrocheck for protection closing. The setting [CBx.CBConfigMode] should be
set according to the actual primary busbar arrangement, otherwise, the voltage switching of
synchrocheck for manual closing will fail, so as to block manual closing with synchrocheck.
During dead charge check, when only single-phase voltage is connected to UL1, live voltage is
valid if the setting [VTS.En] should be set as 0 and the connected single-phase voltage is higher
than the setting [MCBrd.CBx.25.U_Lv], otherwise, live voltage is regarded as live only when three
phases voltages are all higher than [MCBrd.CBx.25.U_Lv].
CSWI01.Op_Opn
CSWI01.CILO.EnCls
CSWI01.Op_Cls
CSWI01.RmtCtrl
CSWI01.LocCtrl
CSWI01.CILO.Disable
CSWI02
CSWI02.CILO.EnOpn
CSWI02.Op_Opn
CSWI02.CILO.EnCls
CSWI02.Op_Cls
CSWI02.RmtCtrl
CSWI02.LocCtrl
CSWI02.CILO.Disable
CSWIxx
CSWIxx.CILO.EnOpn
CSWIxx.Op_Opn
CSWIxx.CILO.EnCls
CSWIxx.Op_Cls
CSWIxx.RmtCtrl
CSWIxx.LocCtrl
CSWIxx.CILO.Disable
3-281
3 Operation Theory
BIinput
BIinput.RmtCtrl
BIinput.RmtCtrl
BIinput.LocCtrl
BIinput.LocCtrl
BIinput.CILO.Disable
BIinput.CILO.Disable
CSWI01.ManSynCls
CSWI01.ManOpn
CSWI02.ManSynCls
CSWI02.ManOpn
xx can be from 02 or 03 to 10
Input Signal
Description
From receiving a closing command, this device will continuously check
whether the 2 voltages (Incoming voltage and reference voltage)
involved in synchronism check(or dead check) can meet the criteria.
MCBrd.CBx.25.Ok_Chk
CSWIxx.CILO.EnOpn
CSWIxx.CILO.EnCls
CSWIxx.LocCtrl
(CB/DS/ES). When the local control is active, No.xx binary outputs can
only be locally controlled. (xx=01~10)
It is used to select the remote control to No.xx controlled object
CSWIxx.RmtCtrl
CSWIxx.CILO.Disable
BIinput.RmtCtrl
When the remote control is active, all binary outputs can only be
remotely controlled by SCADA or control centers.
BIinput.LocCtrl
3-282
3 Operation Theory
controlled.
It is used to disable the interlock blocking function for control output. If
9
BIinput.CILO.Disable
CSWI01.ManSynCls
CSWI01.ManOpn
CSWI02.ManSynCls
13
CSWI02.ManOpn
to execute manually open the circuit breaker. (for double circuit breakers
application)
14
MCBrd.CBx.25.Sel_SynChk
15
MCBrd.CBx.25.Sel_NoChk
No.
Output Signal
Description
CSWIxx.Op_Opn
CSWIxx.Op_Cls
BIinput.RmtCtrl
BIinput.LocCtrl
output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can
BIinput.CILO.Disable
MCBrd.CBx.Alm_VTS
3.34.5 Settings
Table 3.34-2 Control settings
No.
Name
Range
Step
Unit
Remark
No.xx holding time of a normal open contact
CSWIxx.t_PW_Opn
0~65535
ms
CSWIxx.t_PW_Cls
0~65535
ms
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
These settings are applied to configure the
CSWIxx.t_DPU_DPS
0~60000
ms
CSWIxx.En_Opn_Blk
logic
0 or 1
0: disable
1: enable
(xx=01, 02.10)
Enabling/disabling No.xx closing output of the
BO module be controlled by the interlocking
5
CSWIxx.En_Cls_Blk
logic
0 or 1
0: disable
1: enable
(xx=01, 02.10)
Table 3.34-3 Synchrocheck settings
No.
Name
Range
Step
Unit
Remark
Enabling/disabling
alarm
MCBrd.CBx.En_Alm_VTS
0 or 1
abnormal
0: disable
1: enable
Name
Range
Step
Unit
Remark
Voltage selecting mode of
MCBrd.CBx.25.Opt_Source_UL1
Ua
line 1
Ub
Uc
Uab
Ubc
Uca
MCBrd.CBx.25.Opt_Source_UB1
Ua
bus 1
Ub
Uc
Uab
Ubc
Uca
MCBrd.CBx.25.Opt_Source_UL2
Ua
3-284
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
Ub
line 2
Uc
Uab
Ubc
Uca
MCBrd.CBx.25.Opt_Source_UB2
Ua
bus 2
Ub
Uc
Uab
Ubc
Uca
MCBrd.CBx.25.U_Dd
0.05Un~0.8Un
0.001
MCBrd.CBx.25.U_Lv
0.5Un~Un
0.001
of
live
MCBrd.CBx.25.K_Usyn
0.20-5.00
synchronism
voltage
for
manual closing
Phase difference limit
8
MCBrd.CBx.25.phi_Diff
0~ 89
deg
synchronism
check
of
for
manual closing
Compensation
9
MCBrd.CBx.25.phi_Comp
0~359
difference
of
phase
between
synchronous
two
voltages
for
manual closing
Frequency difference limit of
10
MCBrd.CBx.25.f_Diff
0.02~1.00
0.01
Hz
synchronism
check
for
manual closing
Voltage difference limit of
11
MCBrd.CBx.25.U_Diff
0.02Un~0.8Un
0.01
synchronism
check
for
manual closing
Synchrocheck
mode
MCBrd.CBx.25.SetOpt
0, 1
0: determined by external
signal
1: determined by the setting
Enabling/disabling
13
MCBrd.CBx.25.En_SynChk
0 or 1
synchronism
check
for
manual clsoing
3-285
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
0: disable
1: enable
Enabling/disabling dead line
and dead bus (DLDB) check
14
MCBrd.CBx.25.En_DdL_DdB
0 or 1
15
MCBrd.CBx.25.En_DdL_LvB
0 or 1
16
MCBrd.CBx.25.En_LvL_DdB
0 or 1
17
MCBrd.CBx.25.En_NoChk
manual
0 or 1
0: disable
1: enable
Threshold
of
rate
of
MCBrd.CBx.25.df/dt
0.00~3.00
0.01
Hz/s
both
sides
synchronism
of
CB
for
check
of
manual closing
Circuit breaker closing time
for manual closing
19
MCBrd.CBx.25.t_Close_CB
20~1000
ms
20
MCBrd.CBx.25.t_Wait_Chk
5~30
0.001
reference
involved
in
voltage
synchronism
3-286
3 Operation Theory
No.
Name
Range
Step
Unit
Remark
synchronism-check (or dead
check) will be confirmed.
Enabling/disabling
synchronism
21
MCBrd.CBx.25.En_VTS_Blk_SynChk
0 or 1
block
check
for
22
MCBrd.CBx.25.En_VTS_Blk_DdChk
0 or 1
check
for
block
manual
2.
The logic makes the device ideal for single-phase tripping applications.
1)
Phase A: UOPA
2)
Phase B: UOPB
3)
Phase C: UOPC
2.
1)
2)
3)
3 Operation Theory
Fault phase
UOPA
Phase A
UOPB
Phase B
UOPC
Phase C
UOPAB
Phase AB
UOPBC
Phase BC
UOPCA
Phase CA
Region A
60
-60
Region B
Region C
180
Depended on the phase relation between I0 and I2A, the faulty phase can be determined.
1.
2.
3.
For single-phase earth fault, I0 and I2 of faulty phase are in-phase and its distance element
operates.
For phase to phase to earth fault, I0 and I2 of non-faulty phase are in-phase but its distance
element does not operate.
3-288
3 Operation Theory
Output Signal
Description
PhSA
PhSB
PhSC
GndFlt
Earth fault
Where:
Dist: The distance of fault location according to the Zcalc (km)
3-289
3 Operation Theory
Zcalc: The impedance value calculated from the location of protection device to fault point
Zl: The impedance value of the whole line + mutual impedance
Length: The input length of transmission line (km)
3.36.2.2 Mutual Compensation
When an earth fault occurred on a line of parallel lines arrangement, a distance relay at one end of
the faulty line will tend to underreach whilst the distance relay at the other end will tend to
overreach. Usually the degree of underreach or overreach is acceptable, however, for cases
where precise fault location is required for long lines with high mutual coupling, mutual
compensation is then required to improve the distance measurement. Practically, the mutual effect
between the parallel lines is insignificant to positive and negative sequence and thus the mutual
compensation is only for zero sequence
A
Ia
ZM
k
C
Ic
ZS
D
(1-k)ZL
kZL
ZL
The principle in the application of mutual compensation is shown as follows with the aid of
following sequence network diagram figure. The diagram indicates a parallel lines arrangement
with an earth fault at location k on line CD.
The equivalent sequence network for an earth fault on a parallel lines arrangement with single
source is shown as below.
Ia1
ZL1
ZS1
kZL1
(1-k)ZL1
Ic1
Ia2
ZL2
ZS2
kZL2
(1-k)ZL2
Ic2
Ia0
ZL0
ZS0
Z0M
kZL0
(1-k)ZL0
Ic0
3-290
3 Operation Theory
The device at location C without mutual compensation will have voltage U RC and current IRC
measured as shown in the expression
URC is the voltage of the device at location C.
3-291
3 Operation Theory
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
Fault_Location
Fault_Phase
Fault_Phase_Curr
Fault_Resid_Curr
3-292
3 Operation Theory
Input Signal
Description
FPS_Fault
FD.Pkp
No.
Output Signal
Description
Fault_Location
Faulty_Phase
Fault_Phase_Curr
Fault_Resid_Curr
3-293
3 Operation Theory
3-294
4 Supervision
4 Supervision
Table of Contents
4 Supervision ........................................................................................ 4-a
4.1 Overview .......................................................................................................... 4-1
4.2 Supervision Alarms ......................................................................................... 4-1
4.3 Relay Self-supervision.................................................................................... 4-8
4.3.1 Relay Hardware Monitoring ................................................................................................. 4-8
4.3.2 Fault Detector Monitoring .................................................................................................... 4-8
4.3.3 Check Setting ...................................................................................................................... 4-8
List of Tables
Table 4.2-1 Alarm description..................................................................................................... 4-1
Table 4.2-2 Troubleshooting ....................................................................................................... 4-5
4-a
Date: 2015-10-23
4 Supervision
4-b
4 Supervision
4.1 Overview
Protection system is in quiescent state under normal conditions, and it is required to respond
promptly for faults occurred on power system. When the device is in energizing process before the
LED HEALTHY is on, the device need to be checked to ensure no abnormality. Therefore, the
automatic supervision function, which checks the health of the protection system when startup and
during normal operation, plays an important role.
The numerical relay based on the microprocessor operations is suitable for implementing this
automatic supervision function of the protection system.
In case a defect is detected during initialization when DC power supply is provided to the device,
the device will be blocked with indication and alarm of relay out of service. It is suggested a trial
recovery of the device by re-energization. Please contact supplier if the device is still failure.
When a failure is detected by the automatic supervision, it is followed by a LCD message, LED
indication and alarm contact outputs. The failure alarm is also recorded in event recording report
and can be printed If required.
Item
Description
Blocking Device
Fail Signals
The device fails.
1
Fail_Device
Blocked
Fail_Setting_OvRange
Blocked
4-1
Date: 2015-10-23
4 Supervision
latched unless the recommended handling suggestion is
adopted.
3
Fail_BoardConfig
Blocked
Fail_SettingItem_Chgd
Blocked
Fail_Memory
Blocked
adopted.
Error is found during checking settings.
6
Fail_Settings
Blocked
adopted.
DSP chip is damaged.
7
Fail_DSP
Blocked
adopted.
Communication between two DSP chips is abnormal
8
Fail_DSP_Comm
Blocked
instantaneously.
Software configuation is incorrect.
9
Fail_Config
Blocked
adopted.
AC current and voltage samplings are abnormal.
10
Fail_Sample
Blocked
suggestion is adopted.
11
MCBrd.Fail_Sample
12
MCBrd.Fail_Settings
Blocked
Blocked
Alarm Signals
The device is abnormal.
13
Alm_Device
Unblocked
and it will drop off when all alarm signals drop off.
14
Alm_Insuf_Memory
Unblocked
Alm_CommTest
Unblocked
instantaneously.
4-2
4 Supervision
The error is found during MON module checking
16
Alm_Settings_MON
settings of device.
This signal will pick up with a time delay of 10s and will
Unblocked
Alm_Version
Unblocked
instantaneously.
The active group set by settings in device and that set
18
Alm_BI_SettingGrp
Unblocked
instantaneously.
Data frame is abnormal between two DSP modules.
19
Alm_DSP_Frame
Unblocked
instantaneously.
The power supply of BI plug-in module in slot xx is
20
Bxx.Alm_OptoDC
abnormal.
This signal will pick up with a time delay of 10s and will
Unblocked
Alm_Pkp_FD
This signal will pick up with a time delay of 50s and will
Unblocked
Alm_Pkp_I0
Unblocked
VTS.Alm
Unblocked
VTNS.Alm
Unblocked
MCBrd.CBx.Alm_VTS
This signal will pick up with a time delay of 1.25s and will
Unblocked
CBx.CTS.Alm
This signal will pick up with a time delay of 10s and will
Unblocked
CBx.Alm_52b
auxiliary
normally
closed
contact
(52b)
of
Unblocked
BI_Maintenance
Unblocked
4-3
Date: 2015-10-23
4 Supervision
will drop off with a time delay of 150ms.
29
Alm_TimeSyn
Unblocked
30
Alm_Freq
than 45Hz.
This signal will pick up with a time delay of 100ms and
Unblocked
31
Alm_Sparexx
(xx=01~08)
Unblocked
32
FOx.Alm
Unblocked
FOx.Alm_ID
Unblocked
FOx.Alm_NoValFram
Unblocked
FOx.Alm_CRC
Unblocked
FOx.Alm_Off
Unblocked
instantaneously.
Optical fibre of channel x is connected wrongly.
37
FOx.Alm_Connect
Unblocked
38
50/51Q4.Alm
39
27P1.Alm
Unblocked
40
27P2.Alm
Unblocked
41
27P3.Alm
Unblocked
42
59P1.Alm
Unblocked
43
59P2.Alm
Unblocked
44
59P3.Alm
Unblocked
45
59G3.Alm
46
49-1.Alm
operates to alarm.
4-4
Unblocked
Unblocked
Unblocked
4 Supervision
47
49-2.Alm
alarm.
Unblocked
87STB.Alm_Diff
Unblocked
87STB.Alm_89b_DS
Unblocked
46BC.Alm
51
CBx.Alm_Invalid_Sel
Unblocked
Unblocked
CBx.25.Alm_VTS_Usyn
Unblocked
CBx.25.Alm_VTS_Uref
Unblocked
CBx.79.Fail_Rcls
55
CBx.79.Fail_Chk
Unblocked
Unblocked
TT.Alm
Unblocked
10s.
Table 4.2-2 Troubleshooting
No.
Item
Handling suggestion
Fail Signals
Fail_Device
The signal is issued with other specific fail signals, and please refer to the
handling suggestion other specific alarm signals.
Please reset setting values according to the range described in the instruction
Fail_Setting_OvRange
manual, then re-power or reboot the device and the device will restore to
normal operation state.
1. Go to the menu InformationBorad Info, check the abnormality
information.
Fail_BoardConfig
2. For the abnormality board, if the board is not used, then remove, and if the
board is used, then check whether the board is installed properly and work
normally.
Please check the settings mentioned in the prompt message on the LCD, and
Fail_SettingItem_Chgd
Fail_Memory
4-5
Date: 2015-10-23
4 Supervision
6
Fail_Settings
Fail_DSP
Fail_DSP_Comm
Fail_Config
10
Fail_Sample
2. Then check if the analog input modules and wiring connectors connected to
those modules are installed at the position.
3. Re-power the device and the device will restore to normal operation state.
1. Please make the device out of service.
11
MCBrd.Fail_Sample
12
MCBrd.Fail_Settings
13
Alm_Device
14
Alm_Insuf_Memory
15
Alm_CommTest
16
Alm_Settings_MON
The signal is issued with other specific alarm signals, and please refer to the
handling suggestion other specific alarm signals.
Please replace MON plug-in module.
No special treatment is needed, and disable the communication test function
after the completion of the test.
Please inform the manufacture or the agent for repair.
Users may pay no attention to the alarm signal in the project commissioning
stage, but it is needed to download the latest package file (including correct
17
Alm_Version
version checksum file) provided by R&D engineer to make the alarm signal
disappear. Then users get the correct software version. It is not allowed that
the alarm signal is issued on the device already has been put into service. the
devices having being put into service so that the alarm signal disappears.
Please check the value of setting [Active_Grp] and binary input of indiating
18
Alm_BI_SettingGrp
active group, and make them matched. Then the ALARM LED will be
extinguished and the corresponding alarm message will disappear and the
device will restore to normal operation state.
19
Alm_DSP_Frame
20
Bxx.Alm_OptoDC
3. After the voltage for binary input module restores to normal range, the
ALARM LED will be extinguished and the corresponding alarm message will
disappear and the device will restore to normal operation state.
Please check secondary values and protection settings. If settings are not set
21
Alm_Pkp_FD
reasonable to make fault detectors pick up, please reset settings, and then
the alarm message will disappear and the device will restore to normal
operation state.
22
Alm_Pkp_I0
Please check secondary values and protection settings. If settings are not set
reasonable to make fault detectors pick up, please reset settings, and then
4-6
4 Supervision
the alarm message will disappear and the device will restore to normal
operation state.
23
VTS.Alm
24
VTNS.Alm
25
MCBrd.CBx.Alm_VTS
26
CBx.CTS.Alm
27
CBx.Alm_52b
28
BI_Maintenance
[BI_Maintenance] and then the alarm will disappear and the device restore to
normal operation state.
1. check whether the selected clock synchronization mode matches the clock
synchronization source;
2. check whether the wiring connection between the device and the clock
synchronization source is correct
29
Alm_TimeSyn
30
31
Alm_Freq
Alm_Sparexx
(xx=01~08)
user-defined.)
Operation Alarm Signals
32
FOx.Alm
33
FOx.Alm_ID
34
FOx.Alm_NoValFram
35
FOx.Alm_CRC
36
FOx.Alm_Off
37
FOx.Alm_Connect
Please check the conncetion of optical fibre channel. (For example, receiving
and sending are inconsistent, or channel 1 and channel 2 are inconsistent)
Please check the corresponding current circuit. After the abnormality is
38
87STB.Alm_Diff
39
87STB.Alm_89b_DS
4-7
Date: 2015-10-23
4 Supervision
Please check the corresponding binary input secondary circuit. After the
40
TT.Alm
4 Supervision
detected in the line (the measured current is greater than a settable threshold value) or
three-phase circuit breaker is in pole disagreement, an alarm signal [Alm_52b] will be issued after
10 seconds.
4-9
Date: 2015-10-23
4 Supervision
4-10
5 Management
5 Management
Table of Contents
5 Management ...................................................................................... 5-a
5.1 Measurement ................................................................................................... 5-1
5.1.1 Measurement Values ........................................................................................................... 5-1
5.1.2 Metering Value ..................................................................................................................... 5-5
5-a
Date: 2015-05-23
5 Management
5-b
5 Management
5.1 Measurement
PCS-931 performs continuous measurement of the analogue input quantities. The current full
scale of relay is 40 times of rated current, and there is no effect to the performance of IED due to
overflowing of current full scale. The device samples 24 points per cycle and calculates the RMS
value in each interval and updated the LCD display in every 0.5 second. The measurement data
can be displayed on the LCD of the relay front panel or on the local/remote PC via software tool.
Navigate the menu to view the sampling value through LCD screen.
NOTICE!
This device can be configured to support single circuit breaker application or double circuit
breakers application by PCS-Explorer. For double circuit breakers mode, the prefix CBx.
is added to related measurement quantities for circuit breaker No.x (x=1 or 2).
Symbol
Definition
Resolution
Unit
CBx.Ia
0.000
CBx.Ib
0.000
CBx.Ic
0.000
CBx.3I0
0.000
Ia
0.000
Ib
0.000
Ic
0.000
I1
0.000
I2
0.000
10
3I0
0.000
11
3I0Adj
0.000
12
Ua
0.000
13
Ub
0.000
14
Uc
0.000
5-1
Date: 2015-05-23
5 Management
15
Uab
0.000
16
Ubc
0.000
17
Uca
0.000
18
UB1
0.000
19
UL2
0.000
20
UB2
0.000
21
U1
0.000
22
U2
0.000
23
3U0
0.000
24
Ang (Ua-Ub)
deg
25
Ang (Ub-Uc)
deg
26
Ang (Uc-Ua)
deg
27
Ang (Ua-Ia)
deg
28
Ang (Ub-Ib)
deg
29
Ang (Uc-Ic)
deg
30
CBx.Ang (Ia-Ib)
deg
31
CBx.Ang (Ib-Ic)
deg
32
CBx.Ang (Ic-Ia)
deg
33
87L.FOx.Ia_Rmt
0.000
34
87L.FOx.Ib_Rmt
0.000
35
87L.FOx.Ic_Rmt
0.000
36
87L.FOx.Ida
0.000
37
87L.FOx.Idb
0.000
38
87L.FOx.Idc
0.000
5-2
5 Management
39
87L.FOx.Ang (Ia_Loc-Ia_Rmt)
40
87L.FOx.Ang (Ib_Loc-Ib_Rmt)
41
87L.FOx.Ang (Ic_Loc-Ic_Rmt)
42
43
Deg
Deg
Deg
0.000
Hz
P1
0.000
44
CBx.25.f_Syn
0.000
Hz
45
CBx.25.f_Diff
0.000
Hz
46
CBx.25.phi_Diff
47
CBx.25.U_Diff
0.000
Frequency
difference
between
protection
Symbol
Definition
Resolution
Unit
CBx.Ia
0.000
CBx.Ib
0.000
CBx.Ic
0.000
Ia
0.000
Ib
0.000
Ic
0.000
49-1.Accu_A
0.000
49-1.Accu_B
0.000
49-1.Accu_C
0.000
10
49-2.Accu_A
0.000
11
49-2.Accu_B
0.000
5-3
Date: 2015-05-23
5 Management
12
49-2.Accu_C
0.000
Symbol
Definition
Resolution
Unit
CBx.Ia
0.000
CBx.Ib
0.000
CBx.Ic
0.000
CBx.I1
0.000
CBx.I2
0.000
CBx.3I0
0.000
Ia
0.000
Ib
0.000
Ic
0.000
10
Ua
0.000
kV
11
Ub
0.000
kV
12
Uc
0.000
kV
13
Uab
0.000
kV
14
Ubc
0.000
kV
15
Uca
0.000
kV
16
U1
0.000
kV
17
U2
0.000
kV
18
3U0
0.000
kV
19
UB1
0.000
kV
20
UL2
0.000
kV
21
UB2
0.000
kV
22
0.000
Hz
23
UB1.f
0.000
Hz
24
UL2.f
0.000
Hz
25
UB2.f
0.000
Hz
5-4
5 Management
26
CBx.P
0.000
MW
27
CBx.Q
0.000
MVAr
28
CBx.S
0.000
MVA
29
CBx.Cos
0.000
30
CBx.Pa
0.000
MW
31
CBx.Pb
0.000
MW
32
CBx.Pc
0.000
MW
33
CBx.Qa
0.000
MVAr
34
CBx.Qb
0.000
MVAr
35
CBx.Qc
0.000
MVAr
36
CBx.Cosa
0.000
37
CBx.Cosb
0.000
38
CBx.Cosc
0.000
0.000
Hz
0.000
Hz/s
0.00
deg
0.000
kV
CBx.f_Diff
40
CBx.df/dt
41
CBx.phi_Diff
42
CBx.U_Diff
Symbol
Definition
Resolution
Unit
PHr+_Pri
0.000
MWh
PHr-_Pri
0.000
MWh
5-5
Date: 2015-05-23
5 Management
No.
Symbol
Definition
Resolution
Unit
QHr+_Pri
0.000
MVAh
QHr-_Pri
0.000
MVAh
5.2 Recording
5.2.1 Overview
PCS-931 provides the following recording functions:
1.
Event recording
2.
Disturbance recording
3.
Present recording
All the recording information except waveform can be viewed on local LCD or by printing.
Waveform could only be printed or extracted with PCS-Explorer software tool and a waveform
analysis software.
5-6
5 Management
Sequence number
Each operation will be recorded with a sequence number in the record and displayed on LCD
screen.
2.
The time resolution is 1ms using the relay internal clock synchronized via clock synchronized
device if connected. The date and time is recorded when a system fault is detected.
3.
An operating time (not including the operating time of output relays) is recorded in the record.
4.
Faulty phase
5.
Fault location
To get accurate result of fault location, the following settings shall be set correctly:
1)
2)
3)
4)
5-7
Date: 2015-05-23
5 Management
5)
6)
7)
8)
9)
6.
Protection elements
5-8
6 Hardware
6 Hardware
Table of Contents
6 Hardware ............................................................................................ 6-a
6.1 Overview .......................................................................................................... 6-1
6.2 Typical Wiring .................................................................................................. 6-4
6.2.1 Conventional CT/VT (For reference only) ........................................................................... 6-4
6.2.2 ECT/EVT (For reference only) ............................................................................................. 6-6
6.2.3 CT Requirement .................................................................................................................. 6-8
List of Figures
Figure 6.1-1 Rear view of fixed module position ..................................................................... 6-1
Figure 6.1-2 Hardware diagram .................................................................................................. 6-2
Figure 6.1-3 Front view of PCS-931 ........................................................................................... 6-3
Figure 6.1-4 Typical rear view of PCS-931 ................................................................................ 6-4
Figure 6.2-1 Typical wiring of PCS-931 (conventional CT/VT) ................................................ 6-5
Figure 6.2-2 Typical wiring of PCS-931 (ECT/EVT) .................................................................. 6-7
Figure 6.3-1 View of PWR plug-in module .............................................................................. 6-10
Figure 6.3-2 Output contacts of PWR plug-in module........................................................... 6-10
PCS-931 Line Differential Relay
6-a
Date: 2015-05-23
6 Hardware
6 Hardware
List of Tables
Table 6.3-1 Terminal definition and description of PWR plug-in module ............................ 6-10
Table 6.3-2 Terminal definition of AI module (NR1401) ......................................................... 6-17
Table 6.3-3 Terminal definition of AI module (NR1408) ......................................................... 6-20
Table 6.3-4 Terminal definition of AI module (NR1401) ......................................................... 6-23
Table 6.3-5 Terminal definition of AI module (NR1401) ......................................................... 6-26
Table 6.3-6 Encoding of IEC 61850-7-3 quality .......................................................................... 6-29
6-c
Date: 2015-05-23
6 Hardware
6-d
6 Hardware
6.1 Overview
PCS-931 adopts 32-bit microchip processor CPU produced by FREESCALE as control core for
management and monitoring function, meanwhile, adopts high-speed digital signal processor DSP
for all the protection calculation. 24 points are sampled in every cycle and parallel processing of
sampled data can be realized in each sampling interval to ensure ultrahigh reliability and safety of
the device.
12
13
PWR module
11
BO module
09
BO module
08
BO module
06
BO module
DSP module
05
BI module
CH Module
04
BI module
DSP module
AI module
MON module
PCS-931 is comprised of intelligent plug-in modules, except that few particular plug-in modules
position cannot be changed in the whole device (gray plug-in modules as shown in Figure 6.1-1),
other plug-in modules like AI (analog input) and IO (binary input and binary output) can be flexibly
configured in the remaining slot positions.
15
P1
Slot No.
01
02
03
07
10
14
PCS-931 has 16 slots, PWR plug-in module, MON plug-in module, DSP plug-in module and CH
plug-in module are assigned at fixed slots.
Besides 5 fixed modules are shown in above figure, there are 12 slots can be flexibly configured.
AI plug-in module, BI plug-in module and BO plug-in module can be configured at position
between slot 02, 03 and 06~15. It should be pay attention that AI plug-in module will occupy two
slots.
This device is developed on the basis of our latest software and hardware platform, and the new
platform major characteristics are of high reliability, networking and great capability in
anti-interference. See Figure 6.1-2 for hardware diagram.
6-1
Date: 2015-05-23
A/D
Protection
Calculation
DSP
A/D
Fault
Detector
DSP
Output Relay
Conventional CT/VT
External
Binary Input
6 Hardware
ECVT
Pickup
Relay
ECVT
ETHERNET
LCD
Power
Supply
Uaux
+E
Clock SYN
LED
CPU
RJ45
Keypad
PRINT
The working process of the device is as shown in above figure: current and voltage from
conventional CT/VT are converted into small voltage signal and sent to DSP module after filtered
and A/D conversion for protection calculation and fault detector respectively (ECVT signal is sent
to the device without small signal and A/D convertion). When DSP module completes all the
protection calculation, the result will be recorded in 32-bit CPU on MON module. DSP module
carries out fault detector, protection logic calculation, tripping output, and MON module perfomes
SOE (sequence of event) record, waveform recording, printing, communication between the
device and SAS and communication between HMI and CPU. When fault detector detects a fault
and picks up, positive power supply for output relay is provided.
The items can be flexibly configured depending on the situations like sampling method of the
device (conventional CT/VT or ECT/EVT), and the mode of binary output (conventional binary
output or GOOSE binary output). The configurations for PCS-900 series based on microcomputer
are classified into standard and optional modules.
Table 6.1-1 PCS-931 module configuration
Module ID
Module description
Remark
NR1101/NR1102
standard
NR1401/NR1408
standard
NR1161
standard
NR1213/NR1214
standard
NR1503/NR1504/NR1508
standard
NR1521/NR1580
standard
NR1301
standard
6-2
6 Hardware
Module ID
Module description
Remark
NR1136
module)
Human machine interface module (HMI module)
option
standard
MON module provides functions like communication with SAS, event record, setting
management etc.
AI module converts AC current and voltage from current transformers and voltage
transformers respectively to small voltage signal.
DSP module performs filtering, sampling, protection calculation and fault detector calculation.
CH module performs information exchange with the remote device through a dedicated
optical fibre channel, multiplex optical fibre channel or PLC channel.
BI module provides binary inputs via opto-couplers with rating voltage among
24V/110V/125V/220V/250V (configurable).
BO module provides output contacts for tripping, and signal output contact for annunciation
signal, remote signal, fault and disturbance signal, operation abnormal signal etc.
PWR module converts DC 250/220/125/110V into various DC voltage levels for modules of
the device.
NET-DSP module receives and sends GOOSE messages, sampled values (SV) from
merging unit by IEC61850-9-2 protocol.
HMI module is comprised of LCD, keypad, LED indicators and multiplex RJ45 ports for user
as human-machine interface.
PCS-931 is made of a 4U height 19 chassis for flush mounting. Components mounted on its front
include a 320240 dot matrix LCD, a 9 button keypad, 20 LED indicators and a multiplex RJ45
port. A monolithic micro controller is installed in the equipment for these functions.
Following figures show front and rear views of PCS-931 respectively.
ALARM
11
PCS-931
12
13
14
15
16
17
18
19
10
20
GRP
HEALTHY
ESC
1
2
ENT
6-3
Date: 2015-05-23
6 Hardware
20 LED indicators are, from top to bottom, operation (HEALTHY), self-supervision (ALARM),
others are configurable.
For the 9-button keypad, ENT is enter, GRP is group number and ESC is escape.
NR1102
NR1401
NR1161
NR1161
NR1213
NR1504
NR1504
NR1521
NR1521
NR1521
NR1521
NR1301
5V OK
ALM
TX
BO_ALM BO_FAIL
RX
ON
TX
OFF
RX
DANGER
1 BO_COM1
2
BO_FAIL
BO_ALM
BO_COM2
BO_FAIL
BO_ALM
OPTO+
OPTO-
9
10
PWR+
11
PWR-
12
GND
12
13
PWR module
11
NR1521F NR1301
BO module
BO module
06
BO module
05
BO module
04
NR1504
BI module
NR1161
DSP module
NR1213
CH Module
AI module
NR1161
DSP module
NR1401
MON module
NR1102
15
P1
Slot No.
01
02
03
07
08
09
10
14
6-4
6 Hardware
0801
CH-TX
CH-RX
BI_01
or
CH-TX
CH-RX
Fibre Optic
0203
Ib
0204
0205
To parallel line
Ic
0206
0207
IM0
0208
0215
Ub
0216
0217
0221
UL2
0222
0223
P110
PWR-
P111
OPTO+
P107
OPTO-
P108
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
Not used
0815
0816
0821
0822
1101
BO_01
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1301
BO_01
1302
1303
BO_02
1304
BO_FAIL
P103
0814
Power
Supply
P102
BI_13
PWR+
0809
External DC power
supply
BI_12
UB2
0224
0808
UB1
0220
Not used
BI_18
Synchronism Voltage
0219
0807
BI_07
Controlled by fault
detector element
Uc
0218
BI_06
Ua
0214
Protection Voltage
0213
0802
0202
Dedicated Channel
Or
Telecom Equipment
BO_11
1321
1322
1501
B
0102
SGND
0103
BO_CtrlOpn1
0104
0101
SYN-
0102
SGND
0103
0104
Clock SYN
SYN+
1502
1503
BO_CtrlCls1
1504
0101
COM
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
0105
TXD
0106
SGND
0107
PRINTER
RTS
BO_Ctrl
Multiplex
RJ45 (Front)
1522
P112
0225
Grounding
Bus
6-5
Date: 2015-05-23
6 Hardware
PCS-931 (conventional CT/VT and conventional binary input and binary output)
Slot No.
01
04
05
08
09
11
12
13
15
P1
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
06
07
NR1504
NR1504
10
NR1521
NR1521
NR1521
14
NR1521
NR1301
MON
AI
DSP
CH
BI
BI
BO
BO
BO
BO
PWR
08
09
11
12
13
PCS-931 (conventional CT/VT and GOOSE binary input and binary output)
Slot No.
01
04
05
06
Module ID
NR1102
02
NR1401
03
NR1161
NR1213
NR1136
07
NR1504
10
14
15
NR1301
P1
MON
AI
DSP
CH
NETDSP
BI
PWR
06
07
08
11
12
NR1301
PWR module
05
BO module
04
NR1521A NR1521C
BO module
BI module
NR1503
NET-DSP Module
NR1136
DSP module
NR1161
CH Module
NR1213
DSP module
NR1161
MON module
NR1102
Slot No.
01
02
03
09
10
13
14
15
P1
6-6
6 Hardware
CH-RX
Dedicated Channel
Or
Telecom Equipment
or
CH-TX
CH-RX
Fibre Optic
MU
Phase B
RX
TX
P111
OPTO+
P107
OPTO-
P108
Power
Supply
BO_FAIL
P103
BO_ALM
P101
COM
P105
BO_FAIL
P106
BO_ALM
P104
COM
0102
SGND
0103
0104
0101
SYN-
0102
SGND
0103
0104
0105
TXD
0106
SGND
0107
0804
0805
0806
0821
0822
1101
1102
1103
BO_02
1104
BO_11
1121
1122
1201
BO_01
1202
1203
BO_02
1204
BO_11
1221
1222
1502
1503
BO_CtrlCls1
1504
1517
BO_CtrlOpn5
1518
1519
BO_CtrlCls5
1520
1521
BO_Ctrl
1522
IRIG-B
PRINTER
RTS
BO_01
Clock SYN
SYN+
0803
0101
1501
COM
0802
BO_CtrlOpn1
Signal Binary Output (option)
P102
PWR-
0801
P110
BI_11
External DC power
supply
PWR+
BI_03
Controlled by fault
detector element
Phase C
BI_02
Phase A
SV from
ECT/EVT
BI_01
CH-TX
P112
Multiplex
RJ45 (Front)
0225
Grounding
Bus
Slot No.
01
04
05
06
Module ID
NR1102
02
03
NR1161
NR1213
NR1136
07
NR1504
08
09
10
11
12
13
14
15
NR1301
P1
MON
DSP
CH
NETDSP
BI
PWR
Slot No.
01
Module ID
02
03
04
05
06
NR1102
NR1161
NR1213
MON
DSP
CH
07
08
09
NR1136
NR1504
NETDSP
BI
11
12
13
NR1504
NR1521
NR1521
BI
BO
BO
10
14
15
P1
NR1521
NR1521
NR1301
BO
BO
PWR
6-7
Date: 2015-05-23
6 Hardware
In the protection system adopting electronic current and voltage transformer (ECT/EVT), the
merging unit will merge the sample data from ECT/EVT, and then send it to the device through
multi-mode optical fibre. DSP module receives the data from merging unit through the optical-fibre
interface to complete the protection calculation and fault detector.
The difference between the hardware platform based on ECT/EVT and the hardware platform
based on conventional CT/VT lies in the receiving module of sampled values only, and the device
receives the sampled value from merging unit through multi-mode optical fibre.
6.2.3 CT Requirement
-Rated primary current Ipn:
According to the rated current or maximum load current of primary apparatus.
-Rated continuous thermal current Icth:
According to the maximum load current.
-Rated short-time thermal current Ith and rated dynamic current Idyn:
According to the maximum fault current.
-Rated secondary current Isn
-Accuracy limit factor Kalf:
Ipn
Icth
Ith
Idyn
Isn
Kalf
IPal
Performance verification
Esl > Esl
Esl
Kalf
IPal
Ipn
Isn
Rct
Rbn
Rbn=Sbn/Isn
Sbn
Esl
6-8
6 Hardware
Esl = kIpcf Isn(Rct+Rb)/Ipn
k
Ipcf
stability factor = 2
Protective checking factor current (amps)
Same as the maximum prospective fault current
Isn
Rct
Rb
Rc
RL
Rr
Ipn
For example:
1.
Esl = 2IpcfIsn(Rct+Rb)/Ipn
= 2Ipcf Isn(Rct+(Rr+2RL+Rc))/Ipn
= 2400005(1+(0.1+20.5+0.1))/2000=440V
Thus, Esl > Esl
6-9
Date: 2015-05-23
6 Hardware
as below.
NR1301
5V OK
ALM
BO_ALM BO_FAIL
ON
OFF
BO_COM1
BO_FAIL
BO_ALM
BO_COM2
BO_FAIL
BO_ALM
OPTO+
OPTO-
9
10 PWR+
11 PWR12 GND
The power switch in the dotted box of above figure maybe is not existed.
01
BO_FAIL
02
BO_ALM
03
04
BO_FAIL
05
BO_ALM
06
Symbol
Description
01
BO_COM1
Common terminal 1
02
BO_FAIL
03
BO_ALM
04
BO_COM2
Common terminal 2
05
BO_FAIL
6-10
6 Hardware
Terminal No.
Symbol
Description
06
BO_ALM
07
OPTO+
08
OPTO-
09
Blank
Not used
10
PWR+
11
PWR-
12
GND
NOTICE!
The standard rated voltage of PWR module is self-adaptive to 88~300 Vdc. If input
voltage is out of range, an alarm signal (Fail_Device) will be issued. For non-standard
rated voltage power supply module please specify when place order, and check if the
rated voltage of power supply module is the same as the voltage of power source
before the device being put into service.
PWR module provides terminal 12 and grounding screw for device grounding. Terminal
12 shall be connected to grounding screw and then connected to the earth copper bar
of panel via dedicated grounding wire.
Effective grounding is the most important measure for a device to prevent EMI, so
effective grounding must be ensured before the device is put into service.
PCS-931, like almost all electronic relays, contains electrolytic capacitors. These
capacitors are well known to be subject to deterioration over time if voltage is not
applied periodically. Deterioration can be avoided by powering the relays up once a
year.
6-11
Date: 2015-05-23
6 Hardware
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
NR1102I
NR1102D
NR1101E
TX
ETHERNET
ETHERNET
RX
TX
RX
ETHERNET
Memory
Interface
Terminal No.
4 RJ45 Ethernet
RS-485
NR1102D
128M DDR
128M DDR
Physical Layer
To SCADA
01
SYN+
02
SYN-
To
03
SGND
synchronization
clock
04
RS-232
NR1102I
Usage
05
RTS
06
TXD
07
SGND
To printer
Cable
2 RJ45 Ethernet
To SCADA
2 FO Ethernet
To SCADA
Optical fibre ST
RS-485
01
SYN+
02
SYN-
To
03
SGND
synchronization
RTS
To printer
clock
04
RS-232
05
6-12
Cable
PCS-931 Line Differential Relay
Date: 2015-05-23
6 Hardware
06
TXD
07
SGND
2 RJ45 Ethernet
RS-485
To SCADA
01
02
03
SGND
To SCADA
04
RS-485
NR1101E
128M DDR
05
06
07
SGND
To SCADA
08
RS-485
09
SYN+
10
SYN-
To
11
SGND
synchronization
clock
12
RS-232
13
RTS
14
TXD
15
SGND
To printer
Cable
16
The correct connection is shown in Figure 6.3-4. Generally, the shielded cable with two pairs of
twisted pairs inside shall be applied. One pair of the twisted pairs are respectively used to connect
the + and terminals of difference signal. The other pair of twisted pairs are used to connect
the signal ground of the communication interface. The module reserves a free terminal for all the
communication ports. The free terminal has no connection with any signal of the device, and it is
used to connect the external shields of the cable when connecting multiple devices in series. The
external shield of the cable shall be grounded at one of the ends only.
Twisted pair wire
01
02
SGND
03
COM
04
SYN-
02
SGND
03
Clock SYN
SYN+
04
Cable
05
TXD
06
SGND
07
RTS
6-13
Date: 2015-05-23
6 Hardware
Pin1
Pin2
Pin3
NOTICE!
As shown in Figure 6.3-5, the external receiving mode of IRIG-B differential time
synchronization interface can be set by the jumper J8&J9.
Jumper
RS-485
TTL
J8
J9
Socket
Plug
In
Out
6-14
6 Hardware
In
Out
There are three types of AI module with rating 1A (NR1401), 5A (NR1401) or 1A/5A (NR1408).
Please declare which kind of AI module is needed before ordering. Maximum linear range of the
current converter is 40In.
1.
One CT group input without synchronism voltage switchover (optional NR1401 or NR1408)
NR1401
For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01, 03, 05 and 07 are
polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section Fault Location.
6-15
Date: 2015-05-23
6 Hardware
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02
01
02
01
04
03
04
03
06
05
06
05
08
07
08
07
13
14
15
16
17
18
19
20
6-16
6 Hardware
A
B
C
13
14
15
16
17
18
19
20
Ia
01
Ian
02
Ib
03
Ibn
04
Ic
05
Icn
06
IM0
07
IM0n
08
NR1401
09
10
11
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
Us
19
Usn
20
21
22
23
24
Figure 6.3-10 View of AI plug-in module for one CT group input (NR1401)
Definition
Ia
Definition
The current of A-phase (Polarity mark)
6-17
Date: 2015-05-23
6 Hardware
Terminal No.
Definition
Definition
02
Ian
03
Ib
04
Ibn
05
Ic
06
Icn
07
IM0
08
IM0n
09
Reserve
10
Reserve
11
Reserve
12
Reserve
13
Ua
14
Uan
15
Ub
16
Ubn
17
Uc
18
Ucn
19
Us
20
Usn
Synchronism voltage
21
Reserve
22
Reserve
23
Reserve
24
Reserve
25
GND
Ground
NR1408
For one CT group input, three phase currents (Ia, Ib and Ic) and residual current from parallel line
(for mutual compensation) are input to AI module separately. Terminal 01 (or 03), 05 (or 07), 09 (or
11) and 13 (or 15) are polarity marks. It is assumed that polarity mark of CT installed on line is at
line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
In order to accurately locate the fault for parallel lines arrangement, residual current from parallel
line is required to be connected to the device to eliminate the mutual effect between the parallel
lines. Otherwise, residual current from parallel line is not necessary.
Relevant description about parallel line to refer to section Fault Location.
6-18
6 Hardware
A
B
C
P2
S2
P2
S2
P1
S1
P1
S1
02/04
01/03
02/04
01/03
06/08
05/07
06/08
05/07
10/12
09/11
10/12
09/11
14/16
13/15
14/16
13/15
17
18
19
20
21
22
23
24
6-19
Date: 2015-05-23
6 Hardware
A
B
C
17
18
19
20
21
22
23
24
Ia-1A
01
Ian-1A
02
Ia-5A
03
Ian-5A
04
Ib-1A
05
Ibn-1A
06
Ib-5A
07
Ibn-5A
08
Ic-1A
09
Icn-1A
10
Ic-5A
11
Icn-5A
12
IM0-1A
13
IM0n-1A
14
IM0-5A
15
IM0n-5A
16
Ua
17
Uan
18
Ub
19
Ubn
20
Uc
21
Ucn
22
Us
23
Usn
24
NR1408
Figure 6.3-14 View of AI plug-in module for one CT group input (NR1408)
Definition
Ia-1A
Definition
The current of A-phase (Polarity mark)
6-20
6 Hardware
Terminal No.
2.
Definition
Definition
02
Ian-1A
03
Ia-5A
04
Ian-5A
05
Ib-1A
06
Ibn-1A
07
Ib-5A
08
Ibn-5A
09
Ic-1A
10
Icn-1A
11
Ic-5A
12
Icn-5A
13
IM0-1A
14
IM0n-1A
15
IM0-5A
16
IM0n-5A
17
Ua
18
Uan
19
Ub
20
Ubn
21
Uc
22
Ucn
23
Us
24
Usn
Synchronism voltage
25
GND
Ground
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2) are input to AI module.
Terminal 01, 03, 05, 07, 09 and 11 are polarity marks. It is assumed that polarity mark of CT
installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) are input to AI module. UB1, UB2 and UL2 are the
synchronism voltage from bus VT and line VT used for synchrocheck, it could be any
phase-to-ground voltage or phase-to-phase voltage. The device can automatically switch
synchronism voltage according to auxiliary contact of CB position or DS position.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
6-21
Date: 2015-05-23
6 Hardware
P2
P1
P1
P2
S1
S2
A
B
S2
S1
02
01
04
03
06
05
08
07
10
09
12
11
13
14
15
16
17
18
19
20
21
22
23
24
6-22
6 Hardware
Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
Ua
13
Uan
14
Ub
15
Ubn
16
Uc
17
Ucn
18
UB1
19
UB1n
20
UL2
21
UL2n
22
UB2
23
UB2n
24
NR1401
Figure 6.3-17 View of AI plug-in module for two CT group input (NR1401)
Definition
Definition
01
Ia1
02
Ia1n
03
Ib1
04
Ib1n
05
Ic1
06
Ic1n
07
Ia2
08
Ia2n
09
Ib2
10
Ib2n
11
Ic2
12
Ic2n
13
Ua
14
Uan
15
Ub
16
Ubn
17
Uc
18
Ucn
19
UB1
20
UB1n
6-23
Date: 2015-05-23
6 Hardware
Terminal No.
3.
Definition
Definition
21
UL2
22
UL2n
23
UB2
24
UB2n
25
GND
Ground
For two circuit breakers configuration with two CT groups input, three phase currents
corresponding to CB1 and CB2 respectively (Ia1, Ib1, Ic1 and Ia2, Ib2, Ic2), and residual current
from parallel line (for mutual compensation) are input to AI module. Terminal 01, 03, 05, 07, 09, 11
and 13 are polarity marks. It is assumed that polarity mark of CT installed on line is at line side.
Three phase voltages (Ua, Ub, and Uc) for protection calculation and one synchronism voltage are
input to AI module. The synchronism voltage could be any phase-to-ground voltage or
phase-to-phase voltage.
If the auto-reclosing is enabled but synchronism check is not required, the synchronism voltage
should be disconnected.
P2
P1
P1
P2
A
B
S2
S1
S1
02
01
04
03
06
05
08
07
10
09
12
11
14
13
S2
To parallel line
From parallel line
6-24
6 Hardware
A
15
16
17
18
19
20
21
22
23
24
Ia1
01
Ia1n
02
Ib1
03
Ib1n
04
Ic1
05
Ic1n
06
Ia2
07
Ia2n
08
Ib2
09
Ib2n
10
Ic2
11
Ic2n
12
IM0
13
IM0n
14
Ua
15
Uan
16
Ub
17
Ubn
18
Uc
19
Ucn
20
Us
21
Usn
22
NR1401
23
24
Figure 6.3-20 View of AI plug-in module for two CT group input (NR1401)
6-25
Date: 2015-05-23
6 Hardware
Definition
Definition
01
Ia1
02
Ia1n
03
Ib1
04
Ib1n
05
Ic1
06
Ic1n
07
Ia2
08
Ia2n
09
Ib2
10
Ib2n
11
Ic2
12
Ic2n
13
IM0
14
IM0n
15
Ua
16
Uan
17
Ub
18
Ubn
19
Uc
20
Ucn
21
Us
22
Usn
Synchronism voltage
23
Reserve
24
Reserve
25
GND
Ground
6-26
6 Hardware
NR1161
This device can be equipped with 2 DSP plug-in modules at most and 1 DSP plug-in module at
least. The default DSP plug-in module is necessary, which mainly is responsible for protection
function including fault detector and protection calculation.
The default module consists of high-performance double DSP (digital signal processor),16-digit
high-accuracy ADC that can perform synchronous sampling and manage other peripherals. One
of double DSP is responsible for protection calculation, and can fulfill analog data acquisition,
protection logic calculation and tripping output. The other is responsible for fault detector, and can
fulfill analog data acquisition, fault detector and providing power supply to output relay.
When the module is connected with conventional CT/VT, it can perform the synchronous data
acquisition through AI plug-in module. When the module is connected with ECT/EVT, it can
receive the real-time synchronous sampled value from merging unit through NET-DSP plug-in
module.
The other module is optional and it is not required unless control and manual closing with
synchronism check are equppied with this device. The default DSP plug-in module is fixed at slot
04 and the option DSP plug-in module is fixed at slot 06.
6-27
Date: 2015-05-23
6 Hardware
NR1136A
NR1136C
RX
This module consists of high-performance DSP (digital signal processor), 2~8 100Mbit/s
optical-fibre interface (LC type) and selectable IRIG-B interface (ST type). It supports GOOSE and
SV by IEC 61850-9-2 protocols. It can receive and send GOOSE messages to intelligent control
device, and receive SV from MU (merging unit).
This module supports IEEE1588 network time protocol, E2E and P2P defined in IEEE1588
protocol can be selected.This module supports Ethernet IEEE802.3 time adjustment message
format, UDP time adjustment message format and GMRP.
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
The device can output q data by GOOSE, and an output signal is provided Output_q. This signal
is used to indicate the quality of all output signals. According to the standard definition about the
quality by IEC 61850, the value of this signal is 0 under normal conditions, and it will be 2048
(Bit1 is 1, and other bits is 0) when the device is under maintenance condtion.
The definition of each bit about quality signal by IEC 61850 is as below.
6-28
6 Hardware
Table 6.3-6 Encoding of IEC 61850-7-3 quality
Bit (s)
IEC 61850-7-3
Bit
0-1
Attribute name
Validity
Bit-String
Attribute value
Value
Good
00
Invalid
01
Reserved
10
Questionable
11
Default
00
Overflow
TRUE
FALSE
OutofRange
TRUE
FALSE
BadReference
TRUE
FALSE
Oscillatory
TRUE
FALSE
Failure
TRUE
FALSE
OldData
TRUE
FALSE
Inconsistent
TRUE
FALSE
Inaccurate
TRUE
FALSE
10
Source
Process
Subsituted
11
Test
TRUE
FALSE
12
OperatorBlocked
TRUE
FALSE
2.
Step2: Taking PTRC_out module as an example, which can be found in Symbol Library
and instanced as bellow.
6-29
Date: 2015-05-23
6 Hardware
3.
Step3: Double click the instanced module, the parameter list is displayed as bellow. Tr1~Tr8
are used for sending signals, q1~q8 are used for q data, the relationship between them is one
to one. Only one total q data can be added to all 8 sending signals by batch_q.
4.
Step4: The output q data, named Output_q in variable library, is used for all sending signals.
The path is shown as bellow which is marked in red color.
6-30
6 Hardware
5.
Step5: Put the mouse on the Output_q signal, hold the left button of the mouse and drag it to
the corresponding position, and then release. The detail is as bellow.
After the above steps, save the modifications and compress driver file. Check the latest GOOSE
and CID file.
6-31
Date: 2015-05-23
6 Hardware
NR1213
NR1213
NR1213
NR1213
TX
TX
TX
TX
RX
RX
RX
RX
TX
TX
RX
RX
NR1213A
NR1213
NR1213A-100
NR1213
NR1213B
NR1214
TX
TX
RX
RX
NR1213B-100
NR1214
TX1
TX1
RX1
RX1
TX1
TX1
TX1
RX1
RX1
RX1
NR1213F
NR1213F-100
NR1214A
NR1214B
6-32
6 Hardware
Type
Wavelength
Application
NR1213A
1310nm
NR1213A-100
1550nm
NR1213B
1310nm
NR1213B-100
1550nm
1310nm
830nm
1550nm
830nm
NR1214A
830nm
NR1214B
830nm
NR1213F
NR1213F-100
PCS-931 series can exchange information with the device at the remote end through a dedicated
optical fibre channel or multiplex channel. The module transmits and receives optical signal using
FC/PC or ST optical connector.
The parameters are shown as follows:
Item
Type1
Type2
Type3
Fiber Optic
Wavelength
1310nm
1550nm
830nm
Transmission power
-13.03.0 dBm
-12dBm~-20 dBm
Receiving sensitivity
Min.-37 dBm
Min.-36 dBm
Min.-30 dBm
Transmission distance
Max.40 km
Max.100 km
Max.2 km
Min.-3 dBm
Min.-3 dBm
Min.-8 dBm
NOTICE!
When using dedicated optical fibre channel, if the transmission distance is longer than
50km, the transmitted power may be enchanced to ensure received power larger than
receiving sensitivity. Please notify supplier before ordering and it will be considered as
special project using 1550nm laser diode.
When using multiplex channel, the sending power of the device is fixed.
When using channel multiplexing equipment, the parameters are shown as follows:
1.
2.
The routine of both direction shall be same to each other, so the time delays of both direction
are the same.
2.
The maximum one-way channel propagation delay shall be less than 15 ms.
6-33
Date: 2015-05-23
6 Hardware
CAUTION!
Do NOT look into the end of an optical fiber connected to an optical port.
Do NOT look into an optical port/connector.
A direct sight to laser light may cause temporary or permanent blindness.
176
154
140
110
87.5
77
62.5
Operation
55
Operation uncertain
No operation
110V
125V
220V
220V
The well-designed debouncing technique is adopted in this device, and the state change of binary
input within Debouncing time will be ignored. As shown in Figure 6.3-25.
6-34
6 Hardware
Binary input state
0
Debouncing time
T0
Time
T1
1.
NR1503
Each BI module is with a 22-pin connector for 11 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. Each binary input of NR1503A and NR1503AR has
independent negative power input of opto-coupler and can be configurable. NR1503As pickup
voltage and dropoff voltage are fixed value, and the range is from 55%Un to 70%Un. NR1503ARs
pickup voltage and dropoff voltage are settable by the setting [xx.U_Pickup_BI] and
[xx.U_Dropoff_BI] from 55%Un to 80%Un.
NR1503
BI_01
01
Opto01-
02
BI_02
03
Opto02-
04
BI_03
05
Opto03-
06
BI_04
07
Opto04-
08
BI_05
09
Opto05-
10
BI_06
11
Opto06-
12
BI_07
13
Opto07-
14
BI_08
15
Opto08-
16
BI_09
17
Opto09-
18
BI_10
19
Opto10-
20
BI_11
21
Opto11-
22
6-35
Date: 2015-05-23
6 Hardware
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ).
Terminal description for NR1503 is shown as follows.
Terminal No.
Symbol
Description
01
BI_01
02
Opto01-
03
BI_02
04
Opto02-
05
BI_03
06
Opto03-
07
BI_04
08
Opto04-
09
BI_05
10
Opto05-
11
BI_06
12
Opto06-
13
BI_07
14
Opto07-
15
BI_08
16
Opto08-
17
BI_09
18
Opto09-
19
BI_10
20
Opto10-
21
BI_11
22
Opto11-
2.
NR1504
Each BI module is with a 22-pin connector for 18 binary inputs, and its rated voltage can be
selected to be 110Vdc, 125Vdc, 220Vdc. All binary inputs of NR1504A and NR1504AR share one
common negative power input and can be configurable. NR1504As pickup voltage and dropoff
voltage are fixed value, and the range is from 55%Un to 70%Un. NR1504ARs pickup voltage and
dropoff voltage are settable by the setting [xx.U_Pickup_BI] and [xx.U_Dropoff_BI] from 55%Un to
80%Un.
6-36
6 Hardware
NR1504
Opto+
01
BI_01
02
BI_02
03
BI_03
04
BI_04
05
BI_05
06
BI_06
07
08
BI_07
09
BI_08
10
BI_09
11
BI_10
12
BI_11
13
BI_12
14
15
BI_13
16
BI_14
17
BI_15
18
BI_16
19
BI_17
20
BI_18
21
COM-
22
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ).
Terminal description for NR1504 is shown as follows.
Terminal No.
Symbol
Description
01
Opto+
02
BI_01
03
BI_02
04
BI_03
05
BI_04
06
BI_05
07
BI_06
08
Blank
Not used
09
BI_07
10
BI_08
11
BI_09
12
BI_10
13
BI_11
14
BI_12
15
Blank
Not used
16
BI_13
17
BI_14
18
BI_15
19
BI_16
6-37
Date: 2015-05-23
6 Hardware
Terminal No.
Symbol
Description
20
BI_17
21
BI_18
22
COM-
3.
NR1508
NR1508A is with a 22-pin connector for 11 binary inputs, and its rated voltage is 220Vdc. Each
binary input of NR1508A has independent negative power input of opto-coupler and can be
configurable. NR1508As pickup voltage and dropoff voltage are fixed value, and the range is from
75%Un to 80%Un.
NR1508A
BI_01
01
Opto01-
02
BI_02
03
Opto02-
04
BI_03
05
Opto03-
06
BI_04
07
Opto04-
08
BI_05
09
Opto05-
10
BI_06
11
Opto06-
12
BI_07
13
Opto07-
14
BI_08
15
Opto08-
16
BI_09
17
Opto09-
18
BI_10
19
Opto10-
20
BI_11
21
Opto11-
22
[BI_n] can be configured as a specified binary input by PCS-Explorer software (n=01, 02, ).
Terminal description for NR 1508A is shown as follows.
Terminal No.
Symbol
Description
01
BI_01
02
Opto01-
03
BI_02
04
Opto02-
05
BI_03
06
Opto03-
07
BI_04
08
Opto04-
09
BI_05
6-38
6 Hardware
Terminal No.
Symbol
Description
10
Opto05-
11
BI_06
12
Opto06-
13
BI_07
14
Opto07-
15
BI_08
16
Opto08-
17
BI_09
18
Opto09-
19
BI_10
20
Opto10-
21
BI_11
22
Opto11-
NOTICE!
A default configuration is given for first four binary signals (BI_01, BI_02, BI_03, BI_04)
in first BI plug-in module, and they are [BI_TimeSyn], [BI_Print], [BI_Maintenance] and
[BI_RstTarg] respectively. They can alos be configured as other signals. Because the
first binary signal [BI_01] is set as [BI_TimeSyn] by default (the state change
information of binary signal [BI_TimeSyn] does not need be displayed), new binary
signal should be added to state change message if it is set as other signal.
1.
It is used to receive clock synchronization signal from clock synchronization device, the binary
input [BI_TimeSyn] will change from 0 to 1 once pulse signal is received. When the device
adopts Conventional mode as clock synchronization mode (refer to section Communication
Settings), the device can receives PPM (pulse per minute) and PPS (pulse per second). If the
setting [Opt_TimeSyn] is set as other values, this binary input is invalid.
2.
It is used to manually trigger printing latest report when the equipment is configured as manual
printing mode by logic setting [En_AutoPrint]=0. The printer button is located on the panel usually.
If the equipment is configured as automatic printing mode ([En_AutoPrint]=1), report will be printed
automatically as soon as it is formed.
3.
It is used to block communication export when this binary input is energized. During device
maintenance or testing, this binary input is then energized not to send reports via communication
port, local display and printing still work as usual. This binary input should be de-energized when
the device is restored back to normal.
The application of the binary input [BI_Maintenance] for digital substation communication adopting
IEC61850 protocol is given as follows.
6-39
Date: 2015-05-23
6 Hardware
1)
a)
The protection device should send the state of this binary input to client.
b) When this binary input is energized, the bit Test of quality (Q) in the sent message changes
to 1.
c) When this binary input is energized, the client cannot control the isolator link and circuit
breaker, modify settings and switch setting group remotely.
d) According to the value of the bit Test of quality (Q) in the message sent, the client
discriminate whether this message is maintenance message, and then deal with it correspondingly.
If the message is the maintenance message, the content of the message will not be displayed on
real-time message window, audio alarm not issued, but the picture is refreshed so as to ensure
that the state of the picture is in step with the actual state. The maintenance message will be
stored, and can be inquired, in independent window.
2)
a) When this binary input is energized, the bit Test in the GOOSE message sent by the
protection device changes to 1.
b) For the receiving end of GOOSE message, it will compare the value of the bit Test in the
GOOSE message received by it with the state of its own binary input (i..e [BI_Maintenance]), the
message will be thought as invalid unless they are conformable.
3)
a) When this binary input of merging unit is energized, the bit Test of quality (Q) of sampling
data in the SV message sent change 1.
b) For the receiving end of SV message, if the value of bit Test of quality (Q) of sampling data
in the SV message received is 1, the relevant protection functions will be disabled, but under
maintenance state, the protection device should calculate and display the magnitude of sampling
data.
c) For duplicated protection function configurations, all merging units of control module
configured to receive sampling should be also duplicated. Both dual protection devices and dual
merging units should be fully independent each other, and one of them is in maintenance state will
not affect the normal operation of the other.
4.
It is used to reset latching signal relay and LCD displaying. The reset is done by pressing a button
on the panel.
NOTICE!
The rated voltage of binary input is optional: 110V, 125V, 220V or 250V, which must be
specified when placed order. It is necessary to check whether the rated voltage of BI
module complies with site DC supply rating before put the relay in service.
6-40
6 Hardware
There three binary signals are fixed for measurement functions, they are [BI_Rmt/Loc],
[BI_ManSynCls] and [BI_ManOpen] respectively.
5.
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
synchronism check for closing circuit breaker will be initiated if it is energized.
7.
When the device is under local control condition (i.e. [BI_Rmt/Loc] is de-energized), the manual
control for open circuit breaker will be initiated if it is energized.
6-41
Date: 2015-05-23
6 Hardware
BO_01
NR1521A
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
BO_01
NR1521C
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
6-42
6 Hardware
BO plug-in module (NR1521F) is dedicatedly for remote/manual open or closing to circuit breaker,
disconnector and earth switch. 5 pairs of binary outputs (one for open and the other for closing)
can be provided by this BO plug-in module configured in slot 15 if measurement and control
function is equipped with the device. More binary outputs can be provided by another BO plug-in
modules that can be configured in slot 11, 12, 13, 14 if open or closing contacts is not enough.
First pair of binary outputs are used to remote/manual open or close circuit breaker, and second
pair of binary outputs are also used to remote/manual open or close circuit breaker for double
circuit breakers application.
A normally open contact is presented via terminal 21-22 designated as ROS (i.e. remote operation
signal). Whenever any of binary output contacts for open or closing is closed, ROS contact will
close to issue a signal indicating that this device is undergoing a remote operation.
BO plug-in module (NR1521F) is displayed as shown in the following figure.
BO_CtrlOpn01
NR1521F
BO_CtrlCls01
BO_CtrlOpn02
BO_CtrlCls02
BO_CtrlOpn03
BO_CtrlCls03
BO_CtrlOpn04
BO_CtrlCls04
BO_CtrlOpn05
BO_CtrlCls05
BO_Ctrl
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
NR1521G can provide 11 output contacts without controlled by fault detector. The first four output
contacts are in parallel with instantaneous operating contacts which are recommended to be
configured as fast signaling contacts to send PLC signal.
6-43
Date: 2015-05-23
6 Hardware
BO_01
NR1521G
BO_02
BO_03
BO_04
BO_05
BO_06
BO_07
BO_08
BO_09
BO_10
BO_11
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
NR1580A can provide 6 output contacts with controlled by fault detector. It is a heavy-capacity
binary output plug-in module, which can be used to control the circuit breaker directly.
+
01
BO_01
NR1580A
02
03
04
05
BO_02
06
07
08
09
BO_03
10
11
12
13
BO_04
14
15
16
17
BO_05
18
19
20
+
-
BO_06
21
22
6 Hardware
6-45
Date: 2015-05-23
6 Hardware
6-46
7 Settings
7 Settings
Table of Contents
7 Settings .............................................................................................. 7-a
7.1 System Settings .............................................................................................. 7-1
7.1.1 Setting Description............................................................................................................... 7-1
7.1.2 Access Path ......................................................................................................................... 7-2
7.5 Control and Synchrocheck for Manual Closing Settings .......................... 7-44
7.5.1 Setting Description............................................................................................................. 7-44
7.5.2 Access Path ....................................................................................................................... 7-47
List of Tables
Table 7.1-1 System settings ....................................................................................................... 7-1
Table 7.2-1 Device settings......................................................................................................... 7-2
Table 7.2-2 Communication settings ......................................................................................... 7-3
7-a
Date: 2015-10-22
7 Settings
7-b
7 Settings
The device has some setting groups for protection to coordinate with the mode of power system
operation, one of which is assigned to be active. However, communication settings, system
settings, device settings, logic link settings and measurement and control settings are common for
all protection setting groups.
NOTICE!
All current settings in this chapter are secondary current converted from primary current
by CT ratio. Zero-sequence current or voltage setting is configured according to 3I0 or
3U0 and negative sequence current setting according to I2 or U2.
Item
Range
Unit
Active_Grp
1~10
Opt_SysFreq
50 or 60
PrimaryEquip_Name
Maximum 12 character
U1n
10.00~65500.00
kV
U2n
80.00~220.00
CBx.I1n
100~30000
I1n_Base
100~30000
I2n_Base
1 or 5
f_High_FreqAlm
50~65
Hz
10
f_Low_FreqAlm
45~60
Hz
1.
Hz
Active_Grp
The number of active setting group, 10 setting groups can be configured for protection settings,
and only one is active at a time
2.
PrimaryEquip_Name
It is recognized by the device automatically. Such setting is used for printing messages
3.
Opt_SysFreq
Un1
Un2
CBx.I1n
7-1
Date: 2015-10-22
7 Settings
I1n_Base
I2n_Base
f_High_FreqAlm
It is frequency upper limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is higher than the setting.
10. f_Low_FreqAlm
It is frequency lower limit setting.The device will issue an alarm [Alm_Freq], when system
frequency is lower than the setting.
1.
Item
Range
HDR_EncodeMode
GB18030, UTF-8
Opt_Caption_103
Bxx.Un_BinaryInput
Bxx.U_Pickup_BI
55%Un~80%Un
Bxx.U_Dropoff_BI
55%Un~80%Un
En_MDisk
0 or 1
HDR_EncodeMode
Opt_Caption_103
Bxx.Un_BinaryInput
7-2
7 Settings
This setting is used to set voltage level of binary input module. If low-voltage BI module is
equipped, 24V, 30V or 48V can be set according to the actual requirement, and if high-voltage BI
module is equipped, 110V, 125V or 220V can be set according to the actual requirement.
Bxx: this plug-in module is inserted in slot xx.
4.
Bxx.U_Pickup_BI
This setting is used to set pickup voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
5.
Bxx.U_Dropoff_BI
This setting is used to set dropoff voltage of binary input module. Bxx: this plug-in module is
inserted in slot xx.
6.
En_MDisk
Item
Range
IP_LAN1
000.000.000.000~255.255.255.255
Mask_LAN1
000.000.000.000~255.255.255.255
IP_LAN2
000.000.000.000~255.255.255.255
Mask_LAN2
000.000.000.000~255.255.255.255
En_LAN2
0 or 1
IP_LAN3
000.000.000.000~255.255.255.255
Mask_LAN3
000.000.000.000~255.255.255.255
En_LAN3
0 or 1
IP_LAN4
000.000.000.000~255.255.255.255
10
Mask_LAN4
000.000.000.000~255.255.255.255
11
En_LAN4
0 or 1
7-3
Date: 2015-10-22
7 Settings
No.
Item
Range
12
Gateway
000.000.000.000~255.255.255.255
13
En_Broadcast
0 or 1
14
Addr_RS485A
0~255
15
Baud_RS485A
4800,9600,19200,38400,57600,115200 (bps)
16
Protocol_RS485A
17
Addr_RS485B
0~255
18
Baud_RS485B
4800,9600,19200,38400,57600,115200 (bps)
19
Protocol_RS485B
20
Threshold_Measmt_Net
0~100%
21
Period_Measmt_Net
0~65535s
22
Format_Measmt
0, 1
23
Baud_Printer
4800,9600,19200,38400,57600,115200 (bps)
24
En_AutoPrint
0 or 1
25
Opt_TimeSyn
26
IP_Server_SNTP
000.000.000.000~255.255.255.255
27
IP_StandbyServer_SNTP
000.000.000.000~255.255.255.255
28
OffsetHour_UTC
-12~+12 (hrs)
29
OffsetMinute_UTC
0~60 (min)
30
Opt_Display_Status
PriValue, SecValue
31
Num_Cyc_PreTrigDFR
0~140 (cycles)
32
En_TCPx_DNP
0 or 1
33
Addr_Slave_TCPx_DNP
0~65519
34
Addr_Master_TCPx_DNP
0~65519
35
IP_Master_TCPx_DNP
000.000.000.000~255.255.255.255
36
Opt_Map_TCPx_DNP
0~4
37
Obj01DefltVar_TCPx_DNP
0~1
38
Obj02DefltVar_TCPx_DNP
0~2
39
Obj30DefltVar_TCPx_DNP
0~4
40
Obj32DefltVar_TCPx_DNP
0~2
41
Obj40DefltVar_TCPx_DNP
0~2
42
t_AppLayer_TCPx_DNP
0~5 (s)
43
t_KeepAlive_TCPx_DNP
0~7200 (s)
44
En_UR_TCPx_DNP
0 or 1
45
Num_URRetry_TCPx_DNP
2~10
46
t_UROfflRetry_TCPx_DNP
1~5000 (s)
47
Class_BI_TCPx_DNP
0~3
48
Class_AI_TCPx_DNP
0~3
49
t_Select_TCPx_DNP
0~240 (s)
7-4
7 Settings
No.
Item
50
t_TimeSynIntvl_TCPx_DNP
1.
Range
0~3600 (s)
IP address of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
2.
Subnet mask of Ethernet port 1, Ethernet port 2, Ethernet port 3 and Ethernet port 4
3.
4.
Gateway
5.
En_Broadcast
This setting is only used only for IEC 60870-5-103 protocol. If NR network IEC 60870-5-103
protocol is used, the setting must be set as 1.
0: the device does not send UDP messages through network
1: the device sends UDP messages through network
6.
Addr_RS485A, Addr_RS485B
They are the devices communication address used to communicate with the SCADA or RTU via
serial ports (port A and port B).
7.
Baud_RS485A, Baud_RS485B
Protocol_RS485A, Protocol_RS485B
7-5
Date: 2015-10-22
7 Settings
(port A and port B) are not listed in this submenu. And the settings about the Ethernet
ports only listed in this submenu according to the actual number of Ethernet ports.
The standard arrangement of the Ethernet port is two, at most four (predetermined
when ordering). Set the IP address according to actual arrangement of Ethernet
numbers and the un-useful port/ports need not be configured. If PCS-Explorer
configuration tool auxiliary software is connected with this device through the Ethernet,
the IP address of PCS-Explorer must be set as one of the available IP address of this
device.
9.
Threshold_Measmt_Net
10. Period_Measmt_Net
The time period for equipment sends measurement data to SCADA through IEC 60870-5-103
protocol via Ethernet port.
Default value: 60
11. Format_Measmt
The setting is used to select the format of measurement data sent to SCADA through IEC
60870-5-103 protocol.
0: GDD data type through IEC103 protocol is 12
1: GDD data type through IEC103 protocol is 7, i.e. 754 short real number of IEEE standard
12. Baud_Printer
Baud rate of printer port
13. En_AutoPrint
If automatic print is required for fault report after protection operating, it is set as 1. Otherwise, it
should be set to 0.
14. Opt_TimeSyn
There are four selections for clock synchronization of device shown as follow.
Conventional
PPS (RS-485): Pulse per second (PPS) via RS-485 differential level
IRIG-B (RS-485): IRIG-B via RS-485 differential level
PPM (DIN): Pulse per minute (PPM) via the binary input [BI_TimeSyn]
PPS (DIN): Pulse per second (PPS) via the binary input [BI_TimeSyn]
7-6
7 Settings
SAS
Advanced
NoTimeSync
When no time synchronization signal is connected to the device, please select this option and the
alarm message [Alm_TimeSyn] will not be issued anymore.
Conventional mode and SAS mode are always be supported by the device, but Advanced
mode is only supported when NET-DSP module is equipped. The alarm signal [Alm_TimeSyn]
may be issued to remind user loss of time synchronization signals.
1)
When SAS is selected, if there is no conventional clock synchronization signal, the device
will not send the alarm signal [Alm_TimeSyn]. When Conventional mode is selected, if there
is no conventional clock synchronization signal, SAS mode will be enabled automatically
with the alarm signal [Alm_TimeSyn] issued simultaneously.
2)
3)
When NoTimeSyn mode is selected, the device will not send alarm signals without time
synchronization signal. But the device can be still synchronized if receiving time
synchronization signal.
NOTICE!
The clock message via IEC 60870-5-103 protocol is invalid when the device receives
the IRIG-B signal through RCS-485 port.
15. IP_Server_SNTP
It is the address of the SNTP time synchronization server which sends SNTP timing messages to
the relay or BCU.
16. IP_StandbyServer_SNTP
Both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are ineffective unless SNTP clock
synchronization is valid.
When both [IP_Server_SNTP] and [IP_StandbyServer_SNTP] are set as "000.000.000.000", the
7-7
Date: 2015-10-22
7 Settings
GMT zone
East 1st
East 2nd
East 3rd
East 4th
East 5th
Setting
Time zone
th
East 6
Setting
Time zone
East 7
Setting
Time zone
th
7
th
East 8
8
st
East/West 12
West 1
12/-12
-1
East 9
9
nd
West 2
-2
th
th
rd
West 3
-3
th
th
East 10
East 11th
10
11
th
West 4
-4
th
West 5th
-5
West 6
West 7
West 8
West 9
West 10
West 11th
-6
-7
-8
-9
-10
-11
Setting
th
th
th
18. Opt_Display_Status
This setting is used to set display mode of current and voltage in fault records, primary value or
secondary value. The sampled values of current and voltage are displayed as secondary value by
default. When it is set as primary value, both secondary voltage and secondary current are
converted into primary voltage and primary current according to rated secondary and primary
value of VT and CT respectively.
19. Num_Cyc_PreTrigDFR
The setting is used to set the cycle number recorded by the device before the trigger element
operating.
20. En_TCPx_DNP
The logic setting is used to enable or disable network No.x DNP client. (x=1, 2, 3, 4)
7-8
7 Settings
1: enable
0: disable
When network No.x DNP client is not configured to be in service by PCS-Explorer, DNP client
settings corresponding to network No.x will be hidden.
21. Addr_Slave_TCPx_DNP
It is the slave address of network No.x DNP client. (x=1, 2, 3, 4)
22. Addr_Master_TCPx_DNP
It is the master address of network No.x DNP client. (x=1, 2, 3, 4)
23. IP_Master_TCPx_DNP
It is the IP address of network No.x DNP client. (x=1, 2, 3, 4)
24. Opt_Map_TCPx_DNP
It is the communication map of network No.x DNP client. (x=1, 2, 3, 4)
25. Obj01DefltVar_TCPx_DNP
It is the OBJ1 default variation of network No.x DNP client. (x=1, 2, 3, 4)
26. Obj02DefltVar_TCPx_DNP
It is the OBJ2 default variation of network No.x DNP client. (x=1, 2, 3, 4)
27. Obj30DefltVar_TCPx_DNP
It is the OBJ30 default variation of network No.x DNP client. (x=1, 2, 3, 4)
28. Obj32DefltVar_TCPx_DNP
It is the OBJ32 default variation of network No.x DNP client. (x=1, 2, 3, 4)
29. Obj40DefltVar_TCPx_DNP
It is the OBJ40 default variation of network No.x DNP client. (x=1, 2, 3, 4)
30. t_AppLayer_TCPx_DNP
It is the timeout of application layer of network No.x DNP client. (x=1, 2, 3, 4)
31. t_KeepAlive_TCPx_DNP
It is the heartbeat time interval of network No.x DNP client. (x=1, 2, 3, 4)
32. En_UR_TCPx_DNP
The logic setting is used to enable or disable the unsolicited message function of network No.x
DNP client. (x=1, 2, 3, 4)
1: enable
7-9
Date: 2015-10-22
7 Settings
0: disable
33. Num_URRetry_TCPx_DNP
It is the online retransmission number of the unsolicited message of network No.x DNP client. (x=1,
2, 3, 4)
34. t_UROfflRetry_TCPx_DNP
It is the offline timeout of the unsolicited message of network No.x DNP client. (x=1, 2, 3, 4)
35. Class_BI_TCPx_DNP
It is the class level of the Binary Input of network No.x DNP client. (x=1, 2, 3, 4)
36. Class_AI_TCPx_DNP
It is the class level of the Analog Input of network No.x DNP client. (x=1, 2, 3, 4)
37. t_Select_TCPx_DNP
It is the selection timeout of network No.x DNP client. (x=1, 2, 3, 4)
38. t_TimeSynIntvl_TCPx_DNP
It is the time interval of the time synchronization function of network No.x DNP client. (x=1, 2, 3, 4)
Item
Remark
Range
X1L
(0.000~4Unn)/In (ohm)
R1L
(0.000~4Unn)/In (ohm)
X0L
(0.000~4Unn)/In (ohm)
R0L
(0.000~4Unn)/In (ohm)
X0M
(0.000~4Unn)/In (ohm)
R0M
(0.000~4Unn)/In (ohm)
LineLength
0.00~655.35 (km)
7-10
7 Settings
Item
FD.DPFC.I_Set
FD.ROC.3I0_Set
FD.NOC.I2_Set
FD.NOC.En
Remark
Range
(0.050~30.000)In (A)
(0.050~30.000)In (A)
(0.050~30.000)In (A)
0 or 1
Item
AuxE.OCD.t_DDO
AuxE.OCD.En
AuxE.ROC1.3I0_Set
AuxE.ROC1.En
AuxE.ROC2.3I0_Set
AuxE.ROC2.En
AuxE.ROC3.3I0_Set
AuxE.ROC3.En
AuxE.OC1.I_Set
Remark
Range
0 or 1
0.000~10.000 (s)
auxiliary
element
Enable stage 2 residual current auxiliary element
Current setting of stage 3 residual current auxiliary
element
Enable stage 3 residual current auxiliary element
Current setting of stage 1 phase current auxiliary
element
Enable stage 1 phase current auxiliary element
(0.050~30.000)In (A)
0 or 1
(0.050~30.000)In (A)
0 or 1
(0.050~30.000)In (A)
0 or 1
(0.050~30.000)In (A)
10
AuxE.OC1.En
11
AuxE.OC2.I_Set
12
AuxE.OC2.En
13
AuxE.OC3.I_Set
14
AuxE.OC3.En
0 or 1
15
AuxE.UVD.U_Set
0~Un (V)
16
AuxE.UVD.t_DDO
17
AuxE.UVD.En
18
AuxE.UVG.U_Set
19
AuxE.UVG.En
0 or 1
(0.050~30.000)In (A)
0 or 1
(0.050~30.000)In (A)
0.000~10.000 (s)
0 or 1
0~Un (V)
0 or 1
7-11
Date: 2015-10-22
7 Settings
Voltage setting for phase-to-phase under voltage
20
AuxE.UVS.U_Set
21
AuxE.UVS.En
22
AuxE.ROV.3U0_Set
0~Un (V)
23
AuxE.ROV.En
0 or 1
auxiliary element
Enable phase-to-phase under voltage auxiliary
0~Unn (V)
0 or 1
element
Item
Remark
Range
21D.Z_Set
(0.000~4Unn)/In (ohm)
21D.En
0 or 1
Item
Remark
Range
LoadEnch.phi
LoadEnch.R_Set
(0.05~200)/In (ohm)
recommended.
3
LoadEnch.En
0 or 1
Item
21-x. DirMode
21-x.Real_K0
21-x.Imag_K0
21-x.phi1_Reach
21Mx.ZG.phi_Shift
21Mx.ZP.phi_Shift
21Mx.ZG.Z_Set
21Mx.ZG.t_Op
21Mx.ZG.t_ShortDly
Remark
Range
component
of
zero-sequence
7-12
0 or 1
-4.000~4.000
-4.000~4.000
30.00~89.00 (deg)
0, 15 or 30 (deg)
0, 15 or 30 (deg)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
7 Settings
10
21Mx.ZG.En
11
21Mx.ZG.En_BlkAR
12
21Mx.ZP.Z_Set
13
21Mx.ZP.t_Op
14
21Mx.ZP.t_ShortDly
15
21Mx.ZP.En
16
21Mx.ZP.En_BlkAR
17
21Mx.En_ShortDly
0 or 1
0 or 1
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
Item
21Q.Ang_Alpha
21-x. DirMode
21-x.Real_K0
21-x.Imag_K0
21-x.phi1_Reach
21Qx.ZG.RCA
21Qx.ZG.Z_Set
21Qx.ZG.R_Set
21Qx.ZG.t_Op
10
21Qx.ZG.t_ShortDly
11
21Qx.ZG.En
12
21Qx.ZG.En_BlkAR
Remark
Range
5~30 (deg)
component
of
zero-sequence
0 or 1
-4.000~4.000
-4.000~4.000
30~89 (deg)
0~45 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
7-13
Date: 2015-10-22
7 Settings
13
21Qx.ZP.RCA
14
21Qx.ZP.Z_Set
15
21Qx.ZP.R_Set
16
21Qx.ZP.t_Op
17
21Qx.ZP.t_ShortDly
18
21Qx.ZP.En
19
21Qx.ZP.En_BlkAR
20
21Qx.En_ShortDly
0~45
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
Item
21.Pilot.Real_K0
21.Pilot.Imag_K0
21.Pilot.phi1_Reach
21M.Pilot.Z_Set
21Q.Pilot.Z_Set
21M.Pilot.Z_Rev
21Q.Pilot.Z_Rev
21Q.Pilot.R_Set
21Q.Pilot.R_Rev
Remark
Range
component
of
zero-sequence
30.00~89.00 (deg)
-4.000~4.000
-4.000~4.000
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
Item
Remark
Range
78.En
0 or 1
78.En_Trp
0 or 1
7-14
7 Settings
3
78.Z_Fwd
78.Z_Rev
78.phi1_Reach
78.phi_Start
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
30.00~89.00 (deg)
0~180 (deg)
78.phi_Trp
78.N_Limit
1~20
Item
21M1.En_PSBR
21Q1.En_PSBR
21M2.En_PSBR
21Q2.En_PSBR
21M3.En_PSBR
21Q3.En_PSBR
21M4.En_PSBR
21Q4.En_PSBR
21M5.En_PSBR
10
21Q5.En_PSBR
11
21M.Pilot.En_PSBR
12
21Q.Pilot.En_PSBR
13
21M.I_PSBR
Remark
Enable zone 1 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 1 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 2 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 2 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 3 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 3 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 4 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 4 of distance protection controlled by
PSBR (Quad characteristic)
Enable zone 5 of distance protection controlled by
PSBR (Mho characteristic)
Enable zone 5 of distance protection controlled by
PSBR (Quad characteristic)
Enable pilot distance zone controlled by PSBR (Mho
characteristic)
Enable pilot distance zone controlled by PSBR (Quad
characteristic)
Current setting for power swing blocking (Mho
characteristic)
Range
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
(0.050~30.000)In (ohm)
7-15
Date: 2015-10-22
7 Settings
14
21Q.I_PSBR
(0.050~30.000)In (ohm)
Item
Remark
Range
SOTF.t_En
21SOTF.En
0 or 1
21SOTF.Z2.En_ManCls
21SOTF.Z3.En_ManCls
21SOTF.Z4.En_ManCls
21SOTF.t_ManCls
21SOTF.Z2.En_3PAR
21SOTF.Z3.En_3PAR
21SOTF.Z4.En_3PAR
10
21SOTF.Z2.En_PSBR
11
21SOTF.Z3.En_PSBR
12
21SOTF.Z4.En_PSBR
13
21SOTF.t_3PAR
14
21SOTF.En_1PAR
15
21SOTF.t_1PAR
16
21SOTF.En_PDF
17
21SOTF.t_PDF
18
SOTF.U_Ddl
0~Unn (V)
19
SOTF.t_Ddl
0.000~600.000 (s)
7-16
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
0 or 1
0.000~10.000 (s)
0 or 1
0.000~10.000 (s)
7 Settings
ManClsBI
CBPos
20
ManClsBI/ CBPos
AutoInit
All
Item
Remark
Range
FO.LocID
0-65535
FO.RmtID
0-65535
FO.Protocol
FO.BaudRate
64 or 2048
FOx.Nx64k_C37.94
FOx.En_IntClock
0 or 1
FOx.En
Enable channel x
0 or 1
Item
Remark
Minimum
pickup
current
Range
setting
of
current
87L.I_Pkp
87L.K_Cr_CT
87L.I_Pkp_CTS
87L.XC1L
87L.XC0L
(40~60000)/In (ohm)
87L.Z_LocReac
(40~60000)/In (ohm)
87L.Z_LocGndReac
(40~60000)/In (ohm)
87L.Z_RmtReac
(40~60000)/In (ohm)
87L.Z_RmtGndReac
10
87L.En
11
87L.En_DPFC1
12
87L.En_DPFC2
13
87L.En_Biased1
14
87L.En_Biased2
15
87L.En_Neutral
differential protection
Current ratio factor of CT
Current setting of differential protection when CT
circuit failure
Positive-sequence capacitive impedance of the
line
(0.050~30.000)In (A)
0.200~10.000
(0.050~30.000)In (A)
(40~60000)/In (ohm)
(40~60000)/In (ohm)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
7-17
Date: 2015-10-22
7 Settings
16
87L.En_InterTrp
0 or 1
87L.En_LocDiff
protection
(independent
current
differential
protection
means
current
differential 0 or 1
local
87L.En_CapCurrComp
19
87L.En_CTS_Blk
0 or 1
0 or 1
Item
Remark
Range
POTT
85.Opt_PilotMode
PUTT
Blocking
Option of phase-segregated
signal scheme or
85.Opt_Ch_PhSeg
85.En_WI
0 or 1
85.U_UV_WI
0~Unn (V)
85.Z.En
0 or 1
85.En_Unblocking1
0 or 1
85.t_DPU_Blocking1
85.t_DPU_CR1
0.000~1.000 (s)
85.t_DDO_CR1
0.000~1.000 (s)
10
85.ZX.En
0 or 1
11
85.t_DPU_ZX
0 or 1
0.000~1.000 (s)
0.000~10.000 (s)
Item
85.DEF.En
85.DEF.En_BlkAR
85.DEF.En_IndepCh
85.En_Unblocking2
85.DEF.3I0_Set
85.DEF.t_DPU
Remark
Range
0 or 1
setting
of
pilot
directional
earth-fault
protection
Time delay of pilot directional earth-fault protection
7-18
0 or 1
0 or 1
0 or 1
(0.050~30.000)In (A)
0.001~10.000 (s)
7 Settings
Time delay pickup for current reversal logic when pilot
7
85.t_DPU_CR2
85.t_DDO_CR2
pilot
directional
earth-fault
protection
Item
Remark
Range
RCA_OC
RCA_ROC
RCA_NegOC
Z0_Comp
Z2_Comp
overcurrent element
The characteristic angle of directional earth fault
element
The
characteristic
angle
of
directional
compensation
impedance
setting
30.00~89.00 (deg)
30.00~89.00 (deg)
30.00~89.00 (deg)
(0.000~4Unn)/In (ohm)
(0.000~4Unn)/In (ohm)
Item
50/51P.K_Hm2
50/51P1.I_Set
50/51P1.t_Op
50/51P1.En
50/51P1.En_BlkAR
50/51P1.En_VTS_Blk
50/51P1.Opt_Dir
50/51P1.En_Hm2_Blk
Remark
Setting of second harmonic component for
blocking phase overcurrent elements
Current setting for stage 1 of phase overcurrent
protection
Time delay for stage 1 of phase overcurrent
protection
Enable stage 1 of phase overcurrent protection
Enable auto-reclosing blocked when stage 1 of
phase overcurrent protection operates
Enable stage 1 of phase overcurrent protection is
blocked by VT circuit failure
Direction option for stage 1 of phase overcurrent
protection
Range
0.000~1.000
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non-Directional
Forward
Reverse
0 or 1
7-19
Date: 2015-10-22
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
9
50/51P1.Opt_Curve
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
10
50/51P1.TMS
11
50/51P1.tmin
50/51P1.Alpha
time
for
stage
of
12
operating
for
stage
of
0.010~200.000
0.000~20.000 (s)
customized
13
50/51P1.C
for
stage
of
customized
14
50/51P1.K
for
stage
of
customized
15
50/51P2.I_Set
16
50/51P2.t_Op
17
50/51P2.En
18
50/51P2.En_BlkAR
19
50/51P2.En_VTS_Blk
20
21
50/51P2.Opt_Dir
50/51P2.En_Hm2_Blk
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non-Directional
Forward
Reverse
7-20
0 or 1
7 Settings
DefTime
IECN
IECV
IECE
IECST
22
50/51P2.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
23
50/51P2.TMS
24
50/51P2.tmin
25
50/51P3.I_Set
26
50/51P3.t_Op
27
50/51P3.En
28
50/51P3.En_BlkAR
29
50/51P3.En_VTS_Blk
30
31
50/51P3.Opt_Dir
50/51P3.En_Hm2_Blk
operating
time
for
stage
of
0.010~200.000
0.000~20.000 (s)
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non-Directional
Forward
Reverse
0 or 1
DefTime
IECN
IECV
IECE
IECST
32
50/51P3.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
7-21
Date: 2015-10-22
7 Settings
33
50/51P3.TMS
34
50/51P3.tmin
35
50/51P4.I_Set
36
50/51P4.t_Op
37
50/51P4.En
38
50/51P4.En_BlkAR
39
50/51P4.En_VTS_Blk
40
41
50/51P4.Opt_Dir
50/51P4.En_Hm2_Blk
operating
time
for
stage
of
0.010~200.000
0.000~20.000 (s)
(0.050~30.000)In (A)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non-Directional
Forward
Reverse
0 or 1
DefTime
IECN
IECV
IECE
IECST
42
50/51P4.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
43
50/51P4.TMS
44
50/51P4.tmin
operating
time
for
stage
of
0.010~200.000
0.010~20.000 (s)
Item
Remark
Range
50/51G.K_Hm2
50/51G1.3I0_Set
50/51G1.t_Op
0.000~20.000 (s)
50/51G1.En
0 or 1
7-22
0.000~1.000
7 Settings
5
50/51G1.En_BlkAR
50/51G1.Opt_Dir
50/51G1.En_Hm2_Blk
50/51G1.En_Abnor_Blk
50/51G1.En_CTS_Blk
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
IECLT
10
50/51G1.Opt_Curve
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
11
50/51G1.TMS
12
50/51G1.tmin
13
50/51G1.Alpha
14
50/51G1.C
15
50/51G1.K
16
50/51G2.3I0_Set
17
50/51G2.t_Op
18
50/51G2.t_ShortDly
19
50/51G2.En
20
50/51G2.En_ShortDly
operating
time
for
stage
of
for
stage
of
customized
for
stage
of
customized
for
stage
of
customized
0.010~200.000
0.050~20.000 (t)
0.010~5.000
0.000~20.000
0.050~20.000
0.000~20.000 (s)
0.000~20.000 (s)
0 or 1
0 or 1
7-23
Date: 2015-10-22
7 Settings
21
22
50/51G2.En_BlkAR
50/51G2.Opt_Dir
23
50/51G2.En_Hm2_Blk
24
50/51G2.En_Abnor_Blk
25
50/51G2.En_CTS_Blk
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
26
50/51G2.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
27
50/51G2.TMS
28
50/51G2.tmin
29
50/51G3.3I0_Set
30
50/51G3.t_Op
31
50/51G3.t_ShortDly
32
50/51G3.En
33
50/51G3.En_ShortDly
34
50/51G3.En_BlkAR
35
36
50/51G3.Opt_Dir
50/51G3.En_Hm2_Blk
operating
time
for
stage
of
0.010~200.000
0.050~20.000 (s)
0.000~20.000 (s)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
7-24
0 or 1
7 Settings
37
50/51G3.En_Abnor_Blk
38
50/51G3.En_CTS_Blk
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
39
50/51G3.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
40
50/51G3.TMS
41
50/51G3.tmin
42
50/51G4.3I0_Set
43
50/51G4.t_Op
44
50/51G4.t_ShortDly
45
50/51G4.En
46
50/51G4.En_ShortDly
47
50/51G4.En_BlkAR
48
50/51G4.Opt_Dir
49
50/51G4.En_Hm2_Blk
50
50/51G4.En_Abnor_Blk
51
50/51G4.En_CTS_Blk
operating
time
for
stage
of
0.010~200.000
0.050~20.000 (s)
0.000~20.000 (s)
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
0 or 1
7-25
Date: 2015-10-22
7 Settings
DefTime
IECN
IECV
IECE
IECST
52
50/51G4.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
53
50/51G4.TMS
54
50/51G4.tmin
operating
time
for
stage
of
0.010~200.000
0.050~20.000 (s)
Item
50/51Q1.I2_Set
50/51Q1.I2/I1_Set
50/51Q1.t_Op
50/51Q1.En
50/51Q1.En_BlkAR
50/51Q1.Opt_Dir
50/51Q1.En_Abnor_Blk
50/51Q1.En_CTS_Blk
Remark
Range
coefficient
(I2/I1)
for
stage
of
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
7-26
(0.050~30.000)In (A)
0 or 1
0 or 1
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
9
50/51Q1.Opt_Curve
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
10
50/51Q1.TMS
11
50/51Q1.tmin
0.010~200.000
0.050~20.000 (s)
50/51Q1.Alpha
characteristic
negative-sequence
overcurrent 0.010~5.000
protection
Constant C for stage 1 of customized inverse-time
13
50/51Q1.C
characteristic
negative-sequence
overcurrent 0.000~20.000
protection
Constant K for stage 1 of customized inverse-time
14
50/51Q1.K
characteristic
negative-sequence
overcurrent 0.050~20.000
protection
15
50/51Q2.I2_Set
16
50/51Q2.I2/I1_Set
17
50/51Q2.t_Op
18
50/51Q2.En
19
50/51Q2.En_BlkAR
20
50/51Q2.Opt_Dir
21
50/51Q2.En_Abnor_Blk
22
50/51Q2.En_CTS_Blk
coefficient
(I2/I1)
for
stage
of
(0.050~30.000)In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
7-27
Date: 2015-10-22
7 Settings
DefTime
IECN
IECV
IECE
IECST
23
50/51Q2.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
24
50/51Q2.TMS
25
50/51Q2.tmin
26
50/51Q3.I2_Set
27
50/51Q3.I2/I1_Set
28
50/51Q3.t_Op
29
50/51Q3.En
30
50/51Q3.En_BlkAR
31
50/51Q3.Opt_Dir
32
50/51Q3.En_Abnor_Blk
33
50/51Q3.En_CTS_Blk
coefficient
(I2/I1)
for
stage
of
0.050~20.000 (s)
(0.050~30.000)In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
Non_Directional
Forward
Reverse
7-28
0.010~200.000
0 or 1
0 or 1
7 Settings
DefTime
IECN
IECV
IECE
IECST
34
50/51Q3.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
35
50/51Q3.TMS
36
50/51Q3.tmin
37
50/51Q4.I2_Set
38
50/51Q4.I2/I1_Set
39
50/51Q4.t_Op
40
50/51Q4.En
41
50/51Q4.En_Trp
42
50/51Q4.En_BlkAR
43
50/51Q4.Opt_Dir
44
50/51Q4.En_Abnor_Blk
45
50/51Q4.En_CTS_Blk
coefficient
(I2/I1)
for
stage
of
0.010~200.000
0.050~20.000 (s)
(0.050~30.000)In (A)
0.00~1.00
0.000~20.000 (s)
0 or 1
0 or 1
0 or 1
Non_Directional
Forward
Reverse
0 or 1
0 or 1
7-29
Date: 2015-10-22
7 Settings
DefTime
IECN
IECV
IECE
IECST
46
50/51Q4.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
47
50/51Q4.TMS
48
50/51Q4.tmin
0.010~200.000
0.050~20.000 (s)
Item
50PVT.I_Set
50PVT.t_Op
50PVT.En
Remark
Range
(0.050~30.000)In (A)
0.000~10.000 (s)
0 or 1
DefTime
IECN
IECV
IECE
IECST
50PVT.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
50PVT.TMS
50PVT.tmin
inverse-time phase
7-30
0.010~200.000
0.000~20.000 (s)
7 Settings
Constant
7
50PVT.Alpha
for
customized
inverse-time
0.010~5.000
VT circuit failure
Constant
8
50PVT.C
for
customized
inverse-time
0.000~20.000
VT circuit failure
Constant
9
50PVT.K
for
customized
inverse-time
0.050~20.000
VT circuit failure
10
50GVT.3I0_Set
11
50GVT.t_Op
12
50GVT.En
(0.050~30.000)In (A)
0.000~10.000 (s)
0 or 1
DefTime
IECN
IECV
IECE
IECST
50GVT.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
14
50GVT.TMS
15
50GVT.tmin
16
50GVT.Alpha
characteristic
for
customized
ground
0.010~200.000
0.000~20.000 (s)
inverse-time
overcurrent
protection
0.010~5.000
50GVT.C
characteristic
for
customized
ground
inverse-time
overcurrent
protection
0.000~20.000
50GVT.K
characteristic
for
customized
ground
inverse-time
overcurrent
protection
0.050~20.000
7-31
Date: 2015-10-22
7 Settings
Item
Remark
Range
50PSOTF.I_Set
(0.050~30.000)In (A)
50PSOTF.t_Op
0.000~10.000 (s)
50PSOTF.Up_Set
50PSOTF.Upp_Set
50PSOTF.U2_Set
50PSOTF.3U0_Set
50PSOTF.En
50PSOTF.En_Up_UV
50PSOTF.En_Upp_UV
10
50PSOTF.En_U2_OV
11
50PSOTF.En_3U0_OV
(0~1) Un (V)
(0~1) Un (V)
(0~1) Un (V)
(0~1) Un (V)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Item
50GSOTF.3I0_Set
50GSOTF.t_Op_3P
50GSOTF.t_Op_1P
50GSOTF.En
50GSOTF.En_Hm2_Blk
Remark
Current
setting
of
residual
Range
current
SOTF
protection
Time delay for residual current SOTF protection
when 3 pole closed
Time delay for residual current SOTF protection
when 1 pole closed
Enable residual current SOTF protection
(0.050~30.000)In (A)
0.000~10.000 (s)
0.000~10.000 (s)
0 or 1
0 or 1
Item
59Px.U_Set
59Px.t_Op
59Px.En
Remark
Range
7-32
Un~2Unn (V)
0.000~30.000 (s)
0 or 1
7 Settings
4
59Px.Opt_1P/3P
59Px.Opt_Up/Upp
59Px.En_Alm
59Px.En_52b_TT
59Px.En_TT
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
DefTime
IECN
IECV
IECE
IECST
59Px.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
10
59Px.TMS
11
59Px.tmin
0.010~200.000
0.050~20.000 (s)
Item
59Q.U_Set
59Q.t_Op
59Q.En
Remark
Range
delay
for
negative-sequence
overvoltage
protection
Enable negative-sequence overvoltage protection
0~Un (V)
0.000~30.000 (s)
0 or 1
Item
59G1.3U0_Set
59G1.t_Op
59G1.En
Remark
Voltage setting of stage 1 of residual overvoltage
protection.
Time delay of stage 1 of residual overvoltage
protection.
Enable stage 1 of residual overvoltage protection.
Range
2.000~200.000 (V)
0.000~3600.000 (s)
0 or 1
7-33
Date: 2015-10-22
7 Settings
4
59G2.3U0_Set
59G2.t_Op
59G2.tmin
59G2.TMS
59G2.K
59G2.C
10
59G2.Alpha
2.0000~200.000 (V)
0.000~3600.000 (s)
0.000~20.000 (s)
0.050~3.200
0.000~120.000
0.000~20.000
0.020~5.000
DefTime
IECN
IECV
IECE
IECST
IECLT
11
59G2.Opt_Curve
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
12
59G2.En
13
59G3.3U0_Set
14
59G3.t_Op
15
59G3.tmin
16
59G3.TMS
17
59G3.K
18
59G3.C
19
59G3.Alpha
7-34
0 or 1
2.0000~200.000 (V)
0.000~3600.000 (s)
0.000~20.000 (s)
0.050~3.200
0.000~120.000
0.000~20.000
0.020~5.000
7 Settings
DefTime
IECN
IECV
IECE
IECST
IECLT
20
59G3.Opt_Curve
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
UserDefine
21
59G3.En
22
59G3.En_Trp
0 or 1
0 or 1
Item
27Px.U_Set
27Px.t_Op
27Px.En
27Px.En_FD_Ctrl
27Px.En_Curr_Ctrl
27Px.En_VTS_Blk
27Px.Opt_1P/3P
Remark
Voltage setting for stage x of undervoltage protection
(x=1, 2, 3)
Time delay for stage x of undervoltage protection
(x=1, 2, 3)
Enable stage x of undervoltage protection (x=1, 2, 3)
Enable stage x of undervoltage protection controlled
by FD element reflecting current (x=1, 2, 3)
Enable stage x of undervoltage protection controlled
by current condition (x=1, 2, 3)
Enable stage x of undervoltage protection controlled
by VT circuit failure (x=1, 2, 3)
Option of 1-out-of-3 mode or 3-out-of-3 mode for
stage x of undervoltage protection (x=1, 2, 3)
Range
0~Unn (V)
0.000~30.000 (s)
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
27Px.Opt_Up/Upp
27Px.En_Alm
0 or 1
7-35
Date: 2015-10-22
7 Settings
DefTime
IECN
IECV
IECE
IECST
10
27Px.Opt_Curve
IECLT
ANSIE
ANSIV
ANSI
ANSIM
ANSILTE
ANSILTV
ANSILT
11
27Px.TMS
12
27Px.tmin
delay
for
stage
of
inverse-time
0.010~200.000
0.050~20.000 (s)
Item
Remark
Range
81O.f_Pkp
81O.OF1.f_Set
81O.OF1.t_Op
0.050~20.000 (s)
81O.OF1.En
0 or 1
81O.OF2.f_Set
81O.OF2.t_Op
0.050~20.000 (s)
81O.OF2.En
0 or 1
81O.OF3.f_Set
81O.OF3.t_Op
0.050~20.000 (s)
10
81O.OF3.En
0 or 1
11
81O.OF4.f_Set
12
81O.OF4.t_Op
0.050~20.000 (s)
13
81O.OF4.En
0 or 1
14
81U.f_Pkp
15
81U.df/dt_Blk
16
81U.UF1.f_Set
Frequency
pickup
setting
for
underfrequency
protection
Rate
of
frequency
change
for
blocking
underfrequency protection
Frequency setting for stage 1 of underfrequency
protection
7-36
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
50.000~65.000 (Hz)
45.000~60.000 (Hz)
0.200~20.000 (Hz/s)
45.000~60.000 (Hz)
7 Settings
17
81U.UF1.t_Op
0.050~30.000 (s)
18
81U.UF1.En
0 or 1
19
81U.UF1.En_df/dt_Blk
20
81U.UF2.f_Set
21
81U.UF2.t_Op
0.050~30.000 (s)
22
81U.UF2.En
0 or 1
23
81U.UF2.En_df/dt_Blk
24
81U.UF3.f_Set
25
81U.UF3.t_Op
0.050~30.000 (s)
26
81U.UF3.En
0 or 1
27
81U.UF3.En_df/dt_Blk
28
81U.UF4.f_Set
29
81U.UF4.t_Op
0.050~30.000 (s)
30
81U.UF4.En
0 or 1
31
81U.UF4.En_df/dt_Blk
0 or 1
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
0 or 1
45.000~60.000 (Hz)
0 or 1
Item
Remark
Range
(0.050~30.000 )In (A)
CBx.50BF.I_Set
CBx.50BF.3I0_Set
CBx.50BF.I2_Set
CBx.50BF.t_ReTrp
0.000~10.000 (s)
CBx.50BF.t1_Op
0.000~10.000 (s)
CBx.50BF.t2_Op
0.000~10.000 (s)
CBx.50BF.En
0 or 1
CBx.50BF.En_ReTrp
0 or 1
CBx.50BF.En_3I0_1P
7-37
Date: 2015-10-22
7 Settings
10
CBx.50BF.En_3I0_3P
11
CBx.50BF.En_I2_3P
12
CBx.50BF.En_CB_Ctrl
Item
Remark
Range
49-1.K
49-2.K
49.Ib_Set
49.Tau
49-1.En_Alm
49-1.En_Trp
49-2.En_Alm
49-2.En_Trp
Name
Remark
Pickup
current
setting
of
Range
stub
differential
87STB.I_Pkp
87STB.I_ Alm
(0.050~30.000)In (A)
87STB.Slope
0.5~1
87STB.t_Op
0.000~10.000 (s)
87STB.En
0 or 1
87STB.En_Alm
0 or 1
87STB.En_CTS_Blk
protection
(0.050~30.000)In (A)
0 or 1
7-38
7 Settings
No.
Name
Remark
Range
CBx.50DZ.I_Set
(0.050~30.000)In (A)
CBx.50DZ.t_Op
0.000~10.000 (s)
CBx.50DZ.En
0 or 1
Item
Remark
Range
CBx.62PD.3I0_Set
CBx.62PD.I2_Set
CBx.62PD.t_Op
0.000~600.000 (s)
CBx.62PD.En
0 or 1
discrepancy protection
Current
setting
CBx.62PD.En_3I0/I2_Ctrl
negative-sequence
current
Enable
5
of
residual
negative-sequence
current
current
criterion
criterion
for
and
pole 0 or 1
discrepancy protection
Item
Remark
Ratio
46BC.I2/I1_Set
setting
(negative-sequence
Range
current
to
46BC.t_Op
46BC.I_Min
46BC.En_Trp
46BC.En_Alm
0.000~600.000 (s)
protection
Enable broken conductor protection to operate to
0 or 1
trip
Enable broken conductor protection to operate to
0 or 1
alarm
Item
Remark
Range
32R1.P_Set
32R1.t_Alm
32R1.t_Trp
(0.100~50.000)In (W)
protection
Time delay of stage 1 of reverse power protection
for alarm purpose
0.100~3000.000 (s)
0.100~3000.000 (s)
7-39
Date: 2015-10-22
7 Settings
Enable stage 1 of reverse power protection to
32R1.En_Trp
32R1.En_Alm
32R2.P_Set
32R2.t_Trp
32R2.En_Trp
32R.Opt_Dir
0 or 1
operate to trip
Enable stage 1 of reverse power protection to
0 or 1
operate to alarm
Power setting of stage 2 of reverse power
(0.100~50.000)In (W)
protection
operate to trip
The
directionality
option
of
protection
reverse
Item
Remark
Range
Ua
Ub
CBx.25.Opt_Source_UL1
Uc
Uab
Ubc
Uca
Ua
Ub
Uc
Uab
Ubc
Uca
Ua
Ub
CBx.25.Opt_Source_UL2
Uc
Uab
Ubc
Uca
Ua
Ub
Uc
Uab
Ubc
Uca
7-40
7 Settings
NoVoltSel
Option of circuit breaker configuration, and it should
5
CBx.CBConfigMode
DblBusOneCB
3/2BusCB
adopted.
3/2TieCB
6
CBx.25.U_Dd
0.05Un~0.8Un (V)
CBx.25.U_Lv
0.5Un~Un (V)
CBx.25.K_Usyn
0.20-5.00
CBx.25.phi_Diff
0~ 89 (deg)
10
CBx.25.phi_Comp
11
CBx.25.f_Diff
12
CBx.25.U_Diff
0.02Un~0.8Un (V)
13
CBx.25.t_DdChk
0.010~25.000 (s)
14
CBx.25.t_SynChk
0.010~25.000 (s)
15
CBx.25.En_fDiffChk
0 or 1
16
CBx.25.SetOpt
0, 1
17
CBx.25.En_SynChk
0 or 1
18
CBx.25.En_DdL_DdB
0 or 1
19
CBx.25.En_DdL_LvB
0 or 1
20
CBx.25.En_LvL_DdB
0 or 1
21
CBx.25.En_NoChk
0 or 1
22
CBx.25.En_3PLvChk
0 or 1
synchronism voltages
Frequency difference limit of synchronism check for
AR
0~359 (deg)
0.02~1.00 (Hz)
Item
Remark
Range
CBx.79.N_Rcls
1~4
CBx.79.t_Dd_1PS1
0.000~600.000 (s)
CBx.79.t_Dd_3PS1
0.000~600.000 (s)
CBx.79.t_Dd_3PS2
0.000~600.000 (s)
CBx.79.t_Dd_3PS3
0.000~600.000 (s)
CBx.79.t_Dd_3PS4
0.000~600.000 (s)
CBx.79.t_CBClsd
0.000~600.000 (s)
7-41
Date: 2015-10-22
7 Settings
Time delay to wait for CB healthy, and begin to timing
8
CBx.79.t_CBReady
when
the
input
signal
[79.CB_Healthy]
is
0.000~600.000 (s)
CBx.79.t_Wait_Chk
0.000~600.000 (s)
10
CBx.79.t_Fail
11
CBx.79.t_PW_AR
0.000~600.000 (s)
12
CBx.79.t_Reclaim
Reclaim time of AR
0.000~600.000 (s)
13
CBx.79.t_PersistTrp
reclosing successful
0.000~600.000 (s)
0.000~600.000 (s)
CBx.79.t_DDO_BlkAR
15
CBx.79.t_AddDly
16
CBx.79.t_WaitMaster
0.000~600.000 (s)
0.000~600.000 (s)
CBx.79.t_SecFault
18
CBx.79.En_PDF_Blk
19
CBx.79.En_AddDly
20
CBx.79.En_CutPulse
21
CBx.79.En_FailCheck
22
CBx.79.En
23
CBx.79.En_ExtCtrl
24
CBx.79.En_CBInit
25
CBx.79.Opt_Priority
Option of AR priority
26
CBx.79.SetOpt
0 or 1
27
CBx.79.En_1PAR
0 or 1
28
CBx.79.En_3PAR
0 or 1
29
CBx.79.En_1P/3PAR
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
Item
TT.t_Op
Remark
Time delay of transfer trip
7-42
Range
0.000~600.000 (s)
7 Settings
2
TT.En_FD_Ctrl
0 or 1
Item
En_MPF_Blk_AR
En_3PF_Blk_AR
En_PhSF_Blk_AR
CBx.En_Trp3P
t_Dwell_Trp
Remark
Range
0 or 1
0 or 1
0 or 1
0 or 1
0.000~10.000 (s)
Item
Remark
Range
VTS.t_DPU
0.200~100.000
VTS.t_DDO
0.200~100.000
VTS.En_Out_VT
0 or 1
If
three-phase
voltage
used
for
protection
VTS.En_LineVT
VTS.En
0 or 1
7-43
Date: 2015-10-22
7 Settings
Item
Remark
Range
Link_01
0 or 1
Link_02
0 or 1
Link_03
0 or 1
Link_04
0 or 1
Link_05
0 or 1
Link_06
0 or 1
Link_07
0 or 1
Link_08
0 or 1
Item
MCBrd.CBx.En_Alm_VTS
Remark
Range
0 or 1
Item
Remark
Range
Ua
Ub
MCBrd.CBx.25.Opt_Source_UL1
Uc
Uab
Ubc
Uca
7-44
7 Settings
Ua
Ub
2
MCBrd.CBx.25.Opt_Source_UB1
Uc
Uab
Ubc
Uca
Ua
Ub
MCBrd.CBx.25.Opt_Source_UL2
Uc
Uab
Ubc
Uca
Ua
Ub
MCBrd.CBx.25.Opt_Source_UB2
Uc
Uab
Ubc
Uca
MCBrd.CBx.25.U_Dd
1.000~100.000 (V)
MCBrd.CBx.25.U_Lv
1.000~100.000 (V)
MCBrd.CBx.25.K_Usyn
MCBrd.CBx.25.phi_Diff
MCBrd.CBx.25.phi_Comp
10
MCBrd.CBx.25.f_Diff
11
MCBrd.CBx.25.U_Diff
12
MCBrd.CBx.25.SetOpt
13
MCBrd.CBx.25.En_SynChk
14
MCBrd.CBx.25.En_DdL_DdB
15
MCBrd.CBx.25.En_DdL_LvB
16
MCBrd.CBx.25.En_LvL_DdB
17
MCBrd.CBx.25.En_NoChk
18
MCBrd.CBx.25.df/dt
for
phase
difference
0.20-5.00
0~360 (deg)
0.00~3.00 (Hz)
1.000~100.000 (V)
0, 1
0 or 1
0 or 1
0 or 1
0 or 1
0 or 1
both
sides
of
CB
synchronism-check.
PCS-931 Line Differential Relay
7-45
Date: 2015-10-22
7 Settings
Circuit breaker closing time. It is the time
19
MCBrd.CBx.25.t_Close_CB
20
MCBrd.CBx.25.t_Wait_Chk
21
MCBrd.CBx.25.En_VTS_Blk_SynChk
Enable
block
manual
closing
synchronism
when
VT
check
circuit
for
is 0 or 1
abnormal
22
MCBrd.CBx.25.En_VTS_Blk_DdChk
0 or 1
Name
Remark
Range
CSWIxx.t_DPU_DPS
0~60000 (ms)
Name
Remark
Range
CSWIxx.t_PW_Opn
0~60000 (ms)
(xx=01, 02.10)
No.xx closing time of a normal open contact of
2
CSWIxx.t_PW_Cls
0~60000 (ms)
(xx=01, 02.10)
7-46
7 Settings
Name
Remark
Range
CSWIxx.En_Opn_Blk
0 or 1
(xx=01, 02.10)
Enable No.xx closing output of the BO module be
2
CSWIxx.En_Cls_Blk
0 or 1
(xx=01, 02.10)
7-47
Date: 2015-10-22
7 Settings
7-48
8-a
Date: 2015-05-25
List of Figures
Figure 8.1-1 Front panel .............................................................................................................. 8-1
Figure 8.1-2 Keypad buttons ...................................................................................................... 8-2
Figure 8.1-3 LED indications ...................................................................................................... 8-3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel .................................. 8-4
Figure 8.1-5 Rear view and terminal definition of NR1102D ................................................... 8-5
Figure 8.2-1 Menu tree ................................................................................................................ 8-7
List of Tables
Table 8.1-1 Definition of the 8-core cable ................................................................................. 8-4
Table 8.3-1 Tripping report messages ..................................................................................... 8-35
Table 8.3-2 User operating event list ....................................................................................... 8-37
8-b
The operator can access the protective device from the front panel. Local communication with the
protective device is possible using a computer via a multiplex RJ45 port on the front panel.
Furthermore, remote communication is also possible using a PC with the substation automation
system via rear RS485 port or rear Ethernet port. The operator is able to check the protective
device status at any time.
This chapter describes human machine interface (HMI), and give operator an instruction about
how to display or print event report, setting and so on through HMI menu tree and display metering
value, including r.m.s. current, voltage and frequency etc. through LCD. Procedures to change
active setting group or a settable parameter value through keypad is also described in details.
NOTICE!
About the measurements and metering in menu Measurements, please refer to the
following description:
Measurements1 is used to display measured values from protection calculation DSP.
The measurement values can be displayed in primary value or secondary value by the
setting [Opt_Display_Status].
Measurements2 is used to display measured values from fault detector DSP. The
measurement values can be displayed in primary value or secondary value by the
setting [Opt_Display_Status].
Measurements3 is used to display measured values of other calculated quantities
related to the measurement and control. The measurement values are always
displayed in primary value.
Metering is used to display metering values of active and reactive energy. The
metering values are always displayed in primary value.
8.1 Overview
The human-machine interface consists of a human-machine interface (HMI) module which allows
a communication to be as simple as possible for the user.
5
11
PCS-931
12
ALARM
13
14
15
16
17
18
19
10
20
GRP
HEALTHY
ESC
ENT
3
4
8-1
Date: 2015-05-25
The HMI module helps to draw your attention to something that has occurred which may activate a
LED or a report displayed on the LCD. Operator can locate the data of interest by navigating the
keypad. The function of HMI module:
No.
Item
Description
A 320240 dot matrix backlight LCD display is visible in dim lighting
LCD
LED
Keypad
Communication port
Logo
GR
P
ENT
ESC
1.
2.
3.
ESC:
ENT:
GRP
4.
5.
8-2
6.
Page up/down
Display
Off
HEALTHY
Steady Green
Off
Description
When the equipment is out of service or any hardware error is defected during
self-check.
Lit when the equipment is in service and ready for operation.
When equipment in normal operating condition.
ALARM
Steady Yellow
Lit when VT circuit failure, CT circuit failure or other abnormal alarm is issued.
NOTICE!
HEALTHY LED can only be turned on by energizing the device and no abnormality
detected.
ALARM LED is turned on when abnormalities of device occurs like above mentioned
and can be turned off after abnormalities are removed except alarm report [CTS.Alm]
which can only be reset only when the failure is removed and the device is rebooted or
re-energized.
Other LED indicators with no labels are configurable and user can configure them to be lit
by signals of operation element, alarm element and binary output contact according to
requirement through PCS-Explorer software, but as drawn in figure, 2 LEDs are fixed as
the signals of HEALTHY (green) and ALARM (yellow), 18 LEDs are configurable with
selectable color among green, yellow and red.
8-3
Date: 2015-05-25
P2
P1
P3
Figure 8.1-4 Corresponding cable of the RJ45 port in the front panel
Core color
Function
Device side
Computer side
(Left)
(Right)
P1-1
P2-1
Orange
P1-2
P2-2
P1-3
P2-3
Blue
P1-4
P3-2
P1-5
P3-3
Green
P1-6
P2-6
Brown
P1-7
P1-8
P3-5
must be established. Through setting the IP address and subnet mask of corresponding Ethernet
interface in the menu SettingsDevice SetupComm Settings, it should be ensured that the
protection device and PC are in the same network segment. For example, setting the IP address
and subnet mask of network A. (using network A to connect with PC)
PC: IP address is set as 198.87.96.102, subnet mask is set as 255.255.255.0
The IP address and subnet mask of protection device should be [IP_LAN1]= 198.87.96.XXX,
[Mask_LAN1]=255.255.255.0, [En_LAN1]=1. (XXX can be any value from 0 to 255 except 102)
If the logic setting [En_LAN1] is non-available, it means that network A is always enabled.
NR1102D
ETHERNET
Network A
Network B
Network C
Network D
NOTICE!
If using other Ethernet port, for example, Ethernet B, the logic setting [En_LAN2] must
be set as 1.
8-5
Date: 2015-05-25
Press to enter the main menu with the interface as shown in the following diagram:
MainMenu
Language
Clock
Quick Menu
For the first powered device, there is no record in quick menu. Press to enter the main menu
with the interface as shown in the following diagram:
Measurements
Status
Records
Settings
Print
Local Cmd
Information
Test
Clock
Language
The descriptions about menu are based on the maximized configuration, for a specific project, if
some function is not available, the corresponding submenu will hidden.
8-6
Measurements
Status
Records
Settings
Local Cmd
Information
Test
Clock
Language
Under main interface, press to enter main menu, and select submenu by pressing ,
and ENT. The command menu adopts a tree shaped content structure. The above diagram
provides the integral structure and all main menus (first-level menus) under menu tree of the
device.
Measurements
Measurements1
Measurements2
Measurements3
Metering
This menu is used to display real-time measured values, including AC voltage, AC current, phase
angle and calculated quantities. These data can help users to acquaint the devices status. This
menu comprises following submenus. Please refer to section Measurement about the detailed
measured values.
PCS-931 Line Differential Relay
8-7
Date: 2015-05-25
Item
Function description
Measurements1
Measurements2
Measurements3
Metering
8.2.3.2 Status
Main Menu
Status
Inputs
Outputs
Superv State
This menu is used to display real time input signals, output signals and alarm signals of the device.
These data can help users to acquaint the devices status. This menu comprises following
submenus. Please respectively refer to section Signal List about the detailed introduction of input
signals and output signals, and section Supervision Alarms about the detailed introduction of
alarm signals.
No.
Item
Function description
Inputs
Outputs
Superv State
Status
Inputs
Contact Inputs
GOOSE Inputs
Prot Ch Inputs
No.
1
Item
Contact Inputs
Function description
Display states of binary inputs derived from opto-isolated channels
8-8
GOOSE Inputs
Prot Ch Inputs
Status
Outputs
Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs
No.
Item
Function description
Contact Outputs
GOOSE Outputs
Interlock Status
Prot Ch Outputs
Status
Superv State
Prot Superv
FD Superv
GOOSE Superv
SV Superv
BCU Superv
No.
Item
Function description
Prot Superv
FD Superv
8-9
Date: 2015-05-25
GOOSE Superv
SV Superv
BCU Superv
8.2.3.3 Records
Main Menu
Records
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
This menu is used to display all kinds of records, including the disturbance records, supervision
events, binary events and device logs, so that the operator can load to view and use as the
reference of analyzing accidents and repairing the device. All records are stored in non-volatile
memory, it can still record them even if it loses its power.
This menu comprises the following submenus.
No.
Item
Function description
Disturb Records
Superv Events
IO Events
Device Logs
Control Logs
Clear Records
8.2.3.4 Settings
Main Menu
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
8-10
This menu is used to check the device setup, system parameters, protection settings and logic
links settings, as well as modifying any of the above setting items. Moreover, it can also execute
the setting copy between different setting groups.
This menu comprises the following submenus.
No.
Item
Function description
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
Check or modify the logic links settings, including function links, SV links,
GOOSE links and spare links
Check or modify the device setup
Settings
Prot Settings
Line Settings
BFP Settings
FD Settings
Deadzone Settings
AuxE Settings
OV Settings
Direction Settings
UV Settings
NegOV Settings
DiffP Settings
ThOvld Settings
PD Settings
Stub Settings
LoadEnch Settings
FreqProt Settings
Dist Settings
OOS Settings
ROC Settings
MiscProt Settings
NegOC Settings
VTS/CTS Settings
SOTF Settings
OC Settings
VTF OC Settings
RevPower Settings
Copy Settings
BRC Settings
8-11
Date: 2015-05-25
No.
Item
Function description
Line Settings
FD Settings
AuxE Settings
Direction Settings
DiffP Settings
LoadEnch Settings
10
Dist Settings
11
ROC Settings
12
NegOC Settings
13
SOTF Settings
14
OC Settings
15
VTF OC Settings
16
RevPower Settings
17
BRC Settings
18
BFP Settings
19
Deadzone Settings
20
OV Settings
21
UV Settings
22
NegOV Settings
23
ThOvld Settings
24
PD Settings
25
Stub Settings
26
FreqProt Settings
27
OOS Settings
28
MiscProt Settings
29
VTS/CTS Settings
30
31
32
8-12
Copy Settings
Settings
BCU Settings
FUN Settings
CB1 Syn Settings
CB2 Syn Settings
BI Settings
Control Settings
Interlock Settings
No.
Item
Function description
FUN Settings
BI Settings
Control Settings
Interlock Settings
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
No.
1
Item
Function Links
Function description
Check or modify function links settings
8-13
Date: 2015-05-25
SV Links
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
No.
Item
Function description
Device Settings
Comm Settings
Label Settings
8.2.3.5 Print
Main Menu
Device Info
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Waveforms
IEC103 Info
Cancel Print
This menu is used to print device description, settings, all kinds of records, waveforms, information
8-14
Item
Device Info
Function description
Print the description information of the device, including software
version.
Print device setup, system parameters, protection settings and logic
Settings
Disturb Records
Superv Events
IO Events
Prot Ch Superv
Prot Ch Statistics
Device Status
Waveforms
Print the statistic report of optical fibre channel, which is formed A.M.
9:00 every day
Print the current state of the device, including the sampled value of
voltage and current, the state of binary inputs, setting and so on
Print the recorded waveforms
Print 103 Protocol information, including function type (FUN),
10
IEC103 Info
11
Cancel Print
8-15
Date: 2015-05-25
Settings
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
Latest Chgd Settings
No.
Item
Function description
System Settings
Prot Settings
BCU Settings
Logic Links
Device Setup
All Settings
8-16
Settings
Prot Settings
Line Settings
BFP Settings
FD Settings
Deadzone Settings
AuxE Settings
OV Settings
Direction Settings
UV Settings
NegOV Settings
DiffP Settings
ThOvld Settings
PD Settings
Stub Settings
LoadEnch Settings
FreqProt Settings
Dist Settings
OOS Settings
ROC Settings
MiscProt Settings
NegOC Settings
VTS/CTS Settings
SOTF Settings
OC Settings
VTF OC Settings
RevPower Settings
All Settings
BRC Settings
No.
Item
Function description
Line Settings
FD Settings
AuxE Settings
Direction Settings
DiffP Settings
LoadEnch Settings
10
Dist Settings
11
ROC Settings
8-17
Date: 2015-05-25
NegOC Settings
13
SOTF Settings
14
OC Settings
15
VTF OC Settings
16
RevPower Settings
17
BRC Settings
18
BFP Settings
19
Deadzone Settings
20
OV Settings
21
UV Settings
22
NegOV Settings
23
ThOvld Settings
24
PD Settings
25
Stub Settings
26
FreqProt Settings
27
OOS Settings
28
MiscProt Settings
29
VTS/CTS Settings
30
31
32
33
All Settings
8-18
Settings
BCU Settings
FUN Settings
CB1 Syn Settings
CB2 Syn Settings
BI Settings
Control Settings
Interlock Settings
All Settings
No.
Item
Function description
FUN Settings
BI Settings
Control Settings
Interlock Settings
All Settings
8-19
Date: 2015-05-25
Settings
Logic Links
Function Links
GOOSE Send Links
GOOSE Recv Links
SV Links
All Settings
No.
Item
Function description
Function Links
SV Links
All Settings
Settings
Device Setup
Device Settings
Comm Settings
Label Settings
All Settings
No.
Item
Function description
Device Settings
Comm Settings
Label Settings
8-20
All Settings
Prot Ch Superv
Channel 1
Channel 2
No.
Item
Channel 1
Channel 2
Function description
Print the self-check information of optical fibre channel 1, which is made of some
hexadecimal characters and used to developer analyze channel state
Print the self-check information of optical fibre channel 2, which is made of some
hexadecimal characters and used to developer analyze channel state
Prot Ch Statistics
Channel 1
Channel 2
No.
Item
Channel 1
Channel 2
Function description
Print the statistic report of optical fibre channel 1, which is formed A.M. 9:00 every
day
Print the statistic report of optical fibre channel 2, which is formed A.M. 9:00 every
day
8-21
Date: 2015-05-25
Waveforms
Wave
No.
1
Item
Function description
Wave
Local Cmd
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
Clear CB1 AR Counter
Clear CB2 AR Counter
Clear Energy Counter
This menu is used to reset the tripping relay with latch, indicator LED, LCD display, and as same
as the reset function of binary inputs. This menu provides a method of manually recording the
current waveform data of the device under normal condition for printing and uploading SAS.
Besides, it can send out the request of program download, clear statistic information about
GOOSE, SV, AR, FO channel and energy.
This menu comprises the following submenus.
No.
Item
Function description
Reset Target
Trig Oscillograph
Control
Download
Clear Counter
8-22
8.2.3.7 Information
Main Menu
Information
Version Info
Board Info
In this menu, LCD can display software information of all kinds of intelligent plug-in modules,
which consists of version, creating time of software, CRC codes and management sequence
number. Besides, plug-in module information can also be viewed.
This menu comprises the following command menus.
No.
Item
Function description
Display software information of DSP module, MON module and HMI module,
Version Info
Board Info
8.2.3.8 Test
Main Menu
Test
Prot Ch Counter
GOOSE Comm Counter
SV Comm Counter
Device Test
Internal Signal
AR Counter
This menu is mainly used for developers to debug the program and for engineers to maintain the
device. It can be used to fulfill the communication test function. It is also used to generate all kinds
of reports or events to transmit to the SAS without any external input, so as to debug the
communication on site. Besides, it can also display statistic information about GOOSE, SV, AR
and FO channel.
8-23
Date: 2015-05-25
Item
Function description
Prot Ch Counter
SV Comm Counter
Device Test
Internal Signal
AR Counter
Check AR counters
Test
Prot Ch Counter
Ch1 Counter
Ch2 Counter
No.
Item
Function description
Ch1 Counter
Ch2 Counter
Test
Device Test
Disturb Events
Superv Events
IO Events
No.
1
Item
Disturb Events
Function description
View the relevant information about disturbance records (only used for
8-24
Superv Events
IO Events
View the relevant information about supervision events (only used for
debugging persons)
View the relevant information about binary events (only used for debugging
persons)
Users can respectively execute the test automatically or manually by selecting commands All
Test or Select Test.
The submenu Disturb Events comprises the following command menus.
Main Menu
Test
Device Test
Disturb Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
Test
Device Test
Superv Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
8-25
Date: 2015-05-25
Test
Device Test
IO Events
All Test
Select Test
No.
Item
Description
All Test
Select Test
Test
AR Counter
CB1 AR Counter
CB2 AR Counter
No.
Item
Function description
CB1 AR Counter
CB2 AR Counter
8.2.3.9 Clock
The current time of internal clock can be viewed here. The time is displayed in the form
YY-MM-DD and hh:mm:ss. All values are presented with digits and can be modified.
8.2.3.10 Language
This menu is mainly used to set LCD display language.
8-26
allow each user to own different password (user password can support 8 characters at most and
must include one lowercase letter, one capital letter and one number at least) and access authority
(such as modify settings, view records, remote control)
According to different access authority, the corresponding operations to the device by LCD panel
can be allowed to perform. For the operation that requires authorization, the corresponding user
logs in and the correct password must be input after the operation can be performed.
Press the to enter the main menu, the following interface will be shown when performing
an operation. (Multi-users have been configured in advance)
2.
Press the or to select username, and press the ESC to exit this menu
Username
Setting
Password
3.
Press the ENT or to move, and the following interface will be shown after the username
is confirmed.
8-27
Date: 2015-05-25
Username
Password
Setting
******
0 1 2 3 4 5 6 7 8 9
[OK]
4.
Press the or to select number or letter, and press ENT to ensure selected character.
5.
Press the or to page up/down to select previous group or next group characters.
6.
7.
When the password reaches to 8 bits, the device will verify whether the username and
password are correctly. If the password is shorter than 8 bits, select and press OK to begin
to verify whether the username and password are correctly.
8.
Press the ESC to cancel entered character during entering password, and the password will
be cleared if the password check fails. When the password is cleared, press the ESC to
select the username again.
9.
The device provides the function of password memory, the following interface will be shown if
the valid time of the password is set and last entered password is no timeout.
Username
Setting
Password
*******
10. Press the ENT to verify the password, press the or to switch the username and the
8-28
password will be cleared, and press the ESC to exit the interface.
11. If the password is correct and the user owns the authority of the operation performed, the
operation will be performed.
If the password is incorrect, the device will issue an alarm signal Password Error. If the password
is correct but the user has no the authority of the operation performed, the device will issue an
alarm signal Unauthorized. If the password is incorrect or the user has no the authority of the
operation performed more than three times, the device will issue an alarm signal PWD Error or
Unauthorized, Screen Locked and the device will return to main interface after the screen is
locked for 1 minutes, which will be recorded in device log.
Right-click the menu LCD Graph, and select the menu item Edit Shortcut Key to display
the configuration interface of function key shortcuts as shown below.
2.
In configuration interface, double-click the table item in the list of Extend Command to select
LCD extend command of dropdown list corresponding with keypads in front panel as shown
8-29
Date: 2015-05-25
below. Select the first blank item in dropdown list to cancel the setup.
3.
Double-click the table item in the list of Attribute to edit the attribute of keypad in front panel
as shown below. When the attribute is set as 1, the corresponding operation can not excute
unless input correct password. When the attribute is set as 0 or blank, password is not
required. After finishing configuration, click the button OK.
4.
The name description of extend command can be modified in signal setup interface, the
operation Refresh in the interface of Source must be excute at first before configuring
function shortcuts key or generating drive file package.
8-30
5.
Right-click device node and excute the menu Compress Driver File to generate drive file
package of the device. The file LCDConfig.txt in drive file package of the device records
related contents about shortcuts key. If shortcuts keys are not required, set Extend
Command corresponding with function shortcuts key as blank, and generate drive file
package of the device again.
8-31
Date: 2015-05-25
Shortcut keys
[
Extended_Command04
Extended_Command05
Extended_Command06
Extended_Command07
[ + ]
Extended_Command08
Extended_Command09
[ ENT ]
Extended_Command10
Password:
000
Under the interface of function shortcuts key, press a shortcuts key to excute corresponding
operation. If the attribute of the extend command is set as 1, the corresponding operation can not
excute unless input correct password. The extend command excuted by shortcuts key outputs a
pulse signal with 500ms, and for the operation requiring latching signal, the device provides
T_FF and RS_FF to fulfill the application, which can be configured by PCS-Explorer.
8-32
complete the initialization of the device. During the initialization of the device, the HEALTHY
indicator lamp of the device goes out.
The device can display single line diagram (SLD) and primary operation information, it can support
wiring configuration function. LCD configuration file can be downloaded via the network. Remote
control operation through single line diagram is also supported.
Under normal condition, LCD will display the following interface. LCD adopts white color as its
backlight that is activated if once there is any keyboard operation, moreover, the backlight will be
extinguished automatically if no keyboard operation is detected for a duration.
2010-06-08 10:10:00
Ia
0.00A
Ib
0.00A
Ic
0.00A
3I0
0.00A
Ua
0.02V
Ub
0.00V
Uc
0.00V
3U0
0.02V
U_Syn
0.00V
50.00Hz
Addr 24343
Group 01
The content displayed on the screen contains: the current date and time of the device (with a
format of yyyy-mm-dd hh:mm:ss:), the active setting group number, three-phase current sampling
value, residual current sampling value, three-phase voltage sampling value, residual voltage
sampling value, the synchronism voltage sampling value, line frequency and the address relevant
to IP address of Ethernet A. If all the sampling values of the voltage and the current cant be fully
displayed within one screen, they will be scrolling-displayed automatically from the top to the
bottom.
If IP address of Ethernet A is xxx.xxx.a.b, the displayed address equals to (a256+b). For
example, If IP address of Ethernet A is 198.087.095.023, the displayed address will be 95
256+23=24343.
If the device has detected any abnormal state, itll display the self-check alarm information.
S indicates that device clock is synchronized. If S disappears, it means that device clock is not
synchronized.
8-33
Date: 2015-05-25
Up to 1024 disturbance records can be stored in this device. If there is protection element
operation, LCD will automatically display the latest group of disturbance records, and two kinds of
LCD display interfaces will be available depending on whether there are supervision events or not.
For the situation that the disturbance records and the supervision events coexist, the upper half
part is the disturbance record, and the lower half part is the supervision event. The following items
are listed in the upper half part: record No., record name, generation time of the disturbance
record. If there is protection element operation, faulty phase and relative operation time (with
reference to the corresponding fault detector element) will be displayed. If the disturbance records
can not be displayed in one page, they will be displayed in several pages alternately.
If there is no supervision event, disturbance records will be displayed as shown in the following
figure.
NO.001
2013-01-15 13:22:23:669
0000ms
0024ms
Disturb
FD.DPFC.Pkp
AB
21Q.Z1.Op
If the device has the supervision event, the display interface will show the disturbance record and
the supervision event at the same time.
8-34
2013-01-15 13:22:23:669
NO.001
0000ms
Disturb
FD.DPFC.Pkp
0024ms
AB
21Q.Z1.Op
Superv Events
Alm_Device
NO.001
2013-01-15 13:22:23:669
Disturb
0000ms FD.DPFC.Pkp
0024ms AB
21Q.Z1.Op
All the protection elements have been listed in chapter Operation Theory, and please refer to
each protection element for details. The reports related to oscillography function are showed in the
following table.
Table 8.4-1 Tripping report messages
No.
Message
Description
TrigDFR_Man
TrigDFR_Rmt
TrigDFR_BI
8-35
Date: 2015-05-25
Superv Events
Alm_Device
Alm_Version
Alm_Device
Alm_Version
NO.001
2013-01-15 13:31:23:669
BI_Maintenance
IO Chg
0
8-36
NO.001
2013-01-15 13:31:23:669
shows date and time when the report occurred, the format is
yyyy-mm-dd hh:mm:ss:fff.
IO Chg
BI_Maintenance 01
2008-11-28 10:18:47:569
shows date and time when the report occurred, the format is
yearmonth-date and hour:minute:second:millisecond
Reboot
Message
Description
Reboot
Settings_Chgd
ActiveGrp_Chgd
Report_Cleared
All reports have been deleted. (Device logs can not be deleted)
Waveform_Cleared
Process_Exit
Counter_Cleared
Clear counter
It will be displayed on LCD before disturbance records and supervision events are confirmed. Only
8-37
Date: 2015-05-25
pressing both ENT and ESC at the same time can switch among disturbance records,
supervision events and the normal running state of the device to display it. IO events will be
displayed for 5s and then it will return to the previous display interface automatically.
2.
Press the or to move the cursor to the Measurements menu, and then press
the ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most);
5.
6.
Press the ENT or ESC to exit this menu (returning to the Measurements menu);
2.
Press the key or to move the cursor to the Status menu, and then press the
ENT or to enter the menu.
3.
Press the key or to move the cursor to any command menu item, and then press
the key ENT to enter the submenu.
4.
Press the or to page up/down (if all information cannot be displayed in one
display screen, one screen can display 14 lines of information at most).
5.
6.
Press the key ENT or ESC to exit this menu (returning to the Status menu).
2.
Press the or to move the cursor to the Records menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
8-38
4.
5.
6.
7.
Press the ENT or ESC to exit this menu (returning to the Records menu);
2.
Press the or to move the cursor to the Print menu, and then press the ENT or
to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
Selecting the Disturb Records, and then press the or to select pervious
or next record. After pressing the key ENT, the LCD will display Start Printing... ,
and then automatically exit this menu (returning to the menu Print). If the printer
doesnt complete its current print task and re-start it for printing, and the LCD will
display Printer Busy. Press the key ESC to exit this menu (returning to the
menu Print).
Selecting the command menu Superv Events or IO Events, and then press the
key or to move the cursor. Press the or to select the starting and
ending numbers of printing message. After pressing the key ENT, the LCD will
display Start Printing, and then automatically exit this menu (returning to the
menu Print). Press the key ESC to exit this menu (returning to the menu Print).
4.
If selecting the command menu Device Info, Device Status or IEC103 Info, press
the key ENT, the LCD will display Start printing.., and then automatically exit this menu
(returning to the menu Print).
5.
If selecting the Settings, press the key ENT or to enter the next level of menu.
6.
After entering the submenu Settings, press the key or to move the cursor, and
then press the key ENT to print the corresponding default value. If selecting any item to
printing:
Press the key or to select the setting group to be printed. After pressing the key
ENT, the LCD will display Start Printing, and then automatically exit this menu
(returning to the menu Settings). Press the key ESC to exit this menu (returning to the
menu Settings).
7.
After entering the submenu Waveforms, press the or to select the waveform
item to be printed and press ENT to enter. If there is no any waveform data, the LCD will
display No Waveform Data! (Before executing the command menu Waveforms, it is
necessary to execute the command menu Trig Oscillograph in the menu Local Cmd,
8-39
Date: 2015-05-25
otherwise the LCD will display No Waveform Data!). With waveform data existing:
Press the key or to select pervious or next record. After pressing the key ENT, the LCD
will display Start Printing, and then automatically exit this menu (returning to the menu
Waveforms). If the printer does not complete its current print task and re-start it for printing, and
the LCD will display Printer Busy. Press the key ESC to exit this menu (returning to the menu
Waveforms).
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
5.
6.
7.
Press the ESC to exit this menu (returning to the menu Settings).
NOTICE!
If the displayed information exceeds 14 lines, the scroll bar will appear on the right side
of the LCD to indicate the quantity of all displayed information of the command menu
and the relative location of information where the current cursor points at.
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to any command menu, and then press the
ENT to enter the menu;
4.
5.
6.
7.
Press the ESC to exit this menu (returning to the menu Settings );
8.
If selecting the command menu System Settings, move the cursor to the setting item
8-40
Password:
____
Input a 4-bit password (, , and ). If the password is incorrect, continue inputting it,
and then press the ESC to exit the password input interface and return to the displayed interface
of the command menu System Settings. If the password is correct, LCD will display Save
Setting Now, and then exit this menu (returning to the displayed interface of the command
menu System Settings), with all modified setting items as modified values.
NOTICE!
For different setting items, their displayed interfaces are different but their modification
methods are the same. The following is ditto.
9.
If selecting the submenu Prot Settings, and press ENT to enter. After selecting
different command menu, the LCD will display the following interface: (take FD
Settings as an example)
8-41
Date: 2015-05-25
FD Settings
01
Selected Group:
02
Press the or to modify the value, and then press the ENT to enter it. Move the cursor to
the setting item to be modified, press the ENT to enter.
Take the setting [FD.DPFC.I_Set] as an example is selected to modify, then press the ENT to
enter and the LCD will display the following interface. Press or to modify the value and
then press the ENT to confirm.
FD.DPFC.I_Set
Current Value
0.200
Modified Value
0.202
Min Value
0.050
Max Value
30.000
NOTICE!
After modifying protection settings in current active setting group or system parameters
of the device, the HEALTHY LED indicator the device will be lit off, and the MON
module will check the new settings. If the abnormality is detected during the setting
check, corresponding alarm signals will be issued. Moreover, if the critical error is
detected, the device will be blocked.
8-42
2.
Press the or to move the cursor to the Settings menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to the command menu Copy Settings, and
then press the ENT to enter the menu.
Copy Settings
Active Group:
01
Copy To Group:
02
Press the or to modify the value. Press the ESC, and return to the menu Settings.
Press the ENT, the LCD will display the interface for password input, if the password is incorrect,
continue inputting it, press the ESC to exit the password input interface and return to the menu
Settings. If the password is correct, the LCD will display Settings Copied!, and exit this menu
(returning to the menu Settings).
2.
8-43
Date: 2015-05-25
Active Group:
01
Change To Group:
02
Press the or to modify the value, and then press the ESC to exit this menu (returning to
the main menu). After pressing the ENT, the LCD will display the password input interface. If the
password is incorrect, continue inputting it, and then press the ESC to exit the password input
interface and return to its original state. If the password is correct, the HEALTHY indicator lamp
of the protection device will go out, and the protection device will re-check the protection setting. If
the check doesnt pass, the protection device will be blocked. If the check is successful, the LCD
will return to its original state.
2.
Press the , , , and ENT; Press the ESC to exit this menu (returning to
the original state). Press the ENT to carry out the deletion.
8-44
NOTICE!
The operation of deleting device message will delete all messages saved by the
protection device, including disturbance records, supervision events, binary events, but
not including device logs. Furthermore, the message is irrecoverable after deletion, so
the application of the function shall be cautious.
2.
Press the key or to move the cursor to the command menu Local Cmd, and
then press the key ENT to enter submenus. Press the key or to move the
cursor to the command menu Control, and then press the key ENT to enter and the
following display will be shown on LCD.
Password:
000
Input a 3-bit password (111). If the password is incorrect, continue inputting it, and then press the
ESC to exit the password input interface and return to the displayed interface of the command
menu Control. If the password is correct, it will go to the following step.
3.
Press the key or to move the cursor to the control object and press the key
ENT to select control object.
8-45
Date: 2015-05-25
Control
4.
1.
2.
CSWI02
3.
CSWI03
4.
CSWI04
5.
CSWI05
6.
CSWI06
7.
CSWI07
8.
CSWI08
9.
CSWI09
10.
CSWI10
Press the key or to select control command press the key ENT to the next step.
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
5.
Press the key or to select synchronism check mode and press the key ENT to
the next step.
8-46
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterlockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
6.
Press the key or to select interlock mode and press the key ENT to next step.
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
7.
Press the key or to select control type and press the key ENT.
As shown in the following figure, operation results will be shown after Result at the bottom of the
LCD.
8-47
Date: 2015-05-25
Close(Raise)
NoCheck
SynchroCheck
LoopCheck
EF Line Selection
InterlockChk
InterLockNotChk
Select
Execute
(Stop)
DeadCheck
Cancel
Result
NOTICE!
Exectue operation must be operated after Select operation.
2.
Press the or to move the cursor to the Clock menu, and then press the ENT
to enter clock display
3.
4.
Press the + or - to modify value, and then press the ENT to save the modification
and return to the main menu;
5.
Press the ESC to cancel the modification and return to the main menu.
8-48
Clock
Year:
2008
Month:
11
Day:
28
Hour:
20
Minute:
59
Second:
14
2.
Press the or to move the cursor to the Information menu, and then press the
ENT or to enter the menu;
3.
Press the or to move the cursor to the command menu Board Info, and then
press the ENT to enter the menu;
4.
5.
Press the ENT or ESC to exit this menu (returning to the Information menu).
2.
Press the or to move the cursor to the Information menu, and then press the
ENT to enter the submenu.
3.
Press the key or to move the cursor to the command menu Version Info, and
then press the key ENT to display the software version.
4.
2.
Press the key or to move the cursor to the Test menu, and then press the key
ENT or to enter the menu.
8-49
Date: 2015-05-25
3.
Press the key or to move the cursor to the submenu Device Test, and then
press the key ENT to enter the submenu,to select test item. If Disturb Events
Superv Events or IO Events is selected, two options All Test and Select Test are
provided.
4.
Press the key or to move the cursor to select the corresponding command menu
All Test or Select Test. If selecting the All Test, press the ENT, and the device will
successively carry out all operation element message test one by one.
5.
If Select Test is selected, press the key ENT. Press the or to page up/down,
and then press the key or to move the scroll bar. Move the cursor to select the
corresponding protection element. Press the key ENT to execute the communication
test of this protection element, the substation automatic system (SAS) will receive the
corresponding message.
NOTICE!
If no input operation is carried out within 60s, exit the communication transmission and
return to the Test menu, at this moment, the LCD will display Communication Test
Timeout and Exiting....
Press the key ESC to exit this menu (returning to the menu Test, at this moment, the LCD will
display Communication Test Exiting.
2.
Press the key or to move the cursor to the command menu Language, and
then press the key ENT to enter the menu and the following display will be shown on
LCD.
3.
English
Press the key or to move the cursor to the language user preferred and press
8-50
the key ENT to execute language switching. After language switching is finished, LCD
will return to the menu Language, and the display language is changed. Otherwise,
press the key ESC to cancel language switching and return to the menu Language.
NOTICE!
LCD interface provided in this chapter is only a reference and available for explaining
specific definition of LCD. The displayed interface of the actual device may be some
different from it, so you shall be subject to the actual protection device.
8-51
Date: 2015-05-25
8-52
9 Configurable Function
9 Configurable Function
Table of Contents
9 Configurable Function ...................................................................... 9-a
9.1 Overview .......................................................................................................... 9-1
9.2 Introduction on PCS-Explorer Software ........................................................ 9-1
9.3 Signal List ........................................................................................................ 9-2
9.3.1 Input Signal .......................................................................................................................... 9-2
9.3.2 Output Signal ..................................................................................................................... 9-13
List of Tables
Table 9.3-1 Input signals ............................................................................................................. 9-2
Table 9.3-2 Output signals ........................................................................................................ 9-13
9-a
Date: 2015-10-22
9 Configurable Function
9-b
9 Configurable Function
9.1 Overview
By adoption of PCS-Explorer software, it is able to make device configuration, function
configuration, LCD configuration, binary input and binary output configuration, LED indicator
configuration and programming logic for PCS-931.
Programmable logic
Device configuration
Function configuration
LCD configuration
Setting configuration
Analysis of waveform
File downloading/uploading
9-1
Date: 2015-10-22
9 Configurable Function
Item
Description
Circuit breaker position supervision
CBx.52b_PhA
CBx.52b_PhB
CBx.52b_PhC
CBx.Test
CBx.Test should be set as 1 in fixed, and CB No.x will be not take effect
in corresponding protection logics. (CB position supervision is still kept.)
It is only available for double circuit breakers mode.
External manual closing binary input of circuit breaker No.x, it is only
CBx.ManCls
CBx.52b
CBx.52a
CBx.TCCS.Input
AuxE.OCD.En
10
AuxE.OCD.Blk
11
AuxE.ROC1.En
9-2
9 Configurable Function
No.
Item
12
AuxE.ROC1.Blk
13
AuxE.ROC2.En
14
AuxE.ROC2.Blk
15
AuxE.ROC3.En
16
AuxE.ROC3.Blk
17
AuxE.OC1.En
18
AuxE.OC1.Blk
19
AuxE.OC2.En
20
AuxE.OC2.Blk
21
AuxE.OC3.En
22
AuxE.OC3.Blk
23
AuxE.UVD.En
24
AuxE.UVD.Blk
25
AuxE.UVG.En
26
AuxE.UVG.Blk
27
AuxE.UVS.En
28
AuxE.UVS.Blk
29
AuxE.ROV.En
30
AuxE.ROV.Blk
Description
Stage 1 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 2 of residual current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 2 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 3 of residual current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 3 of residual current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 1 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 2 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase current auxiliary element enabling input, it is triggered
from binary input or programmable logic etc.
Stage 3 of phase current auxiliary element blocking input, it is triggered
from binary input or programmable logic etc.
Voltage change auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Voltage change auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element enabling input, it is
triggered from binary input or programmable logic etc.
Phase-to-ground under voltage auxiliary element blocking input, it is
triggered from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element enabling input, it is
triggered from binary input or programmable logic etc.
Phase-to-phase under voltage auxiliary element blocking input, it is
triggered from binary input or programmable logic etc.
Residual voltage auxiliary element enabling input, it is triggered from
binary input or programmable logic etc.
Residual voltage auxiliary element blocking input, it is triggered from
binary input or programmable logic etc.
Distance protection
31
21D.En
32
21D.Blk
9-3
Date: 2015-10-22
9 Configurable Function
No.
Item
Description
or programmable logic etc.
Load trapezoid characteristic enabling input, it is triggered from binary
33
LoadEnch.En
34
LoadEnch.Blk
35
21.En
36
21.Blk
37
21Mx.ZG.En
38
21Mx.ZG.Blk
39
21Mx.ZP.En
40
21Mx.ZP.Blk
41
21Mx.En_ShortDly
42
21Mx.Blk_ShortDly
43
21M1.En_Instant
44
21Qx.ZG.En
45
21Qx.ZG.Blk
46
21Qx.ZP.En
47
21Qx.ZP.Blk
48
21Qx.En_ShortDly
49
21Qx.Blk_ShortDly
50
21Q1.En_Instant
51
78.En
52
78.Blk
53
78.Clr_Counter
54
21Mx.En_PSBR
55
21Qx.En_PSBR
56
21Mx.Blk_PSBR
9-4
9 Configurable Function
No.
Item
57
21Qx.Blk_PSBR
58
21M.Pilot.En_PSBR
59
21M.Pilot.Blk_PSBR
60
21Q.Pilot.En_PSBR
61
21Q.Pilot.Blk_PSBR
62
21SOTF.En
63
21SOTF.Blk
Description
Blocking power swing blocking releasing of zone x (Quad characteristic,
x=1, 2, 3, 4, 5)
Enabling power swing blocking releasing of pilot distance zone (Mho
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Mho
characteristic)
Enabling power swing blocking releasing of pilot distance zone (Quad
characteristic)
Blocking power swing blocking releasing of pilot distance zone (Quad
characteristic)
Distance SOTF protection enabling input, it is triggered from binary input
or programmable logic etc.
Distance SOTF protection blocking input, it is triggered from binary input
or programmable logic etc.
Optical pilot channel
64
FOx.En
Enabling channel x
65
FOx.Send1
66
FOx.Send2
67
FOx.Send3
68
FOx.Send4
69
FOx.Send5
70
FOx.Send6
71
FOx.Send7
72
FOx.Send8
73
85-x.Z.En1
74
85-x.Z.En2
75
85-x.Z.Blk
76
85-x.Abnor_Ch1
77
85-x.Recv1
78
85-x.RecvB
79
85-x.RecvC
9-5
Date: 2015-10-22
9 Configurable Function
No.
Item
Description
scheme, x=1 or 2)
Input signal of initiating sending permissive signal from external tripping
80
85-x.ExTrp
81
85-x.Unblocking1
82
85-x.ZX.En1
83
85-x.ZX.En2
84
85-x.ZX.Blk1
85
85-x.ZX.Blk2
86
85-x.DEF.En1
87
85-x.DEF.En2
88
85-x.DEF.Blk
89
85-x.Abnor_Ch1
90
85-x.Abnor_Ch2
91
85-x.Recv1
92
85-x.Recv2
93
85-x.ExTrp
94
85-x.Unblocking1
95
85-x.Unblocking2
87L.FOx.En1
97
87L.FOx.En2
98
87L.FOx.Blk
99
50/51Px.En1
100
50/51Px.En2
9-6
9 Configurable Function
No.
101
Item
50/51Px.Blk
Description
Stage x of phase overcurrent protection blocking input, it is triggered
from binary input or programmable logic etc. (x=1, 2, 3, 4)
Earth fault protection
102
50/51Gx.En1
103
50/51Gx.En2
104
50/51Gx.Blk
105
50/51Gx.En_ShortDly
106
50/51Gx.Blk_ShortDly
107
50/51Qx.En1
108
50/51Qx.En2
109
50/51Qx.Blk
110
50PVT.En1
111
50PVT.En2
112
50PVT.Blk
113
50GVT.En1
114
50GVT.En2
115
50GVT.Blk
116
50PSOTF.En1
117
50PSOTF.En2
118
50PSOTF.Blk
119
50GSOTF.En1
9-7
Date: 2015-10-22
9 Configurable Function
No.
Item
Description
binary input or programmable logic etc.
120
50GSOTF.En2
121
50GSOTF.Blk
122
59Px.En1
123
59Px.En2
124
59Px.Blk
125
59Q.En1
126
59Q.En2
127
59Q.Blk
128
59Gx.En1
129
59Gx.En2
130
59Gx.Blk
131
27Px.En1
132
27Px.En2
133
27Px.Blk
134
81O.En1
135
81O.En2
136
81O.Blk
137
81U.En1
138
81U.En2
139
81U.Blk
9-8
9 Configurable Function
No.
Item
Description
or programmable logic etc.
Breaker failure protection
140
CBx.50BF.ExTrp3P_L
141
CBx.50BF.ExTrp3P_GT
142
CBx.50BF.ExTrpA
143
CBx.50BF.ExTrpB
144
CBx.50BF.ExTrpC
CBx.50BF.ExTrp_WOI
146
CBx.50BF.En
147
CBx.50BF.Blk
binary input.
When the input is 1, breaker failure protection is reset and time delay is
cleared.
Thermal overload protection
148
49.Clr_Cmd
149
49.En
150
49.Blk
151
87STB.En1
152
87STB.En2
153
87STB.Blk
154
87STB.89b_DS
155
87STB.89b_DS_Rmt
156
CBx.50DZ.En1
157
CBx.50DZ.En2
158
CBx.50DZ.Blk
input. When the input is 1, dead zone protection is reset and time delay
is cleared.
9-9
Date: 2015-10-22
9 Configurable Function
No.
159
Item
CBx.50DZ.Init
Description
Initiation signal input of the dead zone protection.
Pole discrepancy protection
160
CBx.62PD.En1
161
CBx.62PD.En2
162
CBx.62PD.Blk
163
46BC.En1
164
46BC.En2
165
46BC.Blk
166
32R1.En
167
32R1.Blk
168
32R2.En
169
32R2.Blk
170
CBx.25.Blk_Chk
171
CBx.25.Blk_SynChk
172
CBx.25.Blk_DdChk
173
CBx.25.Start_Chk
174
CBx.25.Start_3PLvChk
175
CBx.25.Sel_ SynChk
176
CBx.25.Sel_DdL_DdB
177
CBx.25.Sel_DdL_LvB
178
CBx.25.Sel_ LvL_DdB
179
CBx.25.Sel_ NoChk
No check is selected.
180
CBx.25.Blk_VTS_Usyn
181
CBx.25.Blk_VTS_Uref
182
25.MCB_VT_UL1
183
25.MCB_VT_UL2
Input signal of blocking synchronism check for AR. If the value is 1, the
output of synchronism check is 0.
Input signal of blocking dead charge check for AR.
Input signal of starting synchronism check, usually it was starting signal
of AR from auto-reclosing module.
Input signal of starting live three-phase check, usually it was starting
signal of 1-pole AR
9-10
9 Configurable Function
No.
Item
Description
184
25.MCB_VT_UB1
185
25.MCB_VT_UB2
186
25.NC_UL1DS
187
25.NO_UL1DS
188
25.NC_UB1DS
189
25.NO_UB1DS
190
25.NC_UL2DS
191
25.NO_UL2DS
192
25.NC_UB2DS
193
25.NO_UB2DS
194
CBx.79.En
195
CBx.79.Blk
196
CBx.79.Sel_1PAR
197
CBx.79.Sel_3PAR
198
CBx.79.Sel_1P/3PAR
199
CBx.79.Trp
200
CBx.79.Trp3P
201
CBx.79.TrpA
202
CBx.79.TrpB
203
CBx.79.TrpC
CBx.79.LockOut
205
CBx.79.PLC_Lost
Input signal of indicating the alarm signal that signal channel is lost
206
CBx.79.WaitMaster
207
CBx.79.CB_Healthy
208
CBx.79.Clr_Counter
209
CBx.79.Ok_Chk
210
CBx.79.Ok_3PLvChk
Transfer trip
211
TT.Init
212
TT.En
213
TT.Blk
9-11
Date: 2015-10-22
9 Configurable Function
No.
Item
Description
programmable logic etc.
Trip logic
Trip enabling input, it is triggered from binary input or programmable
214
CBx.TRP.En
logic etc.
Trip blocking input, it is triggered from binary input or programmable
215
CBx.TRP.Blk
logic etc.
Input signal of permitting three-phase tripping
216
CBx.PrepTrp3P
When this signal is valid, three-phase tripping will be adopted for any
kind of faults.
VT circuit supervision
217
VTS.En
218
VTS.Blk
219
VTNS.En
220
VTNS.Blk
221
VTS.MCB_VT
222
CBx.CTS.En
223
CBx.CTS.Blk
224
MCBrd.CBx.25.Ok_Chk
225
CSWIxx.CILO.EnOpn
226
CSWIxx.CILO.EnCls
227
CSWIxx.LocCtrl
(CB/DS/ES). When the local control is active, No.xx binary outputs can
only be locally controlled. (xx=01~10)
It is used to select the remote control to No.xx controlled object
228
CSWIxx.RmtCtrl
9-12
9 Configurable Function
No.
Item
Description
It is used to disable the interlock blocking function for control output. If
229
CSWIxx.CILO.Disable
230
BIinput.RmtCtrl
When the remote control is active, all binary outputs can only be
remotely controlled by SCADA or control centers.
It is used to select the local control to controlled object (CB/DS/ES).
231
BIinput.LocCtrl
When the local control is active, all binary outputs can only be locally
controlled.
It is used to disable the interlock blocking function for control output. If
232
BIinput.CILO.Disable
233
CSWI01.ManSynCls
control is met
234
CSWI01.ManOpn
control is met
235
CSWI02.ManSynCls
control is met
236
CSWI02.ManOpn
control is met
237
MCBrd.CBx.25.Sel_SynChk
238
MCBrd.CBx.25.Sel_NoChk
Signal
Description
Circuit breaker position supervision
CBx.Alm_52b
CBx.TCCS.Alm
FD.Pkp
FD.DPFC.Pkp
FD.ROC.Pkp
FD.NOC.Pkp
9-13
Date: 2015-10-22
9 Configurable Function
No.
Signal
Description
Auxiliary element
AuxE.St
AuxE.OCD.St_Ext
AuxE.OCD.On
10
AuxE.ROC1.St
11
AuxE.ROC1.On
12
AuxE.ROC2.St
13
AuxE.ROC2.On
14
AuxE.ROC3.St
15
AuxE.ROC3.On
16
AuxE.OC1.St
17
AuxE.OC1.StA
18
AuxE.OC1.StB
19
AuxE.OC1.StC
20
AuxE.OC1.On
21
AuxE.OC2.St
22
AuxE.OC2.StA
23
AuxE.OC2.StB
24
AuxE.OC2.StC
25
AuxE.OC2.On
26
AuxE.OC3.St
27
AuxE.OC3.StA
28
AuxE.OC3.StB
29
AuxE.OC3.StC
30
AuxE.OC3.On
31
AuxE.UVD.St
32
AuxE.UVD.St_Ext
33
AuxE.UVD.On
34
AuxE.UVG.St
35
AuxE.UVG.StA
36
AuxE.UVG.StB
37
AuxE.UVG.StC
38
AuxE.UVG.On
39
AuxE.UVS.St
40
AuxE.UVS.StAB
41
AuxE.UVS.StBC
42
AuxE.UVS.StCA
43
AuxE.UVS.On
44
AuxE.ROV.St
45
AuxE.ROV.On
46
21D.Op
9-14
9 Configurable Function
No.
Signal
Description
47
21D.On
48
LoadEnch.St
49
LoadEnch.On
50
21Mx.On
51
21Mx.Op
52
21Qx.On
53
21Qx.Op
54
78.On
55
78.St
56
78.St_Zone
57
78.Op
58
21Mx.Rls_PSBR
59
21Qx.Rls_PSBR
60
21M.Pilot.Rls_PSBR
61
21Q.Pilot.Rls_PSBR
62
21SOTF.Op
63
21SOTF.On
64
21SOTF.Op_PDF
65
FOx.On
Channel x is enabled.
66
FOx.Recv1
67
FOx.Recv2
68
FOx.Recv3
69
FOx.Recv4
70
FOx.Recv5
71
FOx.Recv6
72
FOx.Recv7
73
FOx.Recv8
74
FOx.Alm
Channel x is abnormal
75
FOx.Alm_ID
76
FOx.Alm_87L_Unmatched
77
87L.On
78
87L.FOx.On
79
87L.Op
differential
protection
[87L.Op_DPFC1],
operates,
[87L.Op_DPFC2],
if
any
of
them
[87L.Op_Biased1],
9-15
Date: 2015-10-22
9 Configurable Function
No.
Signal
Description
80
87L.Op_A
81
87L.Op_B
82
87L.Op_C
83
87L.Op_DPFC1
84
87L.Op_DPFC2
85
87L.Op_Biased1
86
87L.Op_Biased2
87
87L.Op_Neutral
88
87L.Op_InterTrp
89
87L.FOx.Alm_Diff
90
87L.FOx.Alm_Comp
channel
are
|IDiff_Actual|<0.7|IDiff_Cal|
mismatched.
or
85-x.Z.On
92
85-x.ZX.On
93
85-x.Op_Z
94
85-x.Send1
permissive
signal
of
pilot
distance
protection
(only
for
95
85-x.SendB
96
85-x.SendC
97
85-x.Op_ZX
98
85-x.ZX_St
99
85-x.DEF.On
100
85-x.Op_DEF
101
85-x.DEF_BlkAR
102
85-x.Send1
103
85-x.Send2
104
FwdDir_ROC
105
RevDir_ROC
9-16
9 Configurable Function
No.
Signal
Description
106
FwdDir_NegOC
107
RevDir_NegOC
108
FwdDir_A
109
FwdDir_B
110
FwdDir_C
111
RevDir_A
112
RevDir_B
113
RevDir_C
114
FwdDir_AB
115
FwdDir_BC
116
FwdDir_CA
117
RevDir_AB
118
RevDir_BC
119
RevDir_CA
120
50/51Px.On
121
50/51Px.Op
122
50/51Px.St
123
50/51Px.StA
124
50/51Px.StB
125
50/51Px.StC
126
50/51Gx.On
127
50/51Gx.On_ShortDly
128
50/51Gx.St
129
50/51Gx.Op
Short time delay for stage x of earth fault protection is enabled. (x=2,
3, 4)
50/51Qx.On
131
50/51Qx.St
132
50/51Qx.Op
133
50/51Q4.Alm
134
50PVT.On
135
50PVT.Op
136
50PVT.St
137
50PVT.StA
138
50PVT.StB
9-17
Date: 2015-10-22
9 Configurable Function
No.
Signal
Description
139
50PVT.StC
140
50GVT.On
141
50GVT.Op
142
50GVT.St
143
50PSOTF.On
144
50PSOTF.Op
145
50PSOTF.St
146
50GSOTF.On
147
50GSOTF.Op
148
50GSOTF.St
149
59Px.On
150
59Px.Op
151
59Px.St
152
59Px.St1
153
59Px.St2
154
59Px.St3
155
59Px.Op_InitTT
156
59Px.Alm
157
59Q.On
158
59Q.Op
159
59Q.St
160
59G x.On
161
59G x.Op
162
59Gx.St
163
59G3.Alm
164
27Px.On
165
27Px.Op
166
27Px.Alm
167
27Px.St
168
27Px.St1
169
27Px.St2
170
27Px.St3
Frequency protection
171
81O.OFx.On
172
81O.OFx.Op
173
81O.St
174
81U.UFx.On
175
81U.UFx.Op
9-18
9 Configurable Function
No.
176
Signal
81U.St
Description
Underfrequency protection starts.
Breaker failure protection
177
CBx.50BF.On
178
CBx.50BF.Op_ReTrpA
179
CBx.50BF.Op_ReTrpB
180
CBx.50BF.Op_ReTrpC
181
CBx.50BF.Op_ReTrp3P
182
CBx.50BF.Op_t1
183
CBx.50BF.Op_t2
49.On
185
49.St
186
49-1.Op
187
49-2.Op
188
49-1.Alm
189
49-2.Alm
190
87STB.On
191
87STB.On_Local
192
87STB.Op
193
87STB.St
194
87STB.StA
195
87STB.StB
196
87STB.StC
197
87STB.Alm_Diff
198
87STB.Alm_DS
CBx.50DZ.On
200
CBx.50DZ.St
201
CBx.50DZ.Op
202
CBx.62PD.On
203
CBx.62PD.Op
204
CBx.62PD.St
205
46BC.On
206
46BC.St
207
46BC.Op
208
46BC.Alm
9-19
Date: 2015-10-22
9 Configurable Function
No.
Signal
Description
Reverse power protection
209
32R1.On
210
32R1.St
211
32R1.Op
212
32R1.Alm
213
32R2.On
214
32R2.St
215
32R2.Op
216
CBx.UL1_Sel
217
CBx.UL2_Sel
218
CBx.UB1_Sel
219
CBx.UB2_Sel
220
CBx.Alm_Invalid_Sel
221
CBx.25.Ok_fDiffChk
222
CBx.25.Ok_UDiffChk
223
CBx.25.Ok_phiDiffChk
224
CBx.25.Ok_DdL_DdB
225
CBx.25.Ok_DdL_LvB
226
CBx.25.Ok_LvL_DdB
227
CBx.25.Chk_LvL
228
CBx.25.Chk_DdL
229
CBx.25.Chk_LvB
230
CBx.25.Chk_DdB
231
CBx.25.Ok_DdChk
232
CBx.25.Ok_SynChk
233
CBx.25.Ok_Chk
234
CBx.25.Ok_3PLvChk
235
CBx.25.Alm_VTS_Uref
236
CBx.25.Alm_VTS_Usyn
237
CBx.25.f_Ref
238
CBx.25.f_Syn
239
CBx.25.U_Diff
240
CBx.25.f_Diff
241
CBx.25.phi_Diff
9-20
9 Configurable Function
No.
Signal
Description
242
CBx.79.On
243
CBx.79.Off
244
CBx.79.Close
245
CBx.79.Ready
246
CBx.79.AR_Blkd
247
CBx.79.Active
248
CBx.79.Inprog
249
CBx.79.Inprog_1P
250
CBx.79.Inprog_3P
251
CBx.79.Inprog_3PS1
252
CBx.79.Inprog_3PS2
253
CBx.79.Inprog_3PS3
254
CBx.79.Inprog_3PS4
255
CBx.79.WaitToSlave
256
CBx.79.Perm_Trp1P
257
CBx.79.Perm_Trp3P
258
CBx.79.Rcls_Status
0: AR is ready.
1: AR is in progress.
2: AR is successful.
259
CBx.79.Fail_Rcls
Auto-reclosing fails
260
CBx.79.Succ_Rcls
Auto-reclosing is successful
261
CBx.79.Fail_Chk
262
CBx.79.Mode_1PAR
263
CBx.79.Mode_3PAR
264
CBx.79.Mode_1/3PAR
265
TT.Alm
266
TT.Op
267
TT.On
268
CBx.TRP.On
269
CBx.TrpA
270
CBx.TrpB
271
CBx.TrpC
272
CBx.Trp
273
CBx.Trp3P
274
CBx.BFI_A
Trip logic
9-21
Date: 2015-10-22
9 Configurable Function
No.
Signal
Description
Protection tripping signal of B-phase configured to initiate BFP, BFI
275
CBx.BFI_B
276
CBx.BFI_ C
277
CBx.BFI
278
CBx.Trp3P_PSFail
279
CBx.TRP.BlkAR
Blocking auto-reclosing
VT circuit supervision
280
VTS.Alm
281
VTNS.Alm
282
CBx.CTS.Alm
283
CSWIxx.Op_Opn
284
CSWIxx.Op_Cls
285
BIinput.RmtCtrl
286
BIinput.LocCtrl
output signals with input signals are available. The relationship with 10
binary output have been configured inside the device. The user only
assigns a specific binary input to input signal, the relevant function can
287
BIinput.CILO.Disable
288
MCBrd.CBx.Alm_VTS
289
PhSA
290
PhSB
291
PhSC
292
GndFlt
Earth fault
9-22
10 Communication
10 Communication
Table of Contents
10 Communication ............................................................................. 10-a
10.1 Overview ...................................................................................................... 10-1
10.2 Rear Communication Port Information ..................................................... 10-1
10.2.1 RS-485 Interface.............................................................................................................. 10-1
10.2.2 Ethernet Interface ............................................................................................................ 10-3
10.2.3 IEC60870-5-103 Communication .................................................................................... 10-4
10.2.4 DNP3.0 Communication .................................................................................................. 10-4
10-a
Date: 2015-05-25
10 Communication
List of Figures
Figure 10.2-1 EIA RS-485 bus connection arrangements ..................................................... 10-2
Figure 10.2-2 Ethernet communication cable ........................................................................ 10-3
Figure 10.2-3 Ethernet communication structure .................................................................. 10-4
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance ......................... 10-9
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance ..................... 10-10
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances .................. 10-11
10-b
10 Communication
10.1 Overview
This section outlines the remote communications interfaces of NR Relays. The protective device
supports a choice of three protocols via the rear communication interface (RS-485 or Ethernet),
selected via the model number by setting. The protocol provided by the protective device is
indicated in the menu SettingsDevice SetupComm Settings.
The rear EIA RS-485 interface is isolated and is suitable for permanent connection of whichever
protocol is selected. The advantage of this type of connection is that up to 32 protective devices
can be daisy chained together using a simple twisted pair electrical connection.
It should be noted that the descriptions contained within this section do not aim to fully detail the
protocol itself. The relevant documentation for the protocol should be referred to for this
information. This section serves to describe the specific implementation of the protocol in the relay.
10-1
Date: 2015-05-25
Master
EIA RS-485
10 Communication
120 Ohm
120 Ohm
Slave
Slave
Slave
10-2
10 Communication
NOTICE!
It is extremely important that the 120 termination resistors are fitted. Failure to do so
will result in an excessive bias voltage that may damage the devices connected to the
bus.
As the field voltage is much higher than that required, NR cannot assume responsibility
for any damage that may occur to a device connected to the network as a result of
incorrect application of this voltage.
Ensure that the field voltage is not being used for other purposes (i.e. powering logic
inputs) as this may cause noise to be passed to the communication network.
10-3
Date: 2015-05-25
10 Communication
SCADA
Switch: Net A
Switch: Net B
Initialization (reset)
10-4
10 Communication
Time synchronization
General interrogation
General commands
Disturbance records
10.3.2 Initialization
Whenever the protective device has been powered up, or if the communication parameters have
been changed, a reset command is required to initialize the communications. The protective
device will respond to either of the two reset commands (Reset CU or Reset FCB), the difference
is that the Reset CU will clear any unsent messages in the transmit buffer.
The protective device will respond to the reset command with an identification message ASDU 5,
the COT (Cause Of Transmission) of this response will be either Reset CU or Reset FCB
depending on the nature of the reset command.
10-5
Date: 2015-05-25
10 Communication
status of binary signal and alarm element are sent by ASDU1 (time-tagged message). The cause
of transmission (COT) of these responses is 1.
All spontaneous events can be gained by printing, implementing submenu IEC103 Info in the
menu Print.
IEC 61850-5: Communications and requirements for functions and device models
10-6
10 Communication
IEC 61850-7-1: Basic communication structure for substation and feeder equipment
Principles and models
IEC 61850-7-2: Basic communication structure for substation and feeder equipment - Abstract
communication service interface (ACSI)
IEC 61850-7-3: Basic communication structure for substation and feeder equipment
Common data classes
IEC 61850-7-4: Basic communication structure for substation and feeder equipment
Compatible logical node classes and data classes
IEC 61850-8-1: Specific Communication Service Mapping (SCSM) Mappings to MMS (ISO
9506-1 and ISO 9506-2) and to ISO/IEC 8802-3
IEC 61850-9-1: Specific Communication Service Mapping (SCSM) Sampled values over
serial unidirectional multidrop point to point link
IEC 61850-9-2: Specific Communication Service Mapping (SCSM) Sampled values over
ISO/IEC 8802-3
IEC 61850-10: Conformance testing
These documents can be obtained from the IEC (http://www.iec.ch). It is strongly recommended
that all those involved with any IEC 61850 implementation obtain this document set.
MMS protocol
IEC 61850 specifies the use of the Manufacturing Message Specification (MMS) at the upper
(application) layer for transfer of real-time data. This protocol has been in existence for a number
of years and provides a set of services suitable for the transfer of data within a substation LAN
environment. IEC 61850-7-2 abstract services and objects are mapped to actual MMS protocol
services in IEC61850-8-1.
2.
Client/server
This is a connection-oriented type of communication. The connection is initiated by the client, and
communication activity is controlled by the client. IEC61850 clients are often substation computers
running HMI programs or SOE logging software. Servers are usually substation equipment such
as protection relays, meters, RTUs, transformer, tap changers, or bay controllers.
3.
Peer-to-peer
10-7
Date: 2015-05-25
10 Communication
A substation configuration language is a number of files used to describe IED configurations and
communication systems according to IEC 61850-5 and IEC 61850-7. Each configured device has
an IED Capability Description (ICD) file and a Configured IED Description (CID) file. The
substation single line information is stored in a System Specification Description (SSD) file. The
entire substation configuration is stored in a Substation Configuration Description (SCD) file. The
SCD file is the combination of the individual ICD files and the SSD file, moreover, add
communication system parameters (MMS, GOOSE, control block, SV control block) and the
connection relationship of GOOSE and SV to SCD file.
10-8
10 Communication
10.4.3.1 Dual-net Full Duplex Mode Sharing the Same RCB Instance
Client
Client
Net A
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
IED (Server)
IED (Server)
TCP Link
MMS Link
Figure 10.4-1 Dual-net full duplex mode sharing the RCB block instance
Net A and Net B share the same report control block (abbreviated as RCB) enabled by the client.
IED sends undifferentiated date through dual-net to the clients. If one net is physically
disconnected, the flag of RCB instance (i.e.: RptEna in above figure) is still true. Only when
both Net A and Net B are disconnected, the flag of the RCB instance will automatically change to
false.
In normal operation status of this mode, IED provides the same MMS service for Net A and Net B.
If one net is physically disconnected (i.e.: Abnormal operation status in above figure), the
working mode will switch to single-net mode seamlessly and immediately. Network communication
supervision is unnecessary here, and Buffered Report Control Block (abbreviated as BRCB) need
not to be used. On the other net, date alternation works normally. Therefore, MMS service can
interact normally without interruption. This mode ensures no data loss during one net is in
abnormal operation status.
In this mode, one report will be transmitted twice via dual nets for the same report instance, so the
client needs to distinguish whether two reports are same according to corresponding EntryIDs.
10-9
Date: 2015-05-25
10 Communication
Client
Net A
Client
Net B
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 1
RptEna = true
IED (Server)
IED (Server)
TCP Link
Figure 10.4-2 Dual-net hot-standby mode sharing the same RCB instance
In this mode, the MMS service is provided on main MMS link, no MMS service interacts on the
standby MMS link. The definitions of two links are as follows:
Main MMS Link: Physically connected, TCP level connected, MMS report service available.
Standby MMS Link: Physically connected, TCP level connected, MMS report service not
available.
If the main net fails to operate (i.e.: Abnormal operation status in the above figure), the IED will
set RptEna to false. Meanwhile the client will detect the failure by heartbeat message or
keep-alive, it will automatically enable the RCB instance by setting RptEna back to true
through standby MMS link. By the buffer function of BRCB, the IED can provide uninterrupted
MMS service on the standby net. However, the differences of BRCB standards among different
manufacturers may cause data loss. Moreover, if duration of net switch is too long, the data loss is
positively as the capacity of BRCBs buffer function is limited.
NOTICE!
The first mode and second mode, Net A IED host address and Net B IED host address
must be the same.
For example, if the subnet mask is 255.255.0.0, network prefix of Net A is
198.120.0.0, network prefix of Net B is 198.121.0.0, Net A IP address of the IED is
198.120.1.2, and then Net B IP address of the IED must be configured as
198.121.1.2, i.e., Net A IED host address =1x256+2=258, Net B IED host address
=1x256+2=258, Net A IED host address equals to Net B IED host address.
10-10
10 Communication
Client
Net A
Client
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
Net A
Net B
Report Instance 1
RptEna = true
Report Instance 2
RptEna = true
IED (Server)
IED (Server)
TCP Link
MMS Link
Figure 10.4-3 Dual-net full duplex mode with 2 independent RCB instances
In this mode, IED provides 2 report instances for each RCB, Net A and Net B work independently
from each other, failures of any net will not affect the other net at all. Tow report instances are
required for each client. Therefore, the IED may be unable to provide enough report instances if
there are too many clients.
Net A and Net B send the same report separately when they operates normally, To ensure no
repeated data is saved into database, massive calculation is required for the client.
Moreover, accurate clock synchronization of the IED is required to distinguish whether 2 reports
are the same report according to the timestamps. Clock synchronization error of the IED may lead
to report loss/redundancy.
As a conclusion, for the second mode, its difficult to realize seamless switchover between dual
nets, however, for the third mode, the IED may be unable to provide enough report instances if too
many clients are applied on site. Considering client treatment and IED implementation, the first
mode (Dual-net full duplex mode sharing the same report instance) is recommended for MMS
communication network deployment.
10-11
Date: 2015-05-25
10 Communication
MMXU.MX.Hz: frequency
10-12
10 Communication
PTUC: Undercurrent
PTOC: Phase overcurrent, zero-sequence overcurrent and overcurrent when VT circuit failure
PTUV: Undervoltage
PTOF: Overfrequency
PTUF: Underfrequency
RSYN: Synchronism-check
The protection elements listed above contain start (pickup) and operate flags, instead of any
element has its own start (pickup) flag separately, all the elements share a common start (pickup)
flags PTRC.ST.Str.general. The operate flag for PTOC1 is PTOC1.ST.Op.general. For
PCS-931 series relays protection elements, these flags take their values from related module for
the corresponding element. Similar to digital status values, the protection trip information is
reported via BRCB, and BRCB also locates in LLN0.
10.4.4.4 LLN0 and Other Logical Nodes
Logical node LLN0 is essential for an IEC61850 based IED. This LN shall be used to address
common issues for Logical Devices. Most of the public services, the common settings, control
values and some device oriented data objects are available here. The public services may be
BRCB, URCB and GSE control blocks and similar global defines for the whole device; the
common settings include all the setting items of communication settings, system settings and
some of the protection setting items, which can be configured to two or more protection elements
(logical nodes). In LLN0, the item Loc is a device control object, this Do item indicates the local
operation for complete logical device, when it is true, all the remote control commands to the IED
will be blocked and those commands make effective until the item Loc is changed to false. In
PCS-900 series relays, besides the logical nodes we describe above, there are some other logical
nodes below in the IEDs:
MMXU: This LN shall be used to acquire values from CTs and VTs and calculate measurands
such as r.m.s. values for current and voltage or power flows out of the acquired voltage and
10-13
Date: 2015-05-25
10 Communication
current samples. These values are normally used for operational purposes such as power
flow supervision and management, screen displays, state estimation, etc. The requested
accuracy for these functions has to be provided.
LPHD: Physical device information, the logical node to model common issues for physical
device.
PTRC: Protection trip conditioning, it shall be used to connect the operate outputs of one or
to the IEEE Standard Format for Transient Data Exchange (COMTRADE) for Power System
(IEC 60255-24). All enabled channels are included in the recording, independently of the
trigger mode.
10 Communication
Bit 9: Segmentation
Complete names are of the form xxxxxxPTOC1, where the xxxxxx character string is configurable.
Details regarding the logical node naming rules are given in IEC61850 parts 6 and 7-2. It is
recommended that a consistent naming convention be used for an entire substation project.
10.4.5.5 GOOSE Services
IEC61850 specifies the type of broadcast data transfer services: Generic Object Oriented
Substation Events (GOOSE). IEC61850 GOOSE services provide virtual LAN (VLAN) support,
Ethernet priority tagging, and Ether-type Application ID configuration. The support for VLANs and
priority tagging allows for the optimization of Ethernet network traffic. GOOSE messages can be
given a higher priority than standard Ethernet traffic, and they can be separated onto specific
VLANs. Devices that transmit GOOSE messages also function as servers. Each GOOSE
publisher contains a GOOSE control block to configure and control the transmission.
The GOOSE transmission (including subscribing and publishing) is controlled by GOOSE logic link
settings in device.
The PCS-900 series relays support IEC61850 Generic Object Oriented Substation Event (GOOSE)
communication. All GOOSE messages contain IEC61850 data collected into a dataset. It is this
dataset that is transferred using GOOSE message services. The GOOSE related dataset is
configured in the CID file and it is recommended that the fixed GOOSE be used for
implementations that require GOOSE data transfer between PCS-900 series relays.
IEC61850 GOOSE messaging contains a number of configurable parameters, all of which must be
correct to achieve the successful transfer of data. It is critical that the configured datasets at the
transmission and reception devices are an exact match in terms of data structure, and that the
GOOSE addresses and name strings match exactly.
10-15
Date: 2015-05-25
10 Communication
Client
Server
PCS-900 Series
B11
C1
B12
C1
Client-Server Roles
SCSMS Supported
B21
B22
B23
B24
SCSM: other
Publisher side
B32
Subscriber side
Publisher side
B42
Subscriber side
Where:
C1: Shall be "M" if support for LOGICAL-DEVICE model has been declared
O: Optional
M: Mandatory
Y:
Client
Server
PCS-900 Series
M1
Logical device
C2
C2
M2
Logical node
C3
C3
M3
Data
C4
C4
M4
Data set
C5
C5
M5
Substitution
M6
M7
M7-1
sequence-number
M7-2
report-time-stamp
M7-3
reason-for-inclusion
M7-4
data-set-name
M7-5
data-reference
Reporting
10-16
10 Communication
M7-6
buffer-overflow
M7-7
entryID
M7-8
BufTm
M7-9
IntgPd
M7-10
GI
M8
M8-1
sequence-number
M8-2
report-time-stamp
M8-3
reason-for-inclusion
M8-4
data-set-name
M8-5
data-reference
M8-6
BufTm
M8-7
IntgPd
M9
Log control
M9-1
IntgPd
M10
Log
M12
GOOSE
M13
GSSE
M14
Multicast SVC
M15
Unicast SVC
M16
Time
M17
File transfer
Logging
GSE
Where:
C2: Shall be "M" if support for LOGICAL-NODE model has been declared
C3: Shall be "M" if support for DATA model has been declared
C4: Shall be "M" if support for DATA-SET, Substitution, Report, Log Control, or Time models has
been declared
C5: Shall be "M" if support for Report, GSE, or SMV models has been declared
M: Mandatory
Y:
Server/Publisher
PCS-931
Server
S1
ServerDirectory
Application association
PCS-931 Line Differential Relay
10-17
Date: 2015-05-25
10 Communication
S2
Associate
S3
Abort
S4
Release
Logical device
S5
LogicalDeviceDirectory
Logical node
S6
LogicalNodeDirectory
S7
GetAllDataValues
S8
GetDataValues
S9
SetDataValues
S10
GetDataDirectory
S11
GetDataDefinition
S12
GetDataSetValues
S13
SetDataSetValues
S14
CreateDataSet
S15
DeleteDataSet
S16
GetDataSetDirectory
Data
Data set
Substitution
S17
SetDataValues
SelectActiveSG
M/O
S19
SelectEditSG
M/O
S20
SetSGValuess
M/O
S21
ConfirmEditSGValues
M/O
S22
GetSGValues
M/O
S23
GetSGCBValues
M/O
Reporting
Buffered report control block
S24
Report
S24-1
data-change
S24-2
qchg-change
S24-3
data-update
S25
GetBRCBValues
S26
SetBRCBValues
Report
S27-1
data-change
S27-2
qchg-change
S27-3
data-update
S28
GetURCBValues
10-18
10 Communication
S29
SetURCBValues
Logging
Log control block
S30
GetLCBValues
S31
SetLCBValues
S32
QueryLogByTime
S33
QueryLogAfter
S34
GetLogStatusValues
Log
SendGOOSEMessage
S36
GetGoReference
S37
GetGOOSEElementNumber
S38
GetGoCBValues
S39
SetGoCBValuess
S51
Select
S52
SelectWithValue
S53
Cancel
S54
Operate
S55
Command-Termination
S56
TimeActivated-Operate
Control
File transfer
S57
GetFile
M/O
S58
SetFile
S59
DeleteFile
S60
GetFileAttributeValues
M/O
Time
SNTP
PCS-931
YES
YES
10-19
Date: 2015-05-25
10 Communication
Nodes
PCS-931
PDIF: Differential
YES
YES
YES
YES
PTOF: Overfrequency
YES
PTOV: Overvoltage
YES
YES
YES
PTUC: Undercurrent
PPDP: Pole discrepancy
YES
PTUV: Undervoltage
YES
YES
YES
YES
10-20
10 Communication
Nodes
PCS-931
YES
YES
RREC: Autoreclosing
YES
YES
CILO: Interlocking
YES
YES
YES
YES
YES
MMTR: Metering
YES
YES
MMXU: Measurement
YES
YES
10-21
Date: 2015-05-25
10 Communication
Nodes
PCS-931
YES
YES
ZBAT: Battery
ZBSH: Bushing
ZCON: Converter
ZGEN: Generator
ZMOT: Motor
ZREA: Reactor
10 Communication
The relay operates as a DNP3.0 slave and supports subset level 3 of the protocol, plus some of
the features from level 4. The DNP3.0 communication uses the Ethernet ports (electrical or optical)
at the rear side of this relay.
Function
0 (0x00)
Confirm
1 (0x01)
Read
2 (0x02)
Write
3 (0x03)
Select
4 (0x04)
Operate
5 (0x05)
Direct Operate
6 (0x06)
13 (0x0D)
Cold Restart
14 (0x0E)
Warm Restart
20 (0x14)
21 (0x15)
22 (0x16)
Assign Class
23 (0x17)
Delay Measurement
REQUEST
Description
No.
Function code
1 (read)
22 (assign class)
1 (read)
1 (read)
Qualifier code
10-23
Date: 2015-05-25
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
REQUEST
Description
No.
Function code
1 (read)
1 (read)
1 (read)
1 (read)
10
1 (read)
10
1 (read)
10
2 (write)
Qualifier code
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
06 (no range, or all)
07, 08 (limited qty)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
3 (select)
12
4 (operate)
(CROB)
5 (direct op)
6 (dir. op, no ack)
17, 28 (index)
1 (read)
22 (assign class)
30
30
1 (read)
30
1 (read)
30
1 (read)
30
1 (read)
30
1 (read)
32
1 (read)
32
1 (read)
32
1 (read)
32
34
10-24
17, 28 (index)
1 (read)
1 (read)
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
REQUEST
Description
No.
Function code
1 (read)
34
1 (read)
34
1 (read)
34
40
1 (read)
40
1 (read)
40
1 (read)
40
1 (read)
Qualifier code
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
17,28 (index)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
00, 01 (start ~ stop)
06 (no range, or all)
3 (select)
41
4 (operate)
17,28 (index)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
3 (select)
41
4 (operate)
17,28 (index)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
3 (select)
41
50
50
51
51
4 (operate)
17,28 (index)
5 (direct op)
6 (dir. Op, no ack)
17,28 (index)
1 (read)
07 (limited qty = 1)
2 (write)
07 (limited qty = 1)
2 (write)
07 (limited qty = 1)
10-25
Date: 2015-05-25
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
Description
No.
60
REQUEST
Function code
1 (read)
22 (assign class)
1 (read)
60
Qualifier code
20 (enable unsol.)
21 (disable unsol.)
22 (assign class)
06 (no range, or all)
1 (read)
60
20 (enable unsol.)
21 (disable unsol.)
22 (assign class)
06 (no range, or all)
1 (read)
60
20 (enable unsol.)
21 (disable unsol.)
22 (assign class)
RESPONSE
Description
No.
Function code
Qualifier code
129 (response)
129 (response)
10
10
10
12
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
129 (response)
17, 28 (index)
17, 28 (index)
17, 28 (index)
echo of request
(CROB)
10-26
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
Description
No.
RESPONSE
Function code
Qualifier code
30
30
129 (response)
30
129 (response)
30
129 (response)
30
129 (response)
30
129 (response)
32
32
32
32
34
34
34
34
40
40
40
40
41
41
41
50
50
51
51
60
129 (response)
130 (unsol. resp)
129 (response)
130 (unsol. resp)
129 (response)
time
17,28 (index)
17,28 (index)
17,28 (index)
129 (response)
129 (response)
129 (response)
129 (response)
129 (response)
129 (response)
129 (response)
echo of request
129 (response)
echo of request
129 (response)
echo of request
129 (response)
07 (limited qty = 1)
129 (response)
synchronized
129 (response)
unsynchronized
07 (limited qty = 1)
07 (limited qty = 1)
10-27
Date: 2015-05-25
10 Communication
OBJECT GROUP & VARIATION
Group/Variation
No.
RESPONSE
Description
60
60
60
Function code
Qualifier code
Pulse On/Null
Pulse On/Close
Pulse On/Trip
Latch On/Null
Latch Off/Null
Remote Control
Not supported
Close
Trip
Close
Trip
Logic Link
Not supported
Set
Clear
Set
Clear
Extended Output
10 Communication
point will output a high ~ level pulse. The pulse width can be decided by the On ~ time in the
related Binary Command which is from the DNP3.0 master. If the On ~ time is set as 0, the
default pulse width is 500ms.
10.5.4.6 Unsolicited Messages
This relay does not transmit the unsolicited messages if the related logic setting is set as 0. If the
unsolicited messages want to be transmitted, the related logic setting should be set as 1 or the
DNP3.0 master will transmit Enable Unsolicited command to this relay through Function Code
20 (Enable Unsolicited Messages). If the Binary Input state changes or the difference value of
the Analog Input is greater than the deadband value, this device will transmit unsolicited
messages. If the DNP3.0 master needs not to receive the unsolicited messages, it should forbid
this relay to transmit the unsolicited messages by setting the related logic setting as 0 or through
the Function Code 21 (Disable Unsolicited Messages).
10.5.4.7 Class Configuration
If the DNP3.0 master calls the Class0 data, this relay will transmit all actual values of the Analog
Input, Binary Input and Analog Output. The classes of the Analog Input and Binary Input
can be defined by modifying relevant settings. In communication process, the DNP3.0 master can
online modify the class of an Analog Input or a Binary Input through Function Code 22 (Assign
Class).
10-29
Date: 2015-05-25
10 Communication
10-30
11 Installation
11 Installation
Table of Contents
11 Installation ...................................................................................... 11-a
11.1 Overview ....................................................................................................... 11-1
11.2 Safety Information ........................................................................................ 11-1
11.3 Checking Shipment ...................................................................................... 11-2
11.4 Material and Tools Required ........................................................................ 11-2
11.5 Device Location and Ambient Conditions .................................................. 11-2
11.6 Mechanical Installation ................................................................................ 11-3
11.7 Electrical Installation and Wiring ................................................................ 11-4
11.7.1 Grounding Guidelines .......................................................................................................11-4
11.7.2 Cubicle Grounding ............................................................................................................11-4
11.7.3 Ground Connection on the Device ...................................................................................11-5
11.7.4 Grounding Strips and their Installation ..............................................................................11-5
11.7.5 Guidelines for Wiring.........................................................................................................11-6
11.7.6 Wiring for Electrical Cables ...............................................................................................11-6
List of Figures
Figure 11.6-1 Dimensions and panel cut-out of PCS-931 ..................................................... 11-3
Figure 11.6-2 Demonstration of plugging a board into its corresponding slot .................. 11-3
Figure 11.7-1 Cubicle grounding system ................................................................................ 11-5
Figure 11.7-2 Ground terminal of this relay ............................................................................ 11-5
Figure 11.7-3 Ground strip and termination ........................................................................... 11-6
Figure 11.7-4 Glancing demo about the wiring for electrical cables ................................... 11-7
11-a
Date: 2015-05-26
11 Installation
11-b
11 Installation
11.1 Overview
The device must be shipped, stored and installed with the greatest care. Choose the place of
installation such that the communication interface and the controls on the front of the device are
easily accessible.
Air must circulate freely around the equipment. Observe all the requirements regarding place of
installation and ambient conditions given in this instruction manual.
Take care that the external wiring is properly brought into the equipment and terminated correctly
and pay special attention to grounding. Strictly observe the corresponding guidelines contained in
this section.
Should boards have to be removed from this relay installed in a grounded cubicle in an HV
switchgear installation, please discharge yourself by touching station ground (the cubicle)
beforehand.
2.
Only hold electronic boards at the edges, taking care not to touch the components.
3.
Only works on boards that have been removed from the cubicle on a workbench designed for
11-1
Date: 2015-05-26
11 Installation
electronic equipment and wear a grounded wristband. Do not wear a grounded wristband,
however, while inserting or withdrawing units.
4.
Always store and ship the electronic boards in their original packing. Place electronic parts in
electrostatic screened packing materials.
The location should not be exposed to excessive air pollution (dust, aggressive substances).
2.
Severe vibration, extreme changes of temperature, high levels of humidity, surge voltages of
high amplitude and short rise time and strong induced magnetic fields should be avoided as
far as possible.
3.
The equipment can in principle be mounted in any attitude, but it is normally mounted vertically
11-2
11 Installation
(visibility of markings).
Front
Side
Cut-Out
Figure 11.6-1 Dimensions and panel cut-out of PCS-931
The safety instructions must be abided by when installing the boards, please see Section 11.2 for
the details.
Following figure shows the installation way of a module being plugged into a corresponding slot.
11-3
Date: 2015-05-26
11 Installation
In the case of equipment supplied in cubicles, place the cubicles on the foundations that have
been prepared. Take care while doing so not to jam or otherwise damage any of the cables that
have already been installed. Secure the cubicles to the foundations.
11 Installation
Door or hinged
equipment frame
Cubicle ground
rail close to floor
Braided
copper strip
Station
ground
Conducting
connection
11-5
Date: 2015-05-26
11 Installation
Braided
copper strip
Terminal bolt
Contact surface
Power supply, binary inputs & outputs: stranded conductor, 1.0mm 2 ~ 2.5mm 2
11-6
11 Installation
Tighten
01
02
03
04
05
06
07
08
09
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
01
Figure 11.7-4 Glancing demo about the wiring for electrical cables
11-7
Date: 2015-05-26
11 Installation
11-8
12 Commissioning
12 Commissioning
Table of Contents
12 Commissioning ............................................................................. 12-a
12.1 Overview ...................................................................................................... 12-1
12.2 Safety Instructions ...................................................................................... 12-1
12.3 Commission Tools ...................................................................................... 12-2
12.3.1 Minimum Equipment Required ........................................................................................ 12-2
12.3.2 Optional Equipment ......................................................................................................... 12-2
12-a
Date: 2015-05-26
12 Commissioning
12-b
12 Commissioning
12.1 Overview
This device is fully numerical in their design, implementing all protection and non-protection
functions in software. The relay employs a high degree of self-checking and in the unlikely event of
a failure, will give an alarm. As a result of this, the commissioning test does not need to be as
extensive as with non-numeric electronic or electro-mechanical relays.
To commission numerical relays, it is only necessary to verify that the hardware is functioning
correctly and the application-specific software settings have been applied to the relay.
Blank commissioning test and setting records are provided at the end of this manual for
completion as required.
Before carrying out any work on the equipment, the user should be familiar with the contents of the
safety and technical data sections and the ratings on the equipments rating label.
The earthing screw of the device must be connected solidly to the protective earth conductor
before any other electrical connection is made.
2.
Hazardous voltages can be present on all circuits and components connected to the supply
voltage or to the measuring and test quantities.
3.
Hazardous voltages can be present in the device even after disconnection of the supply
voltage (storage capacitors!)
4.
The limit values stated in the Chapter Technical Data must not be exceeded at all, not even
during testing and commissioning.
5.
When testing the device with secondary test equipment, make sure that no other
measurement quantities are connected. Take also into consideration that the trip circuits and
maybe also close commands to the circuit breakers and other primary switches are
disconnected from the device unless expressly stated.
12-1
Date: 2015-05-26
12 Commissioning
Multifunctional dynamic current and voltage injection test set with interval timer.
2.
Multimeter with suitable AC current range and AC/DC voltage ranges of 0~440Vac and
0~250Vdc respectively.
3.
4.
5.
An electronic or brushless insulation tester with a DC output not exceeding 500V (for
insulation resistance test when required).
2.
A portable PC, with appropriate software (this enables the rear communications port to be
tested, if this is to be used, and will also save considerable time during commissioning).
3.
EIA RS-485 to EIA RS-232 converter (if EIA RS-485 IEC60870-5-103 port is being tested).
4.
12-2
12 Commissioning
Hardware tests
These tests are performed for the following hardware to ensure that there is no hardware defect.
Defects of hardware circuits other than the following can be detected by self-monitoring when the
DC power is supplied.
2.
3.
4.
5.
Function tests
These tests are performed for the following functions that are fully software-based. Tests of the
protection schemes and fault locator require a dynamic test set.
6.
7.
Timers test
8.
9.
Conjunctive tests
The tests are performed after the relay is connected with the primary equipment and other external
equipment.
10. On load test
11. Phase sequence check and polarity check
12-3
Date: 2015-05-26
12 Commissioning
Protection panel
Carefully examine the protection panel, protection equipment inside and other parts inside to see
that no physical damage has occurred since installation.
The rated information of other auxiliary protections should be checked to ensure it is correct for the
particular installation.
2.
Panel wiring
Check the conducting wire which is used in the panel to assure that their cross section meeting the
requirement.
Carefully examine the wiring to see that they are no connection failure exists.
3.
Label
Check all the isolator binary inputs, terminal blocks, indicators, switches and push buttons to make
sure that their labels meet the requirements of this project.
4.
Check each plug-in module of the device on the panel to make sure that they are well installed into
the equipment without any screw loosened.
5.
Earthing cable
Check whether the earthing cable from the panel terminal block is safely screwed to the panel
steel sheet.
6.
Check whether all the switches, equipment keypad, isolator binary inputs and push buttons work
normally and smoothly.
12.5.1.2 Insulation Test
Insulation resistance tests are only necessary during commissioning if it is required for them to be
done and they have not been performed during installation.
Isolate all wiring from the earth and test the isolation with an electronic or brushless insulation
tester at a DC voltage not exceeding 500V, The circuits need to be tested should include:
1.
2.
3.
DC power supply
12-4
12 Commissioning
4.
5.
Output contacts
6.
Communication ports
12-5
Date: 2015-05-26
12 Commissioning
12-6
12 Commissioning
Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ia
Three-phase current 1
Ib
Ic
Ia
Three-phase current 2
Ib
Ic
Ia
Three-phase current 3
Ib
Ic
Ia
Three-phase current
Ib
Ic
Residual current 1
3I0
Residual current 2
3I0
Residual current 3
3I0
Residual current
3I0
Item
Input Value
Input Angle
Display Value
Display Angle
Ua
Three-phase voltage 1
Ub
Uc
Ua
Three-phase voltage 2
Ub
Uc
Ua
Three-phase voltage 3
Ub
Uc
Three-phase voltage
Ua
12-7
Date: 2015-05-26
12 Commissioning
Group No.
Item
Input Value
Input Angle
Display Value
Display Angle
Ub
Uc
Residual voltage 1
3U0
Residual voltage 2
3U0
Residual voltage 3
3U0
Residual voltage
3U0
Signal Name
BI Status on LCD
Correct?
12-8
12 Commissioning
However, these checks can only be carried out if there are no restrictions preventing the
tenderization of the plant being protected.
Remove all test leads, temporary shorting leads, etc. and replace any external wiring that has
been removed to allow testing.
If it has been necessary to disconnect any of the external wiring from the protection in order to
perform any of the foregoing tests, it should be ensured that all connections are replaced in
accordance with the relevant external connection or scheme diagram. Confirm current and voltage
transformer wiring.
12-9
Date: 2015-05-26
12 Commissioning
12-10
13 Maintenance
13 Maintenance
Table of Contents
13 Maintenance .................................................................................. 13-a
13.1 Overview ...................................................................................................... 13-1
13.2 Appearance Check ...................................................................................... 13-1
13.3 Failure Tracing and Repair ......................................................................... 13-1
13.4 Replace Failed Modules ............................................................................. 13-2
13.4.1 Preparation for Replace Module ...................................................................................... 13-2
13.4.2 Replace HMI Module of Front Panel ............................................................................... 13-3
13.4.3 Replace Module ............................................................................................................... 13-3
13-a
Date: 2015-05-26
13 Maintenance
13-b
13 Maintenance
13.1 Overview
The device is designed to require no special maintenance. All measurement and signal processing
circuit are fully solid state. All input modules are also fully solid state. The output relays are
hermetically sealed.
Since the device is almost completely self-monitored, from the measuring inputs to the output
relays, hardware and software defects are automatically detected and reported. The
self-monitoring ensures the high availability of the device and generally allows for a corrective
rather than preventive maintenance strategy. Therefore, maintenance checks in short intervals are
not required.
Operation of the device is automatically blocked when a hardware failure is detected. If a problem
is detected in the external measuring circuits, the device normally only provides alarm messages.
2.
3.
4.
5.
13-1
Date: 2015-05-26
13 Maintenance
2.
3.
Short circuit all AC current inputs and disconnect all AC voltage inputs
13-2
13 Maintenance
2.
Unplug the ribbon cable on the front panel by pushing the catch outside.
3.
4.
2.
3.
4.
5.
6.
After replacing the MON or DSP module, input the application-specific setting values again.
13.5 Cleaning
Before cleaning the relay, ensure that all AC/DC supplies, current transformer connections are
isolated to prevent any chance of an electric shock whilst cleaning. Use a smooth cloth to clean
the front panel. Do not use abrasive material or detergent chemicals.
13.6 Storage
The spare relay or module should be stored in a dry and clean room. Based on IEC standard
60255-1 the storage temperature should be from -40C to +70C, but the temperature of from 0C
to +40C is recommended for long-term storage.
13-3
Date: 2015-05-26
13 Maintenance
13-4
14-a
Date: 2015-05-26
14-b
14.1 Decommissioning
DANGER!
Switch OFF the circuit breaker for primary CTs and VTs BEFORE disconnecting the
cables of AI module.
WARNING!
Switch OFF the external miniature circuit breaker of device power supply BEFORE
disconnecting the power supply cable connected to the PWR module.
WARNING!
KEEP an adequate safety distance to live parts of the power substation.
1.
Switching off
To switch off the PCS-931, switch off the external miniature circuit breaker of the power supply.
2.
Disconnecting Cables
Disconnect the cables in accordance with the rules and recommendations made by relational
department.
3.
Dismantling
The PCS-931 rack may now be removed from the system cubicle, after which the cubicles may
also be removed.
14.2 Disposal
In every country there are companies specialized in the proper disposal of electronic waste.
NOTICE!
Strictly observe all local and national laws and regulations when disposing the device.
14-3
Date: 2015-05-26
14-4
Software
New
Version
R1.00
R1.00
Date
2011-07-07
Description of change
Form the original manual
Add the description about C37.94
Rewrite datas of ambient temperature and humidity
range and binary input
Amend fault detector (FD)
Add load encroachment element
Delete blinder element
R1.00
R1.01
2011-12-16
R1.10
R1.02
2012-03-15
R1.02
R1.03
2012-05-08
2012-07-02
R1.03
R1.04
R2.00
2012-07-07
2012-08-14
2012-12-10
2013-05-29
R1.04
R1.05
R2.10
2013-06-01
sequence
Modify the breaking capacity of binary output contact
Add the setting of system parameters
Add output sigals of function enabled and element
2013-05-29
15-1
Date: 2015-10-22
New
Software
Version
Date
Description of change
Modify function number of overcurrent protection for VT
circuit failure
Add settings for broken conductor protection and modify
the logic
Add function block diagram for power swing blocking
releasing, current direction, trip logic, faulty phase
R1.04
R1.05
R2.11
2013-09-12
R1.04
R1.05
R2.12
2013-11-11
R1.05
2013-12-25
R1.06
the
seting items of
communication
([Opt_Display_Status],
setting
[t_Dly_Net_DNP],
[Fmt_Setting_DNP])
Add the setting items of
Quadrilateral
Distance
R1.06
2013-12-27
R1.07
2014-03-06
the
settings
[21M.ZP4.En_BlkAR],
R1.07
R1.08
2014-06-04
[21M.ZG4.En_BlkAR],
[21Q.ZP4.En_BlkAR]
and
[21Q.ZG4.En_BlkAR]
First four binary signals (BI_01, BI_02, BI_03, BI_04) are
changed to be configurable .
Modify distance protection logic (5 zones, 1 forwards
zone and 4 settable forward or reverse zones)
Modify the setting range of primary rated current
R1.08
R2.00
R3.00
2014-07-30
15-2
New
Software
Version
Date
Description of change
overvoltage protection and undervoltage protection)
Add the setting [En_MDisk] and related descriptions
Add synchronism voltage switchover in synchrocheck
module
Add the corresponding descriptions about dual-channels
pilot distance protection and pilot directional earth-fault
protection
Modify the logic of VT circuit supervision
Add new fault detectors
Modify
the
setting
items
[50/51Px.Opt_Curve],
of
the
settings
[50/51Gx.Opt_Curve],
2015-05-23
2015-05-25
2015-05-26
15-3
Date: 2015-10-22
New
Software
Version
Date
Description of change
Notice
R2.00
R2.01
2015-07-16
2015-07-20
Add the caution lable about optical fibre and its interface
2015-10-19
2015-10-21
protection
Add residual overvoltage protection
Modify the logic of distance SOTF protection
R2.00
R2.01
R3.10
2015-10-22
2016-03-11
15-4