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Linting

Posted on March 8, 2014 by Sini Balakrishnan in General // 9 Comments

What is meant by lint? It was the name originally given to a program that flagged suspicious and
non-portable constructs in software programs.

Later this was extended to hardware languages as well for early design analysis. That means rule
checks will be applied on the developed RTLs and it helps to identify errors which we would be
getting in the upcoming design cycle stages like synthesis etc.This also helps to make sure that
during optimization stage, design functionality is not changed. Overall, it points out where the code
is likely to have bugs.

One important point about linting is that it checks the cleanness and portability of the HDL code for
various EDA tools and not anything related to the actual functionality of the design.

How does it work?

There are some set of rules defined in the lint tool. Rule means a condition that has to be checked on
your design. User can enable and disable the required rules as per his requirement. Once these rules
are run on the design, and if design source code does not conform to a rule, violation will be
reported.
You can have your own policy file (tcl file) specifying the rules to be checked for. Also specify
whether you want particular rule check result has to be an error, warning or info.

Steps

1. Change configuration/Define rule set.

2. User can change the configuration settings and modify the rules set by enabling or disabling
as per their requirement.
3. Invoke tool and Source rules
4. Analyse Design
5. Elaborate
6. Generate report

Areas Covered

Differences between simulation and synthesis semantics

Opportunities to improve simulation performance
Probable simulation errors
Chances of matching gate level simulations with RTL simulations
Coding guidelines
FSM state reachability and coding issues
Network and connectivity checks for clocks, resets, and tri-state driven signals
Module partitioning
Tool flow issues in the upcoming design cycle stages
Possible synthesis issues. (eg unintended latches or combo loops)
Clocks and reset definitions.

Sample Rules

 COMBO_LOOP : It reports if there is a combinational loop in the design.

TERMINAL_STATE : It reports, if a state in a FSM that once entered never reaches to
another state via next state assignment.
COMBO_NBA : It reports NBA reg assignment from a combo block.
MULTI_DEFINES : It reports, if there are more than one macros with the same name.
INC_SENS_LIST : If a signal is referenced and not used in the sensitivity list of the block, it
reports the failure.

Tools:
Some of the available tools in the market to do linting and CDC checks are

Spyglass
Realintent (Ascentlint, IIV,Meridian)
LEDA
SureLint
Most of the formal verification tools (Onespin, IFV etc)

About

Latest Posts

Sini Balakrishnan
Staff Engineer

at Lantiq

Sini has spent more than a dozen years in the semiconductor industry, focusing mostly on
verification. She is an expert on Formal Verification and has written international papers and
articles on related topics.

Design Checks
Linting
vlsi design
9 Comments on Linting
1.

sharan // September 17, 2014 at 12:31 pm // Reply

Can we also called this Linting errors as post synthesis simulation mismatch?

2.

Sini Balakrishnan // December 16, 2014 at 1:27 pm // Reply

Post synthesis simulation mismatches can be reduced by cleaning up the lint errors in
the RTL stage.
naga surendra // December 15, 2014 at 4:19 pm // Reply

where do we do linting process in ASIC design flow??

Sini Balakrishnan // December 16, 2014 at 1:24 pm // Reply

Linting is used at RTL stage by the designer. Before RTL freeze linting should be clean
so that there wouldnt be any surprise during synthesis.
3.

4.

5.

6.

7.

ssp // July 6, 2015 at 6:28 pm // Reply

how the linting is useful for any varification engineer?

liwei xing // January 15, 2016 at 12:58 pm // Reply

Hi, Sorry for disturbing.

About lint, whether generateendgeneratestructure can pass lint check even its
synthesizable?
thank you!
vijay // February 10, 2016 at 11:58 am // Reply

Hi,
could u pls expain what is diffrence between HAl(cadence) and Lint check(Spyglass)?
are they are same.
regards
vijay
sumanth // May 28, 2016 at 10:44 am // Reply

in pre-pnr netlist why a combo loop should not exist and what is is a effect of combo loop on
back-end.
Alok Dadlani // August 9, 2016 at 7:50 am // Reply

Helped me a lot to get a brief idea about Linting. Thanks!

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