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Serial IO
D[15:0]
CPU #1
CPU #2
clk
CPU #1
Question: Assuming one bit is sent each rising clock edge, how
fast does the clock have to be achieve 600 MB/s?
V 0.2
CPU #1
CPU #1
Rx
Tx
bi-directional
V 0.2
Oe
ia
Rx = ib
Rx
Tx
Rx
ia + ib
Tx
CPU #2
or
uni-directional
CPU #2
CPU #1
For wires:
simplex wire: communication occurs only in one
direction.
Tx
Serial IO Pros/Cons
Parallel IO Pros/Cons
CPU #2
clk
Currents add,
voltages do
not!
ia
Tx
ib
ib
ia + ib
ia + ib
V 0.2
Rx = ia
CPU #1
Synchronous Serial IO
Asynchronous Serial IO
CPU #2
V 0.2
V 0.2
Tx
Rx
Rx
Tx
gnd
gnd
data values
ST D0 D1
ST D0 D1 D2 D3 D4 D5 D6 D7
ST D0 D1
10
Parity
Example
1
ST start bit
D0 LSB
D6(D7) MSB
P parity bit
* - stop bit a mark
ST D0 D1 D2 D3 D4 D5 D6 P
CPU #1
Tx:transmit, Rx:Receive
CPU #2
CPU #1
A single bit error is when one bit of the frame was received
incorrectly (read as 0 when should have been 1, or vice-versa).
Not guaranteed to detect multi-bit errors
ST start bit
= ()/10 = 5%
slide by Prof. Mitch Thornton
V 0.2
11
V 0.2
12
Receiver Sampling
one bit time
8 9
next bit
10 11 12 13 14 15 0 1
sample here
2 3 4
Receiver clock; period usually either 64x or 16x bit time (above is 16x).
At start bit, internal 4-bit counter set to 0. Sample at mid-point of bit time (counter
value 7 or 8, some receivers sample at 7,8 and 9 and only accept bit if all values
are the same do this for glitch rejection).
Receiver/Transmitter clocks not perfectly matched. Our tolerance is bit time
(50%) spread over entire frame. Assuming a 10 bit frame, maximum mismatch
between Rx/Tx clocks is 50%/10 = 5%,
V 0.2
i.e., use 4 different voltage levels, send two bits of data per
signaling event (00 = -15v, 01= -5v, 10=+5v, 11 = 5v).
In this case, bit rate will be double the baud rate
13
V 0.2
128
57600
256
38400
512
19200
1024
9600
2048
4800
4096
1200
16384
CPU #1
RB2
RB3
Rx
Tx
17
16
getch()
getch() -- receive one character
over software serial link
Wait for start bit
while(bittst(PORTB,3));
delay_onehalf_bit();
RB2
putch(c)
CPU #2
RB3
V 0.2
Rx
for(i=0;i<8;i++) {
if (bittst(c,0))
bitset(PORTB,2);
else bitclr(PORTB,2);
delay_1bit();
c = c >> 1;
}
bitset(PORTB,2)
delay_1bit();
Tx
15
bitclear(PORTB,2);
delay_1bit();
Divisor for
14.7456 MHz
14
time
for(i=0;i<8;i++) {
delay_1bit()
if (bittst(PORTB,3)) c = c | 0x80;
if (i != 7) c = c >> 1;
}
Input bit was 1, set MSB.
return(c);
}
18
USART Registers
PIC16F873 USART
USART Universal Synchronous Asynchronous Receiver
Transmitter
TXREG
RCREG
RC6/TX
RC7/RX
V 0.2
19
V 0.2
Transmit Hardware
20
21
V 0.2
Receive Hardware
getch()/putch() (USART)
Two-deep
FIFO. Can
hold 2
characters,
while 3rd
character is
being shifted
into RSR
register.
V 0.2
23
/* while (!RCIF) */
while (!bittst(PIR1,5));
c = RCREG;
return(c);
/* while (!TXIF) */
while (!bittst(PIR1,4));
TXREG = c;
}
24
or
SBPRG = (14.7456e06/[16*9600] ) 1
= 95
SBPRG = (Fosc/[K*Baud_Rate] ) 1
SBPRG = (14.7456e06/[64*9600] ) 1
= 23
V 0.2
25
2. Select high or low speed baud rate via BRGH bit (bit 2) of
TXSTA register
3. Select async mode SYNC bit (TXSTA:4 = 0)
4. Select 8-bit transmit via TX9 bit (TXSTA:6 = 0)
5. Select 8-bit receive via RX9 bit (RCSTA:6 = 0)
6. Enable transmit port via TXEN bit (TXSTA:5 = 1)
7);
7);
6);
2);
4);
6);
6);
5);
4);
/*
/*
/*
/*
/*
/*
/*
/*
/*
/*
V 0.2
28
16F873
RC7/RX
MAX232
Rout
Rin
TX Pin 3
DB9 Female
Gnd Pin 5
RC6/TX
0v to 5v logic
levels
26
V 0.2
V 0.2
Note logic
inversion
29
Tin
Tout
RX Pin 2
serial
cable
connected
to COM
port on PC
logic 1: 3v to 25v
V 0.2
30
What is EIA-RS232?
MAXIM
232/232A
RS232
driver/receiver
31
Hyperterminal
V 0.2
32
33
V 0.2
34