CHAPTER 1

INTRODUCTION
In Recent years, wireless sensor networks (WSNs) have been evolving at an accelerated
pace. To build WSNs, the Zigbee protocol, in which medium access control layer and
physical layer are defined by IEEE 802.15.4, has been generally used. Because the Zigbee
protocol has low data rate and power specifications, its use can prolong battery life. This
feature makes the Zigbee protocol preferred over other technologies such as 802.11. And
Bluetooth. In addition, most Zigbee systems-on-chips (SoCs) support a number of power
modes including a standby mode that occupies the system 99.9% of the time to maximize the
battery life.
Thus, standby power reduction is extremely important for minimizing the power
consumption of Zigbee SoCsstandby power consumption becomes more critical as the
process technology scales down because the leakage current increases exponentially with the
scaling threshold voltage (Vt ) and the gate oxide thickness. To ensure that Zigbee SoCs can
operate properly after returning to the active mode, the logic states containing hardware
calibration, hardware configuration, and network routing information should be preserved
before entering the standby mode. Data preservation is also required to achieve smooth power
mode transition between standby mode and the active mode. Thus, retention flip-flops (RFFs)
aroused in many Zigbee SoCs for storing the logic states, and several types of RFFs have
been widely researched

1.1 ZIGBEE TECHNOLOGY

Zigbee is a IEEE 802.15.4-based specification for a suite of high-level
communication protocols used to create personal area networks with small, low-power digital
radios. The technology defined by the Zigbee specification is intended to be simpler and less
expensive than other wireless personal area networks (WPANs), such as Bluetooth or Wi-Fi.
Applications include wireless light switches, electrical meters with in-home-displays, traffic
management systems, and other consumer and industrial equipment that require short-range
low-rate wireless data transfer. Its low power consumption limits transmission distances to
10100 meters line-of-sight, depending on power output and environmental characteristics.
Zigbee devices can transmit data over long distances by passing data through a mesh network
of intermediate devices to reach more distant ones. Zigbee is typically used in low data rate
1

applications that require long battery life and secure networking (Zigbee networks are
secured by 128 bit symmetric encryption keys.) Zigbee has a defined rate of 250 Kbit/s, best
suited for intermittent data transmissions from a sensor or input device.
Zigbee is a low-cost, low-power; wireless mesh network standard targeted at wide
development of long battery life devices in wireless control and monitoring applications.
Zigbee devices have low latency, which further reduces average current. Zigbee chips are
typically integrated with radios and with microcontrollers that have between 60-256 KB flash
memories. Zigbee operates in the industrial, scientific and medical (ISM) radio bands: 2.4
GHz in most jurisdictions worldwide; 784 MHz in China, 868 MHz in Europe and 915 MHz
in the USA and Australia. Data rates vary from 20 Kbit/s (868 MHz band) to 250 Kbit/s (2.4
GHz band). The Zigbee network layer natively supports both star and tree networks, and
generic mesh networking. Every network must have one coordinator device, tasked with its
creation, the control of its parameters and basic maintenance. Within star networks, the
coordinator must be the central node. Both trees and meshes allow the use of Zigbee routers
to extend communication at the network level. Zigbee builds on the physical layer and media
access control defined in IEEE standard 802.15.4 for low-rate WPANs. The specification
includes four additional key components: network layer, application layer, Zigbee device
objects (ZDOs) and manufacturer-defined application objects which allow for customization
and favour total integration. ZDOs are responsible for a number of tasks, including keeping
track of device roles, managing requests to join a network, as well as device discovery and
security. Zigbee is one of the global standards of communication protocol formulated by the
relevant task force under the IEEE 802.15 working group. The fourth in the series, WPAN
Low Rate/Zigbee is the newest and provides specifications for devices that have low data
rates, consume very low power and are thus characterized by long battery life. Other
standards like Bluetooth and IrDA address high data rate applications such as voice, video
and LAN communications.
Zigbee protocols are intended for embedded applications requiring low power
consumption and tolerating low data rates. The resulting network will use very small amounts
of power individual devices must have a battery life of at least two years to pass Zigbee
certification.
Typical application areas include

Home Entertainment and Control Home automation , smart lighting, advanced

temperature control, safety and security, movies and music

Wireless sensor networks

Industrial control

Embedded sensing

Medical data collection

Smoke and intruder warning

Building automation
Zigbee is a low-cost, low-power, wireless mesh networking standard. The low cost allows

the technology to be widely deployed in wireless control and monitoring applications, the low
power-usage allows longer life with smaller batteries, and the mesh networking provides high
reliability and larger range. The Zigbee Alliance, the standards body which defines Zigbee,
also publishes application profiles that allow multiple OEM vendors to create interoperable
products. The current list of application profiles either published or in the works are:

Home Automation

Zigbee Smart Energy

Telecommunication Applications

Personal Home and Hospital Care

The relationship between IEEE 802.15.4 and Zigbee is similar to that between

IEEE 802.11 and the Wi-Fi Alliance. The Zigbee 1.0 specification was ratified on 14
December 2004 and is available to members of the Zigbee Alliance. Most recently, the
Zigbee 2007 specification was posted on 30 October 2007. The first Zigbee Application
Profile, Home Automation, was announced 2 November 2007.

For non-commercial purposes, the Zigbee specification is available free to the general public.
An entry level membership in the Zigbee Alliance, called Adopter, costs US$ 3500 annually
and provides access to the as-yet unpublished specifications and permission to create
products for market using the specifications.
Zigbee operates in the industrial, scientific and medical (ISM) radio bands; 868 MHz in
Europe, 915 MHz in countries such as USA and Australia, and 2.4 GHz in most jurisdictions
worldwide. The technology is intended to be simpler and less expensive than other WPANs
such as Bluetooth. Zigbee chip vendors typically sell integrated radios and microcontrollers
with between 60K and 128K flash memory, such as the free scale MC13213, the Ember
EM250 and the Texas Instruments CC2430. Radios are also available stand-alone to be used
with any processor or microcontroller. Generally, the chip vendors also offer the Zigbee
software stack, although independent ones are also available.
"In the US, as of 2006, the retail price of a Zigbee-compliant transceiver is approaching
$1, and the price for one radio, processor, and memory package is about $3. Comparatively,
the price of consumer-grade Bluetooth chips is now under $3. In other countries the prices are
higher. For example in the UK, (March 2009) the one-off cost to a hobbyist for a barebones
Zigbee surface-mount transceiver IC varies from 5 to 9, with pre-assembled modules
around 10 more (excluding aerials).
The first stack release is now called Zigbee 2004. The second stack release is called
Zigbee 2006, and mainly replaces the MSG/KVP structure used in 2004 with a "cluster
library". The 2004 stack is now more or less obsolete.Zigbee 2007, now the current stack
release, contains 2 stack profiles, stack profile 1 (simply called Zigbee), for home and light
commercial use, and stack profile 2 (called Zigbee Pro). Zigbee Pro offers more features,
such as multi-casting, many-to-one routing and high security with Symmetric-Key Key
Exchange (SKKE), while Zigbee (stack profile 1) offers a smaller footprint in RAM and
flash. Both offer full mesh networking and work with all Zigbee application profiles
Zigbee 2007 is fully backward compatible with Zigbee 2006 devices: a Zigbee 2007
device may join and operate on a Zigbee 2006 network and vice versa. Due to differences in
routing options, Zigbee Pro devices must become non-routing Zigbee End-Devices (ZEDs)
on a Zigbee 2006 or Zigbee 2007 network, the same as Zigbee 2006 or Zigbee 2007 devices

must become ZEDs on a Zigbee Pro network. The applications running on those devices
work the same regardless of the stack profile beneath them.

1.2 DEVICE TYPES AND OPERATING MODES

Zigbee Coordinator (ZC): The most capable device, the Coordinator forms the root of
the network tree and might bridge to other networks. There is exactly one Zigbee
Coordinator in each network since it is the device that started the network originally (the
Zigbee LightLink specification also allows operation without a Zigbee Coordinator,
making it more usable for over-the-shelf home products). It stores information about the
network, including acting as the Trust Center & repository for security keys.

Zigbee Router (ZR): As well as running an application function, a Router can act as
an intermediate router, passing on data from other devices.

Zigbee End Device (ZED): Contains just enough functionality to talk to the parent
node (either the Coordinator or a Router); it cannot relay data from other devices. This
relationship allows the node to be asleep a significant amount of the time thereby giving
long battery life. A ZED requires the least amount of memory, and therefore can be less
expensive to manufacture than a ZR or ZC.

FIG 1.1: ZIGBEE DEVICES

The current Zigbee protocols support beacon and non-beacon enabled networks. In
non-beacon-enabled networks, an unslotted CSMA/CA channel access mechanism is used. In
this type of network, Zigbee Routers typically have their receivers continuously active,
requiring a more robust power supply. However, this allows for heterogeneous networks in
which some devices receive continuously, while others only transmit when an external
stimulus is detected. The typical example of a heterogeneous network is a wireless light
switch: The Zigbee node at the lamp may receive constantly, since it is connected to the
mains supply, while a battery-powered light switch would remain asleep until the switch is
thrown. The switch then wakes up, sends a command to the lamp, receives an
acknowledgment, and returns to sleep. In such a network the lamp node will be at least a
Zigbee Router, if not the Zigbee Coordinator; the switch node is typically a Zigbee End
Device.

In beacon-enabled networks, the special network nodes called Zigbee Routers

transmit periodic beacons to confirm their presence to other network nodes. Nodes may sleep
between beacons, thus lowering their duty cycle and extending their battery life. Beacon
6

intervals depend on data rate; they may range from 15.36 milliseconds to 251.65824 seconds
at 250 Kbit/s, from 24 milliseconds to 393.216 seconds at 40 Kbit/s and from 48 milliseconds
to 786.432 seconds at 20 Kbit/s.
However, low duty cycle operation with long beacon intervals requires precise timing, which
can conflict with the need for low product cost. In general, the Zigbee protocols minimize
the time the radio is on, so as to reduce power use. In beaconing networks, nodes only need to
be active while a beacon is being transmitted. In non-beacon-enabled networks, power
consumption is decidedly asymmetrical: Some devices are always active, while others spend
most of their time sleeping. Except for the Smart Energy Profile 2.0, Zigbee devices are
required to conform to the IEEE 802.15.4-2003 Low-Rate Wireless Person Area Network
(LR-WPAN) standard. The standard specifies the lower protocol layersthe physical layer
(PHY), and the Media Access Control portion of the data link layer (DLL). The basic channel
access mode is "carrier sense, multiple access/collision avoidance" (CSMA/CA). That is, the
nodes talk in the same way that humans converse; they briefly check to see that no one is
talking before they start, with three notable exceptions. Beacons are sent on a fixed timing
schedule and do not use CSMA. Message acknowledgments also do not use CSMA. Finally,
devices in beacon-enabled networks that have low latency real-time requirements may also
use Guaranteed Time Slots (GTS), which by definition do not use CSMA.

1.3 ZIGBEE ARCHITECTURE

Zigbee uses 128-bit keys to implement its security mechanisms. A key can be associated
either to a network, being usable by both Zigbee layers and the MAC sublayer, or to a link,
acquired through pre-installation, agreement or transport. Establishment of link keys is based
on a master key which controls link key correspondence. Ultimately, at least the initial master
key must be obtained through a secure medium (transport or pre-installation), as the security
of the whole network depends on it. Link and master keys are only visible to the application
layer. Different services use different one-way variations of the link key in order to avoid
leaks and security risks. Key distribution is one of the most important security functions of
the network. A secure network will designate one special device which other devices trust for
the distribution of security keys: the trust centre. Ideally, devices will have the trust center
address and initial master key preloaded; if a momentary vulnerability is allowed, it will be
sent as described above. Typical applications without special security needs will use a

network key provided by the trust centre (through the initially insecure channel) to
communicate.
Thus, the trust centre maintains both the network key and provides point-to-point security.
Devices will only accept communications originating from a key provided by the trust centre,
except for the initial master key. The security architecture is distributed among the network
layers as follows:

The MAC sub layer is capable of single-hop reliable communications. As a rule, the
security level it is to use is specified by the upper layers.

The network layer manages routing, processing received messages and being capable
of broadcasting requests. Outgoing frames will use the adequate link key according to the
routing, if it is available; otherwise, the network key will be used to protect the payload
from external devices.

The application layer offers key establishment and transport services to both ZDO and
applications. It is also responsible for the propagation across the network of changes in
devices within it, which may originate in the devices themselves (for instance, a simple
status change) or in the trust manager (which may inform the network that a certain
device is to be eliminated from it). It also routes requests from devices to the trust center
and network key renewals from the trust centre to all devices. Besides this, the ZDO
maintains the security policies of the device.

FIG 1.2: ZIGBEE ARCHITECTURE

1.4 ZIGBEE GENERAL CHARACTERISTICS

Dual PHY (2.4GHz and 868/915 MHz)

Data rates of 250 kbps (2.4 GHz), 40 kbps ( 915 MHz), and 20 kbps

(868 MHz)

Optimized for low duty-cycle applications (<0.1%)

CSMA-CA channel access Yields high throughput and low latency for low duty cycle
devices like sensors and controls

Low power (battery life multi-month tO years)

Multiple topologies: star, peer-to-peer, mesh

Addressing space of up to: 18,450,000,000,000,000,000 devices (64 bit IEEE address)

65,535 networks

Optional guaranteed time slot for applications requiring low latency

Fully hand-shake protocol for transfer reliability

Range: 50m typical (5-500m based on environment)

1.5 STANBY POWER CONSUMPTION

Standby power, also called vampire power, vampire draw, phantom load, or leaking
electricity ("phantom load" and "leaking electricity" are defined technical terms with other
meanings, adopted for this different purpose), refers to the electric power consumed by
electronic and electrical appliances while they are switched off (but are designed to draw
some power) or in a standby mode. This only occurs because some devices claimed to be
"switched off" on the electronic interface, but are in a different state from switching off at the
plug, or disconnecting from the power point, which can solve the problem of standby power
completely. In fact, switching off at the power point is effective enough; there is no need to
disconnect all devices from the power point. Some such devices offer remote controls and
digital clock features to the user, while other devices, such as power adapters for
disconnected electronic devices, consume power without offering any features (sometimes
called no-load power). All of the above examples, such as the remote control, digital clock
functions andin the case of adapters, no-load powerare switched off just by switching off
at the power point. However, for some devices with built-in internal battery, such as a phone,
the standby functions can be stopped by removing the battery instead.
In the past, standby power was largely a non-issue for users, electricity providers,
manufacturers, and government regulators. In the first decade of the twenty-first century,
awareness of the issue grew and it became an important consideration for all parties. Up to
the middle of the decade, standby power was often several watts or even tens of watts per

10

appliance. By 2010, regulations were in place in most developed countries restricting standby
power of devices sold to one watt.
Standby power is electrical power used by appliances and equipment while switched off or
not performing their primary function, often waiting to be activated by a remote controller.
That power is consumed by internal or external power supplies, remote control receivers, text
or light displays, circuits energized when the device is plugged in even when switched off,
etc. Power can be saved by disconnecting such devices, causing at worst only inconvenience.
While this definition is inadequate for technical purposes, there is as yet no formal definition;
an international standards committee is developing a definition and test procedure. The term
is often used more loosely for any device that continuously must use a small amount of power
even when not active; for example a telephone answering machine must be available at all
times to receive calls, switching off to save power is not an option. Timers, powered
thermostats, and the like are other examples. An uninterruptible power supply could be
considered to be wasting standby power only when the computer it protects is off.
Disconnecting standby power proper is at worst inconvenient; powering down completely, for
example an answering machine not dealing with a call, renders it useless.

11

CHAPTER 2
LITERATURE SURVEY
2.1 TRANCEIVER FOR ZIGBEE APPLICATIONS
A single-chip 2.4-GHz CMOS radio transceiver with integrated baseband processing
according to the IEEE 802.15.4 standard is presented. The transceiver consumes 14.7 mA in
receive mode and 15.7 mA in transmit mode. The receiver uses a low-IF topology for high
sensitivity and low power consumption, and achieves 101 dBm sensitivity for 1% packet
error rate. The transmitter topology is based on a PLL direct-modulation scheme.
Optimizations of architecture and circuit design level in order to reduce the transceiver power
consumption are described. Special attention is paid to the RF front-end design which
consumes 2.4mA in receive mode and features bidirectional RF pins. The 5.77 mm2 chip is
implemented in a standard 0.18- mCMOStechnology. The transmitter delivers +3 dBm into
the 100- differential antenna port. A fully integrated 2.4-GHz transceiver for wireless sensor
network applications based on the IEEE 802.15.4 standard is presented. The IC is fabricated
in a 0.18- m CMOS process and consumes 14.7 mA and 15.7 mA in receive and transmit
mode, respectively. Special attention is paid to design techniques to lower the current
consumption. A receiver RF front-end design is described where a new topology in
conjunction with a stacked LNA configuration leads to a 2.4-mA supply current. The RF
front-end exhibits a 6-dB noise figure and a sensitivity of 101 dBm for 1% packet error rate.
The transmitter topology is improved by using a PLL direct-modulation scheme and
amplifying the LO signal using an efficient push-pull PA. The fully differential RF port
shared between the LNA and PA avoids the antenna switch and, therefore, the associated
insertion loss. A high-level ESD robustness of 6 kV HBM is achieved even at the RF pins.
Low-drop voltage regulators are integrated allowing operation on a single 1.8 V to 3.6 V
supply voltage. The only external components needed are five capacitors for internal supply
voltage decoupling and crystal oscillator loading.
12

2.2 COMPARISION OF WIRELESS PROTOCOLS

Bluetooth (over IEEE 802.15.1), ultra-wideband (UWB, over IEEE 802.15.3), Zigbee
(over IEEE 802.15.4), and Wi-Fi (over IEEE 802.11) are four protocol standards for shortrange wireless communications with low power consumption. From an application point of
view, Bluetooth is intended for a cordless mouse, keyboard, and hands-free headset, UWB
is oriented to high-bandwidth multimedia links, Zigbee is designed for reliable wirelessly
networked monitoring and control networks, while Wi-Fi is directed at computer-to-computer
connections as an extension or substitution of cabled networks. In this paper, we provide a
study of these popular wireless communication standards, evaluating their main features and
behaviours in terms of various metrics, including the transmission time, data coding
efficiency, complexity, and power consumption. It is believed that the comparison presented
in this paper would benefit application engineers in selecting an appropriate protocol. has
presented a broad overview of the four most popular wireless standards, Bluetooth, UWB,
Zigbee, and Wi- Fi with a quantitative evaluation in terms of the transmission time, data
coding efficiency, protocol complexity, and power consumption. Furthermore, the radio
channels, coexistence mechanism, network size, and security are also preliminary compared.
It is not to draw any conclusion regarding which one is superior since the suitability of
network protocols is greatly influenced by practical applications, of which many other factors
such as the network reliability, roaming capability, recovery mechanism, chipset price, and
installation cost need to be considered in the future.

standard

Zigbee

Bluetooth

Wi-Fi

Application focus

Monitoring & control

Cable replacement

Web, video, email

System resource

4 KB - 32KB

250 KB+

16 MB+

Battery life(days)

10-10000+

1-7

Network size

Unlimited

32

Maximum data
rate(KB/S)

20 - 250

720

11000+

13

Transmission
range(meters)

1-100+

1-10+

1-100

Success metrics

Reliability, Power,
Cost

Cost , Convenience

Speed , Flexibility

TABLE 1.1: COMPARISION OF WIRELESS PROTOCOLS

2.3

DC-DC

CONVERTER

FOR

INCREASING

SLEEP-MODE

EFFICIENCY
Battery current is a key parameter that decides the runtime of a portable electronic
system. For low power applications like IEEE 802.15.4 and Zigbee wireless network, the
average battery current drain approximates the sleep mode current drain, since significantly
more time is spent in sleep than in active usage. This paper proposes substituting a DC-DC
converter for a low drop-out (LDO) regulator in the sleep mode power chain, such that the
current drawn from the battery would be less than the actual current drained by the load. The
battery current saving, and hence battery runtime extension, is estimated to be around 35%
based on the analysis of a 65 nm CMOS IEEE 802.15.4/Zigbee low power wireless systemon-chip (SoC) model, whose parameters are extracted from state-of-theart industrial products
and experimental data from advanced nanometer processes. proposes using a DC-DC
converter in the sleep mode power chain of low power electronic system to reduce battery
current.
Compared to the best case scenario of conventional LDO-based power chain
structure, it reduces the battery current by as much as 35% based on the analysis of a leakage
dominated 65 nm CMOS IEEE 802.15.4/ Zigbee wireless SoC model, whose parameters are
extracted from state-of-the-art industrial products and experimental data. However, does not
detail the design of the ultra-light-load DC-DC converter with said efficiency, since
integrated DC-DC converters with similar output power profile (1-100 W) with above 80%
efficiency using all-digital PFM control has already been reported.

2.3.1 PASSIVE WAKE UP SCHEME

In resource limited mobile computing devices (wireless sensor networks), energy
saving is a critical design task. However, existing wake-up mechanisms encounter a critical
trade-off between energy consumption and response time. In this paper, we propose a passive
14

RF wake up (PRFW) scheme instead of time-based scheme to wake up node that indeed
needs to wake up. The PRFW scheme is enabled by a PRFW hardware module sensing radio
signal from other nodes. Analysis of energy consumption and delay shows that the power
saving capability and wake-up delay can be improved by using the PRFW scheme.
We have presented a passive RF wake-up (PRFW) scheme for wireless sensor
networks, which helps to achieve the balance between energy saving and delay. The hardware
architecture of note equipped with a PRFW module that supports the PRFW scheme is
described. By sensing energy from the radio signals, the PRFW module provides a interrupt
to the MCU. The MCU detects the preamble and wakes up RF transceiver when wake-up
signal is indeed to wake itself up. The analysis results show that, based on the PRFW, nodes
can be woken up timely when it is necessary to wake up with the aid of extremely low power.

2.4 AN ULTRA LOW-POWER CMOS TRANCEIVER

We implemented and evaluated a fully integrated 2.4 GHz CMOS RF transceiver
using various low-power techniques for low-rate wireless personal area network (IEEE
802.15.4 LR_WPAN) applications in 0.18- m CMOS technology. In order to achieve an ultra
low power consumption, a RC oscillator (OSC) operating below 200 nA, a regulator
operating below 200 nA for sleep mode, a quick start block for the crystal oscillator, a passive
wake-up circuit, a LNA with negative gm, a current bleeding mixer, and a stacked VCO are
all implemented in this transceiver. The transmitter achieves less than 5.0% error vector
magnitude (EVM) at 5 dBm output, and the receiver sensitivity is dBm. The sensitivity of the
wake-up block is dBm. The current consumption is below 14.3 mA for the data receiving
mode, 16.7 mA for the transmitter, and less than 600 nA for the sleep mode from a 1.8 V
power supply. That is considered to be lowest for the 2.4 GHz CMOS Zigbee transceiver
compared to open literature results.
It has presented a fully integrated ultra-low power transceiver, adopting various
techniques for low power consumption and completely complying with the IEEE 802.15.4
standard. In order to reduce the current consumption in sleep mode, the sleep block regulator,
the RC (resistors and capacitors) oscillator, the quick-start oscillator, the passive wake-up
circuit are implemented. The stacked VCO, the LNA with negative and the current bleeding
mixer are also implemented for the active mode. The current consumption is under 14.3 mA
for the data receiving mode, 16.7 mA for the transmitter at 5 dBm output power, and less than
600 nA for the sleep mode for a 1.8 V power supply. The transmitter achieves less than 5.0%
error vector magnitude (EVM) at 5 dBm output and the receiver sensitivity is dBm. We
15

consider this fully integrated transceiver consumes the lowest energy among different 2.4
GHz CMOS Zigbee transceivers published.

2.5 DATA CENTRIC STORAGES IN ZIGBEE SOCS

Data Centric Storage is a recent paradigm that results more efficient than other storage
techniques (such as local or external storage) in Wireless Sensor Networks (WSN). In this
work we consider the use of this storage paradigm in WSN based on the Zigbee standard. In
particular we propose a novel protocol (Z-DaSt) that exploits the routing and addressing
features of Zigbee (that are based on routing trees) to distribute data to the sensors. The
protocol also features Quality of Service in the storage of data by enabling the user to specify
the amount of redundancy to be used in the storage of each datum. This work evaluates ZDaSt by analysis and simulation, and compares its performance to DCS-GHT. The simulation
results show that Z-DaSt is a viable alternative to DCS-GHT for practical cases, in particular
for low to moderate network densities.
we presented Z-DaSt, a novel DCS protocol tailored to be used over Zigbee-enabled
WSN. Z-DaSt provides Quality of Service to the data storage, i.e. it lets the user application
specify the number of devices that should store a datum. The cost of Z-DaSt was evaluated by
means of theoretical analysis, and of simulations. The simulations also presented a
comparison with DCS-GHT in terms of the cost of store and retrieve operations, and the
results showed that Z-DaSt's operations are better suited to low or moderate network
densities, hence it can be considered a viable alternative in such cases. Future work will
address the load balancing of data over the devices, for example by employing a generalized
hash function to distribute meta-data to home nodes. Another issue that we will cope with is
the comparison of the analytical model we developed with simulations on the performance of
the protocol.

2.6 MTCMOS CIRCUIT SCHEME

It proposes a new multi threshold-voltage CMOS circuit (MTCMOS) concept aimed at
achieving high-speed, ultralow-power large-scale integrators (LSIs) for battery driven
portable equipment. The balloon circuit scheme based on this concept preserves data during
the power-down period in which the power supply to the circuit is cut off in order to reduce
the standby power. Low-power, high-speed performance is achieved by the small preserving
circuit which can be separated from the critical path of the logic circuit. This preserving
circuit is not only three times faster than a conventional MTCMOS one, but it consumes half

16

the power and takes up half the area. Using this scheme for an LSI chip, 20-MHz operation at
1.0 V and only a few nA standby current was achieved with 0.5-m CMOS technology.
Moreover, this scheme is effective for high-speed and low-power operation in quartermicrometer and finer devices. We have developed a new 1-V high-speed MTCMOS circuit
scheme for power-down application circuits. The main feature is a small, fast, low-power
balloon circuit for preserving data. A balloon DFF is not only three times faster than a
conventional MTCMOS DFF, but it consumes half the power and takes up half the area. This
is a very efficient circuit scheme for high-performance power-down application circuits using
MTCMOS technology. Moreover, it is effective for high-speed and low-power operation in
sub-quarter-micrometer and finer devices. Consequently, this scheme brings smart power
management to LSIs.

2.6.1 LOW STAND BY POWER FLIP-FLOP

A flip-flop using a combination of thin and thick gate transistors combines high
performance and low standby power. Setup and hold times are controlled by the master latch
implemented in high performance transistors, while a thick gate slave latch provides state
retention at low standby power when the high performance circuit power supply is gated off.
The design has reduced circuit and power-down control complexity compared to previously
described circuits using thick gate shadow latches for low standby power state storage.
Measured test chip results on a foundry 130 nm process prove the viability of the design. The
thick gate shadow latches are shown to have good retention capability at low supply voltages,
suggesting that reduced shadow latch supply voltage during standby will be effective at
mitigating the drain to bulk leakage components that are increasingly limiting for low power
standby modes.
A master-slave flip-flop has been presented that reduces logic circuit standby power
by over 3 orders of magnitude while retaining state on deep submicron ICs. This is
accomplished by gating power from all but the low leakage thick gate slave latch transistors.
The proposed MSFF requires no additional control signals and hence has less complicated
control timing than previous thick gate shadow latch designs. It uses nine fewer thin tOX and
two fewer thick tOX transistors than the previous MSFF design [5], reductions of 36% and
33%, respectively, which reduce the area cost. Clock frequency is limited by the write delay
of the thick gate slave latch but high performance is obtained. The choice of a rising or falling
edge-triggered design is determined by whether VDD or VSS supply gating is employed.
Simulations on 65 nm process using predictive models and 180 nm thick gate standby mode
17

storage transistors show similar standby power savings of over 5000x, demonstrating
effectiveness for many process generations. This design uses the PMOS slave latch pass
transistors M5 and M6 and the PMOS M5 and M6 reduce the maximum clock frequency,
evident by the ST and STN nodes at VDD = 0.8 V. Finally, reducing the standby storage latch
power supply voltage VDDTG can be used to limit the drain to bulk band to band tunnelling
(IZENER) leakage component, which is increasingly limiting for low standby power modes.

2.6.2 SCAN-RETENTION MECHANISM

It presents a methodology for unifying the scan mechanism and data retention in latches
which leads to scan able latches with the data retention capability achieved at a very low
power overhead during the active mode. A detailed analysis of power and area overhead is
presented, with layout examples for various common latch styles. Implications of using
different power gating techniques for reducing leakage during sleep mode on the design of
retention latches are considered, including well biasing for leakage control and sharing wells
between gated logic and retention latch devices.
A methodology for unifying the scan and data retention mechanisms in latches was
presented which leads to scan able latches with the data retention capability achieved at a
very low power overhead during the active mode. The exact amount of the power and
performance and area overhead was measured using net lists extracted from the layouts built
in a state of the art 0.13um technology. The additional overhead of the data retention feature
over the scan mechanism is very small, and so is the additional overhead of the scan feature
over the data retention mechanism. The proposed integrated scan-retention mechanism
achieves both features at the cost of one.

2.6.3 DATA RETENTION FLIP-FLOPS

A novel technique for retaining data in flip-flops in power-down applications is
presented. In flip-flops data is stored in cross-coupled inverters. Cross-coupled inverters can
hold their states in the power down mode, if their inputs are properly gated. Based on this
fact, simple clock and data gating circuitries are employed in flip-flops to retain their data in
the power-down mode without using any extra data-preserving latches. In a predictive 70nm
technology node, a transmission-gate flip-flop based on the proposed data-retention scheme
exhibits 18X reduction in standby leakage compared to a conventional transmission-gate flipflop. The proposed data-retention scheme also exhibits 40% area reduction compared to the
conventional balloon scheme.
18

A 16-bit shift-register using data-retention flip-flops has been successfully fabricated

and tested in a 0.25m CMOS process. A novel technique for retaining data in flip-flops in
power-down applications is presented. In flip-flops data is stored in cross-coupled inverters.
Cross-coupled inverters can hold their states in the power down mode, if their inputs are
properly gated. Based on this fact, simple clock and data gating circuitries are employed in
flip-flops to retain their data in the power-down mode without using any extra datapreserving latches. In a predictive 70nm technology node, a transmission-gate flip-flop based
on the proposed data-retention scheme exhibits 18X reduction in standby leakage compared
to a conventional transmission-gate flip-flop. The proposed data-retention scheme also
exhibits 40% area reduction compared to the conventional balloon scheme. A 16-bit shiftregister using data-retention flip-flops has been successfully fabricated and tested in a 0.25um
CMOS process. A novel data-retention scheme for power-down applications and applicable
to different types of flip-flops is proposed. The proposed data-retention flip-flops need no
extra data preserving latches, and therefore impose minimal area, power, and delay penalties
for data-retention. The effectiveness of the proposed scheme was demonstrated by design and
fabrication of a 16-bit data-retention shift-register.

19

CHAPTER 3
EXISTING SYSTEM
3.1 BALLOON CIRCUIT RETENTION FLIP-FLOP
Fig. 3.1 shows the concept of the new MTCMOS circuit for preserving data during the
sleep period. It involves the use of a memory circuit, which is always powered, and a switch.
We call the memory circuit a balloon circuit because of its shape and because we blow
up the memory with data at the beginning of the sleep mode to preserve it and let the data
out at the end to restore it. This circuit is connected to node A of the MTCMOS logic circuit.
This scheme has two states according to the circuit modes; sleep and active. In the sleep
mode, the balloon circuit preserves data using the memory circuit and a leakage current from
the memory circuit to the logic circuit is cut off by the switch .In the active mode, the balloon
circuit does not add to the load at the node because it is separated from the node by the switch
During the transitional period between these two states, the Switch becomes on-state to read
data from the node or restore data to the node.
3.1.1 OPERATION

20

FIG 3.1 OPERATION OF BALLON CIRCUIT RFF

In the active period, the balloon circuit is separated from the node by TG2. This keeps the
load down. In this period, the balloon circuit does not operate.
During the sleep-in period, which is a transition period from the active period to the sleep
period, TG2 is turned-on so that the balloon circuit can read data from the node.
In the sleep period, the memory just holds the data. TG2 cuts off the leakage current path
from the memory circuit. In this period, the state in the balloon circuit does not change.
During the sleep-out period, which is a transition period from the sleep period to the active
period, the balloon circuit writes the data back to the node, thus restoring thenode to its
previous state.
This operation enables active-mode operation to resume smoothly. The state of the
balloon circuit only changes during the transitional periods between sleep and active periods.
Since the balloon memory circuit and the switch do not operate in the active period, the
balloon circuit does not become a bottleneck during high-speed operation of the lowapplication circuit. Thus, the balloon circuit does not need to be fast. This means that it can
be designed with a high- and the smallest MOS transistors, thereby allowing a lower standby
power and smaller increase in area.

3.2 SRAM-BASED RFF

21

FIG 3.2 STRUCTURE OF SRAM BASED RFF

The master latch is based on a cross-coupled-inverter latch, which is generally used in
a typical CMOS static D flip-flop (DFF), whereas the slave latch consists of a transmission
gate (TG1), inverters (INV2 and INV5), and a 6T SRAM cell. All gates on the data-to-output
path are composed of thin-oxide transistors to avoid performance degradation, and the 6T
SRAM cell uses thick-oxide transistors to reduce the standby leakage current. As the SRAMbased RFF adopts the MTCMOS scheme, the thin-oxide transistors and access transistors
(M5 and M6) are originally supplied by VDD,virtual, whereas the retention latch (INV3 and
INV4) is originally supplied by VDD,core. However, to use the power management scheme
for turning off the voltage regulator in the standby mode, VDD,virtual and VDD,core used
for the transistors are changed to VDD,core and VDD,IO, respectively. Then, the voltage
regulator generating VDD,core can be turned off, and the retention latch powered by VDD,IO
retains the logic state in the standby mode. The SRAM-based RFF uses access transistors to
convert the voltage level. In the active mode, access transistors are turned on and perform
write/read access.
During write access, the access transistors provide differential write-access, enabling
a conversion in the voltage level from VDD,core to VDD,IO when the clock is asserted high.
The logic states at X and Y are the low and high VDD,core levels, respectively, or vice versa.
A low state is completely transferred to the retention latch through M5 (or M6), after which
22

INV4 (or INV3) generates a high VDD,IO level through M2 (or M1). A high VDD,core is
transferred as (VDD,coreVt_thick) (Vt_thick is Vt of the thickoxide transistor) to the
retention latch through M6 (or M5), after which the access transistor that transferred the high
VDD,core is turned off, avoiding the creation of a dc current path. During read access, the
access transistors supply the correct state to the VDD,core domain. In the standby mode,
VDD,core is turned off, and the clock is asserted low before the access transistors are turned
off; as a result, the retention latch supplied by VDD,IO is isolated by the access transistors
and is able to hold data. The SRAM-based RFF effectively reduces the area overhead by
eliminating additional control codes for power mode transition and embedding the retention
latch into the slave latch. The standby power is also reduced, as the leakage paths in the
standby mode (I1, I2, I3, and I4) include the thick-oxide transistors M1M6.
However, several problems can occur because the retention latch is not on the data-tooutput path. After write access for the high VDD,core level is performed through M5 when
CK is asserted high, M5 is turned off, and node X is left floating temporarily as CK becomes
low. Node X is vulnerable to glitch-creating noise such as cross-talk because it is floating
until the value of node X drops to (VDD, coreVt_thick). During the transition from the
standby mode to the active mode, data in the retention latch need to be transferred to nodes X
and Y; however, if the node value of slv_left is high, X becomes (VDD,coreVt_thick) owing
to the threshold drop, and a dc current will flow through the p and nMOS in INV2, possibly
inducing an incorrect output. To check the read-error rate of the SRAM-based RFF, 10 000
Monte Carlo simulations were performed with the Vt variation. In the simulation node, X was
set to the initial value of low, and the temperature and VDD,core were set to 0 C and 1.1 V
to model the worst condition. The simulation results indicate that 0.12% of SRAM-based
RFFs generate an incorrect output. The read-error rate increases with technology scaling
because the voltage margin for correct operation, [(VDD,coreVt_thick)(VDD,core)/2], is
reduced when VDD,core scales down. This implies that it is difficult to implement an SRAMbased RFF with deep submicrometer process technology.
The master latch and clocking are conventional circuits implemented in the thin gate
transistors. The setup and hold times for the MSFF are the same as for an entirely thin gate
design, since the timing critical path passes from input D to output Through only the fast thin
gate transistors. The slave latch is comprised of thick gate, high Transistors M1-M6.
Transistors M1-M4 forms the thick gate flip-flop slave latch and M5-M6 provides differential
write access when the clock is asserted high. NMOS isolation transistors M5 and M6 are
23

controlled by the VDD power supply of the thin gate circuitry. Unlike the schemes shown in
the thick gate latch is always used for the slave latch storage during both active and standby
modes.
When the VDD power supply is gated off by driving ENN to VDDTG transistor
leakage currents pull VDD toVSS and isolate the thick gate from the thin gate circuits as
transistors M5 and M6 cut-off. The circuit logic state is retained by the un-gatedVDDTG
power supply, while the low leakage thick-gate transistors minimize standby power.
Transistors M5 and M6 supply the correct state to the thing ate circuit domain, which also
contains all combinational logic, as it powers up. The clock must be asserted low before and
during power-down, as well as while the supply voltage is restored, to avoid writing the thick
gate latch. Consequently, for NMOS M5-M6 the entire clock tree can reside in the VDD
domain, allowing that leakage component to be completely suppressed. It is frequently easier
to gate VSS rather than VDD since the latter uses NMOS rather than PMOS supply gating
transistors.
In addition to the greater drive current of the former, it is also easier to provide sufficient
gate overdrive VGS Vt by using a high voltage on the NMOS transistor MG2. This supply
gating transistor is ideally a higher Vt thick gate device as well. In this case, when the power
is gated off, VSS will rise to VDD.

3.3 LEVEL-CONVERTING RFF

24

FIG 3.3 STRUCTURE OF SINGLE BIT LEVEL CONVERTING RFF

The master latch is also based on a cross-coupled-inverter latch as the DFF, and an
additional data transmission path (M3 and M1) is embedded. Both thin- and thick-oxide
transistors are used, and the core logic and retention logic are supplied by VDD,core and
VDD,IO, respectively. Level-up conversion from the VDD,core domain in the master latch to
the VDD,IO domain in the slave latch is achieved through an nMOS pass-transistor levelconversion scheme similar to that developed in [18]. The proposed RFF operates as follows.
When nodes X and Y (or Y and X) in the master latch are high and low, respectively, an
access transistor M4 (or M3) is turned on, and another access transistor M3 (or M4) is turned
off. Then, the ON-state access transistor M4 (M3) forms a transmission path between the
master latch and the slave latch, and node Y (X) becomes an input of the transmission path. In
other words, only the transmission path from the master latch to the slave latch is determined
on the basis of the state of data in the master latch, and the voltage level can be converted in
the slave latch without generating a dc-current path because only a low signal is transmitted
at all times.
Thus, the VDD, core domain is converted into the VDD, IO domain without the need
for an additional level-up converter. Level-down conversion from VDD, IO to VDD,core
occurs at INV3 and INV4, which are composed of thick-oxide transistors but supplied by
VDD,core. In the standby mode, when RSTb is asserted low, CK becomes low, and
25

VDD,core is collapsed by turning off the voltage regulator; in this case, the slave latch is
isolated by turning off the access transistors (M1 and M2) and operates as a retention latch to
hold logic states by VDD,IO that is always turned on. It is important to note that the sizes of
the transistors on the data-to-output path need to be determined carefully. There are two
considerations, standby power and write-ability. As the standby power is consumed by only a
slave latch, INV1 and INV2 should be sized to minimize the sub threshold leakage current
that is generally proportional to the width of the transistor. However, in deep sub micrometer
process technology, Vt sharply decreases with a decrease in the channel width, and this is
called the inverse narrow width effect (INWE). This effect results in an exponential increase
in the leakage current, making the INWE increasingly important with technology scaling. The
second consideration is write-ability.
The write operation is performed by pulling down slv_left or slv_right because the master
latch always transmits a low signal to the slave latch in the proposed RFF. The pull-down
network of slv_right (slv_left) consists of M1 and M3 (M2 and M4) and the nMOS in INV6
(INV5). However, the pull-up network of slv_right (slv_left) composed of two-stacked
pMOS transistors in INV2 (INV1) is simultaneously turned on if the data to be transferred is
different than the retained data. Thus, the pull-down network (three-stacked nMOS
transistors) should be much stronger than the pull-up network (two-stacked pMOS transistors
in INV1 or INV2). The pull-down network is designed to be 10 times stronger than the pullup network in the proposed RFF. To check the write operation, 1 000 000 Monte Carlo
simulations were performed with a high VDD,IO of 2.7 V at a high temperature of 85 C to
consider the worst condition. The results show no failures and thus, reliable write operation is
verified. The proposed RFF does not require an additional retention latch nor does it require
the write/read operations necessary in SRAM-based RFFs. As all standby leakage paths (I1,
I2, I3, and I4) in the proposed RFF consist of thick-oxide transistors, the standby leakage
current will be less than that of an SRAM-based RFF
Further reduction in the standby leakage in paths I3 and I4 can be achieved by arranging
the access transistors (M1 and M3, and M2 and M4) in a stacked structure, and the inverters
(INV1 and INV2) in the slave latch are designed using stacked p/nMOS transistors, allowing
the standby leakage of I1 and I2 to also be reduced. Because the retention latch in the
proposed RFF is located on the data-tooutput path, and level-up conversion from the
VDD,core domain to the VDD,IO domain is achieved through an nMOS passtransistor levelconversion scheme, the problems of threshold drop in the SRAM-based RFF are resolved
with only a degradation in speed. However, the speed degradation is not a problem in this
26

target application because the digital logic in Zigbee SoCs operates at a low frequency of
approximately 20 MHz. Thus, the proposed RFF can be appropriately applied to the Zigbee
SoCs and also implemented using deep submicrometer process technology. In the standby
mode, logic states are preserved in a slave latch composed of thick-oxide transistors utilizing
an I/O supply voltage (VDD,IO) that is always turned on.
To use both the core supply voltage (VDD, core) and VDD,IO domains without incurring
problems due to the threshold drop, as in anSRAM-based RFF, an nMOS pass-transistor
level-conversion scheme is embedded into the data-to-output path. Because the power
management scheme using the proposed RFF enables the voltage regulator generating
VDD,core to be turned off in the standby mode, the standby power consumption can be
significantly reduced.
The proposed RFF also reduces the area overhead because it does not require an
additional retention latch, a level-up converter, control signals for power mode transition, and
power switches.

3.4 ADVANTAGES, DISADVANTAGES AND APPLICATIONS

3.4.1 ADVANTAGES
Leakage current reduction
Static/Leakage power, originates from substrate currents and sub threshold leakages.
For technologies 1 m and above, Switching was predominant. However for deep-submicron
processes below 180nm, Leakage becomes dominant factor. Leakage power is a major
concern in recent technologies, as it impacts battery lifetime. CMOS technology has been
extremely power-efficient when transistors are not switching or in stand-by mode, and system
designers expect low leakage from CMOS chips. To meet leakage power constraints,
multiple-threshold and variable threshold circuit techniques are often used. In multiplethreshold CMOS, the process provides two different threshold transistors. Low-threshold are
employed on speed-critical sub-circuits and there are fast and leaky. High-threshold
transistors are slower but exhibit low sub-threshold leakage, and they are employed in
noncritical/slow paths of the chip. As more transistors become timing-critical multiplethreshold techniques tend to lose effectiveness.

3.4.2 DISADVANTAGES
27

Only single bit is used.

3.4.3 APPLICATIONS

Zigbee socs are used for short distance communication.

These are used for monitoring and controlling the devices.

28

CHAPTER 4
PROPOSED SYSTEM
4.1 RETENTION FLIP-FLOPS
To achieve higher density and performance and lower power consumption, CMOS
technology has been scaled down for several decades. Supply voltage (VDD) has been scaled
down in order to keep the power consumption under control. Hence, the transistor threshold
voltage (Vth) has to be commensurately scaled to maintain a high drive current and achieve
performance improvement. However, the threshold voltage scaling results in the substantial
increase of the sub threshold leakage current. Therefore, as a result of technology scaling,
leakage power is becoming a major contributor to total power consumption. Leakage current
is present in both active and standby modes of operation. In order to reduce the standby
leakage power consumption, circuits can be put in the power-down mode by switching-off
the power during the standby mode. The power can be switched-off by switching-off either
the supply voltage (VDD) or ground (GND) of the circuit. The transistors switching-off the
power are called sleep transistors. For switching-off the VDD (gated-VDD), PMOS sleep
transistors are required between the real VDD and virtual VDD of the circuit. However, for
switching-off the GND (gated-GND), NMOS sleep transistors are used between the real
GND and virtual GND of the circuit. Since the sleep transistors are fairly large, gated-GND is
preferred to gated-VDD because the NMOS sleep transistors can be much smaller than the
PMOS sleep transistors.
The state of a circuit which is stored in flip-flops may be lost in the power-down
mode. Therefore, in power down applications where the state of the circuit is required to be
preserved, shadow or balloon latches that state of the circuit during the power-down mode.
The balloon latch and some switches which are not in the critical paths use high threshold
voltage (high-Vth) transistors to reduce their leakage power, since they are always powered.
This conventional scheme requires extra data-preserving latches (balloon latches) and
complicated timing for transferring data back and forth between balloon latches and flip-flops
on any transition from power-down to active mode and vice versa. To overcome these
problems, several data-retention schemes have been proposed for power-down applications.
However, in some of the previous techniques, depending on the internal state of flip-flops in
the power-down mode, there can be sneak leakage paths due to interaction between gates
29

which are always powered and gates which are powered down. In leakage feedback flip-flop
has been proposed that eliminates all possible sneak leakage paths during the power-down
mode.
The internal clock and data gating circuitry is only composed of one inverter and one
PMOS transistor. The inverter of the clock-gating circuitry may not be required if the clock is
already buffered through the the clock distribution network. In the sleep mode, the PMOS
transistor pulls up the clock input node of the flip-flop to VDD. Therefore, the data input is
also automatically gated by the transmission gate at the input of the flip-flop. Moreover, the
loop of the cross coupled inverters in the master latch is closed to retain the data stored in the
master latch. In this scheme only the inverter that generates signal CKB is required to be
always powered, and therefore, can be implemented using high-Vth transistors. The dataretention TGFF (DR-TGFF) and the balloon-TGFF are designed in the 70nm CMOS
technology node, using Berkeley Predictive Technology Models. The TGFF without any
sleep transistor or data-retention circuitry and with all low-Vth transistors is also designed for
comparison

4.2 RETENTION ARCHITECTURE IN ZIGBEE SOCS

There are three types of retention architectures for zigbee socs as follows.

4.2.1 RETENTION LOGIC WITH THE MULTI THRESHOLD-VOLTAGECMOS

SCHEME
A power-gating scheme using multithreshold-voltageCMOS (MTCMOS) represents one
solution for reducing the standby power and many conventional RFFs adopt theMTCMOS
scheme shown in Fig4.1. Retention logic supplied by VDD, core preserves the logic states in
the standby mode, whereas the computation logic supplied by the virtual supply voltage
(VDD, virtual) is power-gated to reduce the standby power .However, the power reductionism
limited because the voltage regulator generating VDD,core(VR2) must remain on during the
standby mode to supply detention logic. Another flaw of the power-gating scheme using
MTCMOS is the area inefficiency due to the requirement of large head/foot switches.

30

FIG 4.1 MTCMOS SCHEME

4.2.2 RETENTION LOGIC WITH ULTRALOW SUPPLY VOLTAGE

The usage of an ultralow supply voltage for data retention allows for the minimization of
the leakage power during the standby mode. Thus, the power management scheme with the
ultralow-supply voltage retention logic shown in Fig.4.2 is another solution for reducing the
standby power. Because all the transistors in the retention logic operate in weak inversion
with a low drain-to-source voltage, the sub threshold leakage current is exponentially
reduced. Compared with the scheme in Fig.4.1 an additional voltage regulator (VR3)
generating an aggressively scaled supply voltage is employed only for the retention logic at
the cost of area overhead and active power.
31

This power management scheme also has the same disadvantage as the power
management scheme in Fig.4.2 in that the voltage regulator for the retention logic (VR3)
must be turned on during the standby mode. Thus, a power management scheme to turn off
the voltage regulator in the standby mode is required.

FIG 4.2 ULTRA LOW SUPPLY VOLTAGE

4.2.3 RETENTION LOGIC WITH I/O SUPPLY VOLTAGE
The power management scheme for turning off the voltage regulator in the standby mode
is shown in Fig.4.3 In this architecture, the voltage regulator for the retention logic is directly
supplied fromVDD,IO. The standby power of the retention logic itself is actually a little large
owing to the use of VDD, IO that is larger than VDD,core. However, compared with the
power consumption of the voltage regulator for retention logic, the increase in the standby
power caused by VDD, IO is insignificant. The current flowing through the turned-on voltage
regulator is a few microamperes. This current is much larger than that flowing through the
several hundred bits of the retention logic required in Zigbee SoCs.To use this power
management scheme, level conversion between the VDD, core and VDD, IO domains should
be supported; otherwise, the power management scheme cannot be applied owing to the dc
32

current path created by the level difference between VDD,core and VDD,IO. The proposed
RFF achieves level-up conversion from VDD,core to VDD,IO by an embeddednMOS passtransistor level-conversion scheme using a low-only signal-transmitting technique.

FIG 4.3 I/O SUPPLY VOLTAGE

4.3 MULTI BIT LEVEL CONVERTING RFF

Retention flip-flops have been widely used in power gated designs to store data
during sleep mode. However, their excessive area and leakage power render it imperative to
minimize the total retention storage size. The current industry practice replaces all flip-flops
with single bit retention ones, which significantly limits the design freedom and yields
suboptimal designs.
Toward this, for the first time in the literature, we propose the concept and the design
of multi bit retention flip-flops, with which only selected flip-flops need to be replaced. The
technique can significantly reduce the number of bits that need to be stored and thus the
leakage power, but needs several clock cycles for mode transition. In addition, an efficient
assignment algorithm is developed to minimize the total retention storage size subject to
mode transition latency constraint.
33

The proposed level-converting RFF is shown in Fig. 3. The master latch is also based
on a cross-coupled-inverter latch as the DFF, and an additional data transmission path (M3
and M1) is embedded. Both thin- and thick-oxide transistors are used, and the core logic and
retention logic are supplied by VDD, core and VDD,IO respectively. Level up conversion
from the VDD, core domain in the master latch to the VDD, IO domain in the slave latch is
achieved through an nMOS pass-transistor level-conversion.

FIG4.4: STRUCTURE OF MULTI BIT LEVEL CONVERTING RFF

4.3.1 OPERATION
The proposed RFF operates as follows When nodes X and Y (or Y and X) in the master
latch are high and low, respectively, an access transistor M4 (or M3) is turned on, and another
access transistor M3 (or M4) is turned off. Then, the ON-state access transistor M4 (M3)
forms a transmission path between the master latch and the slave latch, and node Y (X)
becomes an input of the transmission path. In other words, only the transmission path from
the master latch to the slave latch is determined on the basis of the state of data in the master
latch, and the voltage level can be converted in the slave latch without generating a dc-current
path because only a low signal is transmitted at all times.
Thus, the VDD, core domain is converted into the VDD,IO domain without the need for an
additional level-up converter. Level-down conversion from VDD, IO to VDD,core occurs at
INV3 and INV4, which are composed of thick-oxide transistors but supplied by VDD,core. In
the standby mode, when RSTb is asserted low, CK becomes low, and VDD,core is collapsed
34

by turning off the voltage regulator; in this case, the slave latch is isolated by turning off the
access transistors (M1 and M2) and operates as a retention latch to hold logic states by
VDD,IO that is always turned on. It is important to note that the sizes of the transistors on the
data-to-output path need to be determined carefully. There are two considerations, standby
power and write-ability. As the standby power is consumed by only a slave latch, INV1 and
INV2 should be sized to minimize the sub threshold leakage current that is generally
proportional to the width of the transistor. However, in deep sub micrometer process
technology, Vt sharply decreases with a decrease in the channel width, and this is called the
inverse narrow width effect (INWE). This effect results in an exponential increase in the
leakage current, making the INWE increasingly important with technology scaling.

4.4 ADVANTAGES AND APPLICTIONS

ADVANTAGES

Power optimization

Effective use of area

APPLICATIONS

On chip networks

Processing units

CHAPTER 5
HARDWARE REQUIREMENT

5.1 INTEGRATED CIRCUITS

The term integrated circuit is used to describe a wide variety of devices ranging from
simple logic gates through to complex state-of- the-art microprocessors. Integrated circuits
basically consist of a circuit, typically made up from a number of transistors and their
interconnections, fabricated from a single semiconductor chip or die.
5.1.1

ANALOGUE INTEGRATED CIRCUITS

Analogue integrated circuits include a wide rang of applications, many of which are

highly specific. Some examples are the simple operational amplifiers and timers, and the
more complex FM stereo decoders and single-chip FM radios.
35

There has been a trend towards fabricating the more commonly used analogue circuits
into single chip form. An example of this is FM radio receiver, which is a fairly complex
circuit when fabricated from discrete components. A FM radio receiver can now be
constructed from a FM radio chip, an audio amplifier chip and a few discrete passive
components.
5.1.2

DIGITAL INTEGRATED CIRCUITS

Digital integrated circuits are devices, which are functionally based on logic gates

(AND & OR gates). They are commercially available in families of devices which take their
name from the fabrication method used to manufacture the devices from different families are
not readily compatible in the same circuit. The more common types of logic integrated
circuits are typically represented in each family of devices like TTL, Schottky TTL, CMOS
and the new high speed CMOS. The CMOS family devices have a very low power
consumption that makes them very popular for many applications where very high speeds are
not required.

5.1.3

COMPUTER INTEGRATED CIRCUITS

Computer integrated circuits are devices, which form the active components of a computer
system. They are often used in conjunction with digital integrated circuits, which provide a
glue logic function. Computer integrated circuits can be functionally divided into
microprocessors, memory devices and peripheral control devices.

5.2 HISTORY OF ICs

The first silicon chip or integrated circuit consisting of many transistors fabricated on
the same piece of silicon was made at Fairchild in 1959. More recent developments have
been towards miniaturization-packing more and more active components or gates on to a
single chip of silicon. The level of device complexity is usually referred to as a scale of
integration. The evolution from scale integration (SSI), through large-scale integration (LSI),
to very large scale integration (VLSI) has already occurred, and the scale is running out of
adjectives. The scale of integration is based on the number of logic elements that constitute a
device.

36

5.3 INTRODUCTION TO VLSI

VLSI stands for "Very Large Scale Integrated Circuits". It's a classification of ICs. An
IC of common VLSI includes about millions active devices. Typical functions of VLSI
include Memories, computers, and signal processors, etc. A semiconductor process
technology is a method by which working circuits can be manufactured from designed
specifications. There are many such technologies, each of which creates a different
environment or style of design. In integrated circuit design, the specification consists of
polygons of conducting and semiconducting material that will be layered on top of each other
to produce a working chip. When a chip is custom-designed for a specific use, it is called an
application-specific integrated circuit (ASIC). Printed-circuit (PC) design also results in
precise positions of conducting materials, as they will appear on a circuit board; in addition,
PC design aggregates the bulk of the electronic activity into standard IC packages, the
position and interconnection of which are essential to the final circuit. Printed circuitry may
be easier to debug than integrated circuitry is, but it is slower, less compact, more expensive,
and unable to take advantage of specialized silicon layout structures that make VLSI systems
so attractive. The design of these electronic circuits can be achieved at many different
refinement levels from the most detailed layout to the most abstract architectures. Given the
complexity that is demanded at all levels, computers are increasingly used to aid this design
at each step. It is no longer reasonable to use manual design techniques, in which each layer
is hand etched or composed by laying tape on film. Thus the term computer-aided design or
CAD is a most accurate description of this modern way and seems more broad in its scope
than the recently popular term computer-aided engineering (CAE)
5.4 APPLICATIONS OF VLSI
Electronic systems now perform a wide variety of tasks in daily life. Electronic
systems in some cases have replaced mechanisms that operated mechanically, hydraulically,
or by other means; electronics are usually smaller, more flexible, and easier to service. In
other cases electronic systems have created totally new applications. Electronic systems
perform a variety of tasks, some of them visible, some more hidden:

Personal entertainment systems such as portable MP3 players and DVD players

perform sophisticated algorithms with remarkably little energy.

Electronic systems in cars operate stereo systems and displays; they also control fuel
injection systems, adjust suspensions to varying terrain, and perform the control
functions required for anti-lock braking (ABS) systems.
37

Digital electronics compress and decompress video, even at high definition data rates,

on-the-fly in consumer electronics.

Low-cost terminals for Web browsing still require sophisticated electronics, despite

their dedicated function.

Personal computers and workstations provide word-processing, financial analysis, and
games. Computers include both central processing units (CPUs) and special-purpose
hardware for disk access, faster screen display, etc.

5.5 ADVANTAGES OF VLSI

While we will concentrate on integrated circuits in this book, the properties of
integrated circuits what we can and cannot efficiently put in an integrated circuitlargely
determine the architecture of the entire system. Integrated circuits improve system
characteristics in several critical ways. ICs have three key advantages over digital circuits
built from discrete components:
Size. Integrated circuits are much smallerboth transistors and wires are shrunk to
micrometer sizes, compared to the millimetre or centimetre scales of discrete components.
Small size leads to advantages in speed and power consumption, since smaller components
have smaller parasitic resistances, capacitances, and inductances.

Speed. Signals can be switched between logic 0 and logic 1 much quicker within a chip
than they can between chips. Communication within a chip can occur hundreds of times
faster than communication between chips on a printed circuit board. The high speed of
circuits on-chip is due to their small sizesmaller components and wires have smaller
parasitic capacitances to slow down the signal
Power consumption. Logic operations within a chip also take much less power. Once
again, lower power consumption is largely due to the small size of circuits on the chip
smaller parasitic capacitances and resistances require less power to drive them.
Smaller physical size. Smallness is often an advantage in itselfconsiders portable
televisions or handheld cellular telephones.
Lower power consumption. Replacing a handful of standard parts with a single chip
reduces total power consumption. Reducing power consumption has a ripple effect on the rest
38

of the system: a smaller, cheaper power supply can be used; since less power consumption
means less heat, a fan may no longer be necessary; a simpler cabinet with less shielding for
electromagnetic shielding may be feasible, too.
Reduced cost. Reducing the number of components, the power supply requirements,
cabinet costs, and so on, will inevitably reduce system cost. The ripple effect of integration is
such that the cost of a system built from custom ICs can be less, even though the individual
ICs cost more than the standard parts they replace. Understanding why integrated circuit
technology has such profound influence on the design of digital systems requires
understanding both the technology of IC manufacturing and the economics of ICs and digital
systems.

39

CHAPTER 6
SOFTWARE REQUIREMENT

Verification Tool
ModelSim 6.4c
Synthesis Tool
Xilinx ISE 9.1

6.1 MODELSIM
ModelSim SE - High Performance Simulation and Debug
ModelSim SE is our UNIX, Linux, and Windows-based simulation and debugs
environment, combining high performance with the most powerful and intuitive GUI in the
industry.
What's New in ModelSim SE?

Improved FSM debug options including control of basic information, transition table
and warning messages. Added support of FSM Multi-state transitions coverage (i.e.
coverage for all possible FSM state sequences).

Improved debugging with hyperlinked navigation between objects and their

declaration, and between visited source files.

The dataflow window can now compute and display all paths from one net to another.

Enhanced code coverage data management with fine grain control of information in
the source window.

Toggle coverage has been enhanced to support SystemVerilog types: structures,

packed unions, fixed-size multi-dimensional arrays and real.

Some IEEE VHDL 2008 features are supported including source code encryption.
Added support of new VPI types, including packed arrays of struct nets and variables.

6.1.1 MODELSIM SE FEATURES

40

Multi-language, high performance simulation engine

Verilog, VHDL, SystemVerilog Design

Code Coverage

SystemVerilog for Design

Integrated debug

JobSpy Regression Monitor

Mixed HDL simulation option

System C Option

Solaris and Linux 32 & 64-bit

Windows 32-bit

6.1.2 MODELSIM SE BENEFITS

High performance HDL simulation solution for FPGA & ASIC design teams

The best mixed-language environment and performance in the industry

Intuitive GUI for efficient interactive or post-simulation debug of RTL and gate-level
designs

Merging, ranking and reporting of code coverage for tracking verification progress

Sign-off support for popular ASIC libraries

All ModelSim products are 100% standards based. This means your investment is
protected, risk is lowered, reuse is enabled, and productivity is enhanced

Award-winning technical support

41

High-Performance, Scalable Simulation Environment

ModelSim provides seamless, scalable performance and capabilities. Through the use
of a single compiler and library system for all ModelSim configurations, employing the right
ModelSim configuration for project needs is as simple as pointing your environment to the
appropriate installation directory.
ModelSim also supports very fast time-tenet-simulation turnarounds while
maintaining high performance with its new black box use model, known as bbox. With bbox,
non-changing elements can be compiled and optimized once and reused when running a
modified version of the test bench. B box delivers dramatic throughput improvements of up
to 3X when running a large suite of test cases.
Easy-to-Use Simulation Environment
An intelligently engineered graphical user interface (GUI) efficiently displays design
data for analysis and debug. The default configuration of windows and information is
designed to meet the needs of most users. However, the flexibility of the ModelSim SE GUI
allows users to easily customize it to their preferences. The result is a feature-rich GUI that is
easy to use and quickly mastered.
A message viewer enables simulation messages to be logged to the ModelSim results
file in addition to the standard transcript file. The GUIs organizational and filtering
capabilities allow design and simulation information to be quickly reduced to focus on areas
of interest, such as possible causes of design bugs.
ModelSim SE allows many debug and analysis capabilities to be employed postsimulation on saved results, as well as during live simulation runs. For example, the coverage
viewer analyzes and annotates source code with code coverage results, including FSM state
and transition, statement, expression, branch, and toggle coverage. Signal values can be
annotated in the source window and viewed in the waveform viewer. Race conditions, delta,
and event activity can be analyzed in the list and wave windows. User-defined enumeration
values can be easily defined for quicker understanding of simulation results. For improved
debug productivity, ModelSim also has graphical and textual dataflow capabilities. The
memory window identifies memories in the design and accommodates flexible viewing and
modification of the memory contents. Powerful search, fill, load, and save functionalities are
42

supported. The memory window allows memories to be pre-loaded with specific or randomly
generated values, saving the time-consuming step of initializing sections of the simulation
merely to load memories. All functions are available via the command line, so they can be
used in scripting.
Advanced Code Coverage
The ModelSim advanced code coverage capabilities deliver high performance with
ease of use. Most simulation optimizations remain enabled with code coverage. Code
coverage metrics can be reported by-instance or by-design unit, providing flexibility in
managing coverage data. All coverage information is now stored in the Unified Coverage
Data Base (UCDB), which is used to collect and manage all coverage information in one
highly efficient database. Coverage utilities that analyze code coverage data, such as merging
and test ranking, are available.
The coverage types supported include:

Statement coverage: number of statements executed during a run

Branch coverage: expressions and case statements that affect the control flow of the
HDL execution

Condition coverage: breaks down the condition on a branch into elements that make
the result true or false

Expression coverage: the same as condition coverage, but covers concurrent signal
assignments instead of branch decisions

Focused expression coverage: presents expression coverage data in a manner that

accounts for each independent input to the expression in determining coverage results

Enhanced toggle coverage: in default mode, counts low-to-high and high-to-low

transitions; in extended mode, counts transitions to and from X

Finite State Machine coverage: state and state transition coverage

43

6.2 SYNTHESIS TOOL:

6.2.1 XILINX ISE
For two-and-a-half decades, Xilinx has been at the forefront of the programmable
logic revolution, with the invention and continued migration of FPGA platform technology.
During that time, the role of the FPGA has evolved from a vehicle for prototyping and gluelogic to a highly flexible alternative to ASICs and ASSPs for a host of applications and
markets. Today, Xilinx FPGAs have become strategically essential to world-class system
companies that are hoping to survive and compete in these times of extreme global economic
instability, turning what was once the programmable revolution into the programmable
imperative for both Xilinx and our customers.
Programmable Imperative
When viewed from the customer's perspective, the programmable imperative is the
necessity to do more with less, to remove risk wherever possible, and to differentiate in order
to survive. In essence, it is the quest to simultaneously satisfy the conflicting demands created
by ever-evolving product requirements (i.e., cost, power, performance, and density) and
mounting business challenges (i.e., shrinking market windows, fickle market demands,
capped engineering budgets, escalating ASIC and ASSP non-recurring engineering costs,
spiraling complexity, and increased risk). To Xilinx, the programmable imperative represents
a two-fold commitment. The first is to continue developing programmable silicon innovations
at every process node that deliver industry-leading value for every key figure of merit against
which FPGAs are measured: price, power, performance, density, features, and
programmability. The second commitment is to provide customers with simpler, smarter, and
more strategically viable design platforms for the creation of world-class FPGA-based
solutions in a wide variety of industrieswhat Xilinx calls targeted design platforms.
Base Platform
The base platform is both the delivery vehicle for all new silicon offerings from
Xilinx and the foundation upon which all Xilinx targeted design platforms are built. As such,
it is the most fundamental platform used to develop and run customer-specific software
applications and hardware designs as production system solutions. Released at launch, the
44

base platform comprises a robust set of well-integrated, tested, and targeted elements that
enable customers to immediately start a design. These elements include:
FPGA silicon
ISE Design Suite design environment
Third-party synthesis, simulation, and signal integrity tools
Reference designs common to many applications, such as memory interface and
configuration designs.
Development boards that run the reference designs
A host of widely used IP, such as Gig E, Ethernet, memory controllers, and PCIe.
Domain-Specific Platform
The next layer in the targeted design platform hierarchy is the domain-specific
platform. Released from three to six months after the base platform, each domain specific
platform targets one of the three primary Xilinx FPGA user profiles (domains):the embedded
processing developer, the digital signal processing (DSP) developer, or the logic/connectivity
developer. This is where the real power and intent of the targeted design platform begins to
emerge. Domain-specific platforms augment the base platform with a predictable, reliable,
and intelligently targeted set of integrated technologies, including:
Higher-level design methodologies and tools
Domain-specific embedded, DSP, and connectivity IP
Domain-specific development hardware and daughter cards
Reference designs optimized for embedded processing, connectivity, and DSP
Operating systems (required for embedded processing) and software
Every element in these platforms is tested, targeted, and supported by Xilinx and/or
our ecosystem partners. Starting a design with the appropriate domain-specific platform can
cut weeks, if not months, off of the user's development time.
Market-Specific Platform
45

A market-specific platform is an integrated combination of technologies that enables

software or hardware developers to quickly build and then run their specific application or
solution. Built for use in specific markets such as Automotive, Consumer, Mil/Aero,
Communications, ISM, market-specific platforms integrate both the base and domain-specific
platforms and provide higher level elements that can be leveraged by customer-specific
software and hardware designs. The market-specific platform can rely more heavily on thirdparty targeted IP than the base or domain-specific platforms. The market-specific platform
includes: the base and domain-specific platforms, reference designs, and boards (or daughter
cards) to run reference designs that are optimized for a particular market (e.g., lane departure
early-warning systems, analytics, and display processing).Xilinx will begin releasing marketspecific platforms three to six months after the domain-specific platforms, augmenting the
domain-specific platforms with reference designs, IP, and software aimed at key growth
markets. Initially, Xilinx will target markets such as Communications, Automotive, Video,
and Displays with platform elements that abstract away the more mundane portions of the
design, thereby further reducing the customer's development effort so they can focus their
attention on creating differentiated value in their end solution. This systematic platform
development and release strategy provides the framework for the consistent and efficient
fulfilment of the programmable imperativeboth by Xilinx and by its customers.
Platform Enablers
Xilinx has instituted a number of changes and enhancements that have contributed
substantially to the feasibility and viability of the targeted design platform. These platformenabling changes cover six primary areas:
Design environment enhancements
Socket able IP creation
New targeted reference designs
Scalable unified board and kit strategy
Ecosystem expansion
Design services supporting the targeted design platform approach
Design Environment Enhancements
46

With the breadth of advances and capabilities that the Virtex-6 and Spartan-6
programmable devices deliver coupled with the access provided by the associated targeted
design platforms, it is no longer feasible for one design flow or environment to fit every
designer's needs. System designers, algorithm designers, SW coders, and logic designers each
represent a different user-profile, with unique requirements for a design methodology and
associated design environment. Instead of addressing the problem in terms of individual fixed
tools, Xilinx targets the required or preferred methodology for each user, to address their
specific needs with the appropriate design flow. At this level, the design language changes
from HDL (VHDL/Verilog) to C, C++, MATLAB software, and other higher level
languages which are more widely used by these designers, and the design abstraction moves
up from the block or component to the system level. The result is a methodology and
complete design flow tailored to each user profile that provides design creation, design
implementation, and design verification. Indicative of the complexity of the problem, to fully
understand the user profile of a logic designer, one must consider the various levels of
expertise represented by this demographic. The most basic category in this profile is the
push-button user who wants to complete a design with minimum work or knowledge.

The push-button user just needs good-enough results. Contrastingly, more advanced
users want some level of interactive capabilities to squeeze more value into their design, and
the power user (the expert) wants full control over a vast array of variables. Add the
traditional ASIC designers, tasked with migrating their designs to an FPGA (a growing trend,
given the intolerable costs and risks posed by ASIC development these days), and clearly the
imperative facing Xilinx is to offer targeted flows and tools that support each user's
requirements and capabilities, on their terms. The most recent release of the ISE Design Suite
includes numerous changes that fulfil requirements specifically pertinent to the targeted
design platform. The new release features a complete tool chain for each top-level user
profile (the domain-specific personas: the embedded, DSP, and logic/connectivity designers),
including specific accommodations for everyone from the push-button user to the ASIC
designer.
The tighter integration of embedded and DSP flows enables more seamless integration
of designs that contain embedded, DSP, IP, and user blocks in one system. To further enhance
productivity and help customers better manage the complexity of their designs, the new ISE
47

Design Suite enables designers to target area, performance, or power by simply selecting a
design goal in the setup. The tools then apply specific optimizations to help meet the design
goal. In addition, the ISE Design Suite boasts substantially faster place-and-route and
simulation run times, providing users with 2X faster compile times. Finally, Xilinx has
adopted the FLEXnet Licensing strategy that provides a floating license to track and monitor
usage.
6.3 XILINX ISE DESIGN TOOLS
Xilinx ISE is the design tool provided by Xilinx. Xilinx would be virtually identical
for our purposes.
There are four fundamental steps in all digital logic design. These consist of:
1. Design The schematic or code that describes the circuit.
2. Synthesis The intermediate conversion of human readable circuit description to
FPGA code (EDIF) format. It involves syntax checking and combining of all the
separate design files into a single file.
3. Place & Route Where the layout of the circuit is finalized. This is the
translation of the EDIF into logic gates on the FPGA.
4. Program The FPGA is updated to reflect the design through the use of
programming (.bit) files. Test bench simulation is in the second step. As its
name implies, it is used for testing the design by simulating the result of
driving the inputs and observing the outputs to verify your design. ISE has the
capability to do a variety of different design methodologies including:
Schematic Capture, Finite State Machine and Hardware Descriptive Language
(VHDL or Verilog).

6.4 SIMULATION IMPLEMENTATION

Verilog HDL is a Hardware Description Language (HDL). A Hardware Description
Language is a language used to describe a digital system, for example, a computer or a
component of a computer. One may describe a digital system at several levels. For example,
an HDL might describe the layout of the wires, resistors and transistors on an Integrated
Circuit (IC) chip, i.e., the switch level. Or, it might describe the logical gates and flip flops in
a digital system, i. e., the gate level. An even higher level describes the registers and the
transfers of vectors of information between registers. This is called the Register Transfer
48

Level (RTL). Verilog supports all of these levels. However, this handout focuses on only the
portions of Verilog which support the RTL level.
Verilog is one of the two major Hardware Description Languages (HDL) used by
hardware designers in industry and academia. VHDL is the other one. The industry is
currently split on which is better. Many feel that Verilog is easier to learn and use than
VHDL. As one hardware designer puts it, I hope the competition uses VHDL. VHDL was
made an IEEE Standard in 1987, and Verilog in 1995. Verilog is very C-like and liked by
electrical and computer engineers as most learn the C language in college. VHDL is very
most engineers have no experience. Verilog was introduced in 1985 by Gateway Design
System Corporation, now a part of Cadence Design Systems, Inc.s Systems Division. Until
May, 1990, with the formation of Open Verilog International (OVI), Verilog HDL was a
proprietary language of Cadence. Cadence was motivated to open the language to the Public
Domain with the expectation that the market for Verilog HDL-related software products
would grow more rapidly with broader acceptance of the language. Cadence realized that
Verilog HDL users wanted other software and service companies to embrace the language
and develop Verilog-supported design tools.

CHAPTER7
RESULTS
SIMULATION RESULT

49

OBSERVATIONS: If we give the data as 1000 we have to retain that data in flip flop in
standby mode. Whenever the circuit goes to active mode from standby mode we have to get that data.
So, the output must have 1000. By simulation we can see that result.

CHAPTER 8
CONCLUSION
The proposed MULTI BIT RFF achieves ultralow-standby power by adopting a power
management scheme to use VDD, IO for data retention and to turn off the voltage regulator in

50

the standby mode. In addition, the retention latch in the proposed RFF is composed of a
stacked structure with thick-oxide transistors to reduce the standby leakage current.

REFERENCES
[1] W. Kluge et al., A fully integrated 2.4-GHz IEEE 802.15.4-complianttransceiver for
Zigbee applications, IEEE J. Solid-State Circuits,vol. 41, no. 12, pp. 27672775, Dec. 2006.
[2] J.-S. Lee, Y.-W. Su and C.-C. Shen, A comparative study of wireless protocols:
Bluetooth, UWB, Zigbee, and Wi-Fi, IEEE Wireless Commun., vol. 14, no. 4, pp. 7078,
Nov. 2007.
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[3] J. Hu, W. Liu, W. Khalil, and M. Ismail, Increasing sleep-mode efficiency by reducing
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[4] Y.-I. Kwon, S.-G. Park, T.-J. Park, K.-S. Cho and H.-Y. Lee, An ultralow-power CMOS
transceiver using various low-power techniques for
LR-WPAN applications, IEEE Trans. Circuits Syst. I, vol. 59, no. 2,pp. 324336, Feb. 2012.
[5] M. Albano and S. Chessa, Data centric storage in Zigbee wireless sensor networks, in
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[6] S. Shigemitsu, S. Mutoh, Y. Matsuya, Y. Tanabe, and J. Yamada,A 1-V high-speed
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[7] L. T. Clark, M. Kabir, and J. E. Knudsen, A low standby power flip-flop with reduced
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[8] V. Yuban and S. V. Kosonocky, Low power integrated scan-retention mechanism, in
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[9]H.Mahmoodi-Meimand and K. Roy, Data-retention flip-flops for power-down
applications, in Proc. ISCAS, vol.2. May. 2004 pp. 67780.
[10] J. Seomun and Y. Shin, Design and optimization power-gated circuits with autonomous
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[12] P. Meinerzhagen, O. Anderson, B. Mohammadi, Y. Sherazi, A. Burg,and J.N.Rodrigues,
A 500 fW/bit 14 fJ/bit-access 4kb standard-cell based sub-VT memory in 65nm CMOS, in
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[13] N. B. Kothari, T. S. B. Sudarshan, S. Gurunarayanan, and R. A. Chandrasekhar, SoC
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[14] P. Zhao et al., Low-power clocked-pseudo-nMOS flip-flop for level conversion in dual
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APPENDIX
SINGLE BIT PROPOSED RFF
module SD_Topmodule(Data,Cntrl,S1,S2,S3,S4,S5,Out,Outb);
input Data,Cntrl;
53

inout S1,S2,S3,S4,S5;
output Out,Outb;
SD_TX_Gate M1(
.A(Cntrl),
.IN(Data),
.OUT(S1)
);
SD_TX_Gate M2(

.A(Cntrl),
.IN(S3),
.OUT(S1)
);

SD_NotGate M3(
.A(S1),
.B(S2)
);
SD_NotGate M4(
.A(S2),
.B(S3)
);
SD_AndGate M5(

.A(S2),
.B(S3),
.C(S4)
);

SD_AndGate M6(

.A(S2),
.B(S3),
.C(S5)
);

SD_NotGate M7(
.A(S5),
.B(S4)
);
SD_NotGate M8(
.A(S4),
.B(S5)
);
SD_NotGate M9(
.A(S4),
.B(Outb)
54

);
SD_NotGate M10(
.A(S5),
.B(Out)
);
endmodule

MULTI BIT PROPOSED RFF

module SD_ProposedRFF(Data,Cntrl,S1,S2,S3,S4,S5,S6,Out,Outb);
input [3:0]Data,Cntrl;
inout [3:0]S1,S2,S3,S4,S5,S6;
output [3:0]Out,Outb;
wire [3:0]S1,S2,S3,S4,S5,S6;
SD_TX_Gate M1(
.A(Cntrl),
.IN(Data),
.OUT(S1)
);
SD_TX_Gate M2(

.A(Cntrl),
.IN(S3),
.OUT(S6)
);

SD_NotGate M3(
.A(S1),
.B(S2)
);
SD_NotGate M4(
.A(S2),
.B(S3)
);
SD_AndGate M5(

.A(S2),
.B(S3),
.C(S4)
);

SD_NotGate M9(
.A(S4),
55

.B(Outb)
);
SD_NotGate M10(
.A(S5),
.B(Out)
);
endmodule

56