Experience:

FPGA, Embedded, Control System

Research Area:
Digital Design
Embedded Systems
Image Processing

Lecture # 1

FPGA-Based System Design 3 + 1

Prerequisite:
EE-230 Digital Logic Design
Objective:
Teach the design of digital electronic
circuits with field-programmable gate arrays.

FPGA-Based System Design

Course

Outline:

Introduction to digital design and FPGA, FPGA

architectures, SRAM -based FPGAs, permanently-programmed
FPGAs, circuit FPGA-based system design, logic design
process, combinational network delay, power and energy
optimization, arithmetic logic elements, logic implementation
using FPGAs, FSM design, ASM design. Physical design ,
synthesis process. Sequential design using FPGAs, sequential
machine design process, sequential design style.

FPGA-Based System Design

Lab Outline:
Introduction to Verilog HDL, gate-level
modeling, data flow modeling, behavioral
modeling, design, simulation, synthesis and
fitting of combinational circuits, design and
implementation of an FSM and memory.

Recommended Books:

Recommended Books:

Digital System
Digital system is black box which process
some digital data to generate digital
output.

Digital
Input

System

Digital
Output

Semi Custom and Full Custom

FPGA-Based System Design

Instead of programming a chip by telling

it what to do, FPGAs allow you to tell a
chip what to be.

Field Programmable Gate Array

(FPGA)

What is FPGA?

Programmable semiconductor devices

Matrix of Configurable Logic Blocks (CLBs)

Programmable interconnects.

Can be programmed to the desired application or

functionality requirements.

ASICs built for the particular design

One-Time Programmable (OTP) FPGAs are available,

SRAM-based can be reprogrammed as the design evolve

Field Programmable Gate Array

(FPGA)

What is FPGA?

Allow designers to change their designs very late in

the design cycle

Even after the end product has been manufactured

and deployed in the field.

Xilinx FPGAs allow for field upgrades remotely

Eliminating the costs associated with re-designing

FPGA

FPGA vs ASIC

ASIC Design
Advantage

Benefit

Full custom capability

For design since device is

manufactured to design specs

Lower unit costs

For very high volume designs

Smaller form factor

Since device is manufactured to

design specs

FPGA vs ASIC
FPGA Design
Advantage

Benefit

Faster time-to-market

No layout, masks or other

manufacturing steps are needed

No-recurring expenses (NRE)

Costs typically associated with an

ASIC design

Simpler design cycle

Due to software that handles

much of the routing, placement,
and timing

More predictable project cycle

Due to elimination of potential

re-spins, wafer capacities, etc.

Field reprogramability

A new bitstream can be uploaded

remotely

FPGA Applications

Aerospace & Defense - Radiation-tolerant FPGAs, waveform

generation

ASIC Prototyping - Accurate SoC

Audio - Lower overall non-recurring engineering costs (NRE) for a

wide range of audio

Automotive - Driver assistance systems, comfort, convenience

Consumer Electronics - Converged handsets, digital flat panel

displays, information appliances, home networking

Data Center - Designed for high-bandwidth, low-latency servers,

networking

FPGA Applications

Industrial - Industrial imaging and surveillance, industrial

automation, and medical imaging equipment.

Medical - For diagnostic, monitoring, and therapy applications,

Security - Security applications, from access control to

surveillance and safety systems.

Video & Image Processing - Wide range of video and imaging

applications

Wired Communications - Reprogrammable Networking, Packet

Processing

Wireless Communications - RF, base band, connectivity, transport

and networking solutions for wireless equipment

FPGA Applications

FPGA Applications

FPGA Applications

FPGA Applications

Design Methodology

Synthesis
Converting HDL code into Hardware design
Realization and mapping of Hardware using
HDL.
Higher Level is ultimately translated to
transistor level or gate level.
Synthesis is process of converting HDL to
gatenet list.

Synthesis

Synthesis tool Steps

Post Synthesis Simulation

Purpose
If code functionally correct?

All four level Coding translated to GNL.

GNL:

i) Gates & wires from Library cells

ii) Not include Verilog primitive

Results of Post synthesis are compared with those in

simulation

Why FPGA

Why FPGA