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Mathematical Model
Ideal Diode Model
Constant Voltage Drop (CVD) Model
Complete Diode Model
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(1)
I D I S [e
VD
)
VT
1]
(2)
Substitute (2) in (1) with IS = 10-13 A,VT = 0.025 V. (for Si diode @ room
temperature)
10 -9 [e 40VD 1] VD 10
(3)
Solve (3) for VD, then VD = 0.5742 V and ID = 9.426 10-4 A = 0.9426 mA
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Therefore, using ideal diode model under this diode circuit condition, we can
conclude that;
= 0 V, and =
= 0 A , and =
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Example 2: Use ideal diode model to analyze ID and VD from Figure 3.3.
Solution : Consider from 4 steps to analyze ID and VD in the diode circuit:
1. Use the ideal diode model for this circuit condition (from Figure 3.3)
(Figure 3.3)
2. Because the voltage source appears to be trying to forward bias the diode,
we assume that the diode is on or acts like a short circuit, see Figure 3.6.
3. Find ID: =
10 V
10 k
= 1 mA
4. The current ID > 0, which is consistent with the assumption that the diode
is on.
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Example 3: Use ideal diode model to analyze ID and VD of both diodes from
Figure 3.7.
Solution :
Use the ideal diode model
Make assumptions. Because we have 2 diodes in this circuit. Therefore we
can assume 4 conditions, as mentioned in Table 1.
Table 1: 4 possible diode conditions for 2 diodes
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First try : Both diodes are on. Under this assumption, the diode circuit from
Figure 3.7 becomes
The result ID1 < 0 is inconsistent with our assumption that D 1 is on. Our
assumption must be incorrect.
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Second try : D1 is off and D2 is on. Under this assumption, the diode circuit from
Figure 3.7 becomes
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Since ID2 > 0 (D2 is on) and VD1 < 0 (D1 is off or reverse biased), they are
consistent with our assumptions.
We can conclude that
ID1 = 0 A , VD1 = 1.67 V, ID2 = 1.67 mA, VD2 = 0 V
Example 4: Determine ID1, ID2 , VD1 and VD2, using ideal diode model.
Solution :
Keep in mind that by using ideal diode model,
For on condition : VD = 0 V and ID > 0 A
For off condition : VD < 0 V and ID = 0 A
First try : Assume diode 1 is on, diode 2 is off. Under this assumption, the diode
circuit from Figure 3.11 becomes
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Second try : Assume both diodes are off. Under this assumption, the diode circuit
from Figure 3.11 becomes
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The characteristic curve for the practical diode model is shown in Figure
3.15. Since the barrier potential is included, the diode is assumed to have a voltage
across it when forward-biased, as indicated by the portion of the curve to the right
of the origin.
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Figure 3.15 V-I characteristic curve (blue) of CVD model for Si diode. [5]
Therefore, using CVD model under this diode circuit condition, we can conclude
that;
For forward bias:
= 0.7 V ( for Si diode) and = 0.3 V ( for Ge diode)
Here, applying Kirchoffs voltage to find IF:
= 0
And
Therefore,
= ( )/
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(Figure 3.3)
2. Because the voltage source appears to be trying to forward bias the diode,
we assume that the diode is on, and we can replace Si diode by V F = 0.7 V,
see Figure 3.16.
3. Find ID:
4. The current ID > 0, which is consistent with the assumption that the
diode is on.
*** Here, comparison of Diode Circuit Analysis (from Example 1, 2, 5) Results
Example 6: Use CVD model to analyze ID1, ID2, ID3, VD1, VD2, and VD3 .
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Example 7: Using CVD model, calculate VO, ID1, ID2, and I for the following
conditions:
(a) V1 = V2 = 0 V
(b) V1 = 20 V, V2 = 0 V
Solution :
(a) When V1 = V2 = 0 V, we assume D1 = on, D2 = on, see Figure 3.20.
10 5I 0.7 5* I / 2
I 1.24 A
I D1 I D2 I / 2 0.62 A
V0 0.7 5* I D1 (or I D2 ) 3.8 V
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I D1 = 0 A______#
I = I D2
10 = 5I + 0.7 + 5I D2
I = 9.3 A = I D2 ______#
V0 = 0.7 + 5I D2
= 0.7 + 5 (9.3)
= 5.35 V______#
Homework 3
1. Using ideal diode model, calculate the voltage across each diode and the current
flowing through each diode in Figure 3.22 (a), (b) and (c).
2. Using ideal diode model , calculate ID1, ID2 in the circuit for each case.
(1) VIN = 0 V
(2) VIN = 10 V
(3) VIN = 10 V
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3. Assume D1, D2 and D3 are Si diodes. Find ID1, ID2, ID3, VD1, VD2 and VD3 in the
circuit of Figure 3.24, using the ideal diode model.
4. Assume D1 and D2 are Si diodes. Find ID1, ID2, VD1, VD2 and VO in the circuit of
Figure 3.25, using the ideal diode model.
ID1
2 k
-5V
+ VD1
+ VD2
0V
VO
ID2
1 k
1 k
-5V
Figure 3.25 For problem 4
5. Assume D1 and D2 are Si diodes. Find ID1, ID2, VD1, VD2 and IO in the circuit of
Figure 3.26, using the ideal diode model.
6. Using CVD model, assume D1, D2, D3 are Si diodes. Calculate VOUT and the
currents ID1, ID2, ID3 and I for the following input conditions:
(a) V1 = V2 = 0 V
(b) V1 = 5 V, V2 = 2 V
+ 10 V
I
0.55 K
D1
10 K
V1
ID1
ID2
V2
0.55 K
K
D2
VOUT
ID3
D3
+5V
Figure 3.27 For problem 6
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7. Let Von (or VF) = 0.6 V. Determine ID and VD in the circuit for each condition,
using the CVD model.
(a) V1 = 15 V, V2 = 10 V
(b) V1 = 10 V, V2 = 15 V
+ 10 V
I
ID1
ID2
D1
D2
+
VOUT
5 K
+5V
9. Assume D1, D2 and D3 are Si diodes. Find ID1, ID2, ID3, VD1, VD2 and VD3 in the
circuit of Figure 3.30, using the CVD model.
+ 10 V
+
VD2
_
5A
ID2
10
VD1 +
5
ID1
10
_
VD3
ID3
+5V
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10. Assume the diode shown here is Ge diode. Find I D, VD and IX in the circuit of
Figure 3.31, using the CVD model.
Power Transformers
Basically, a transformer consists of at least two windings, or coils,
wrapped around a laminated iron core, see Figure 3.34. A transformer may have
multiple secondaries, and one or more of these windings may be center-tapped.
Here, the symbols of a normal transformer and a center-tapped transformer are
shown in Figure 3.35 (a) and (b), respectively.
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(a)
(b)
Here, the dots are used to indicate the phase of the transformer. When the output
waveform is in phase with the input waveform, we can use Figure 3.36 (a) to
shows that condition. However, Figure 3.36 (b) is used when the output waveform
in 180 out of phase with the input waveform. Moreover, Figure 3.37 shows the
how to use 2 dots to indicate the phase of the output waveform for the centertapped transformer.
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(a) In Phase
Rectifiers
A rectifier circuit converts an ac voltage to a pulsating DC voltage. Three
types of rectifier circuits are discussed here.
(1) Half-wave rectifier
(2) Center-tapped full-wave rectifiers
(3) Bridge full-wave rectifiers
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VO(p)
Here, The average value of the half-wave rectified output voltage is the
value you would measure on a dc voltmeter. Mathematically, it is determined by
()
0.7
Figure 3.40 PIV occurs at the peak of each negative half-cycle. [6]
t (s)
0V
(b)
V(t)
20 V
10 V
0V
t (s)
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(c)
V(t)
5V
0V
t (s)
15 V
Solution:
(a) Vav =
Vout(p)
(20-10)
V
10
(5-(-15))
10
15
20
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Example 9: Draw the output voltages of each rectifier for the indicated input
voltages, as shown in Figure 3.42. The 1N4001 and 1N4003 are specific rectifier
diodes.
(a)
(b)
Solution :
The peak output voltage for circuit (a) is
() = () 0.7 V = (5 0.7) V = 4.3 V
The peak output voltage for circuit (b) is
() = () 0.7 V = (100 0.7) V = 99.3 V
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Example 10: Draw the output voltage waveform for the circuit and include the
voltage.
Si diode
5V
+
0V
Vin
Vin
R = 1 k
Vout
5 V
Figure 3.44 For Example 10
Solution :
For negative cycle:
V(t)
Vin
5V
t (s)
0V
4.3 V
5 V
Vout
Figure 3.45 Vout and Vin waveform
Example 11: Consider this circuit, assuming the practical diode model.
(a) Determine the output waveform of the voltage across RL.
(b) Determine the average output voltage across RL.
(c) Determine the average output current through RL.
Solution : (a)
212.13 V( p )
Vin (sec)
1
* 212.13 V( p )
4
53.03 V( p )
()
34.9
11.11 V
10
= 11.11 V
= 1.111 A
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Figure 3.52 Basic operation of a center-tapped full-wave rectifier. Note that the
current through the load resistor is in the same direction during the entire input
cycle, so the output voltage always has the same polarity. [5]
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The comparison between input and output waveform of the center-tapped fullwave rectifier using CVD diode model is shown in Figure 3.53.
The ripple frequency fr(FW) is doubled from the line frequency. Therefore,
fr (FW) = 2fline
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Since each diode conducts only each half of the cycles, the average current through
each diode is
When the total secondary voltage Vsec has the polarity shown, the
maximum anode voltage of D1 is +Vp(sec)/2 and the maximum anode voltage of D2
is Vp(sec)/2. Since D1 is assumed to be forward-biased, its cathode is at the same
voltage as its anode minus the diode drop; this is also the voltage on the cathode of
D2.
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Solution:
(a) The transformer turns ratio n = 0.5. The total peak secondary voltage is
25 V
This is a 25 V peak across each half of the secondary with respect to the
ground.
Vout ( peak )
Vp (sec)
Von
2
25 0.7 24.3 V
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Example 13: Consider this circuit, assuming the practical diode model.
(a) Determine the output waveform of the voltage across RL.
(b) Determine the average output voltage across RL.
(c) Determine the average output current through RL.
Solution:
(a) For + cycle, D1 = on, D2 = off.
Vs 0.7 V 10 V Vout 0
Vout Vs 10 0.7 V
Vout ( p ) Vp 10 V 0.7 V
Here,
30.51v
20.51v
Vav1
10v
Vav
Vout(p)=30.51
v
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(b)
(c)
Figure 3.61 Bridge operation during a positive half-cycle of the primary and
secondary voltages. [5]
fr (FW) = 2fline
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The comparison between input and output waveform of the bridge full-wave
rectifier using CVD diode model is shown in Figure 3.62.
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Example 14: Determine the peak output voltage for the bridge rectifier in this
figure. Assuming the practical model, what PIV rating is required for the diode?
The transformer is specified to have a 12 Vrms secondary voltage for the standard
110 V across the primary.
Solution :
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Homework 4
1. Draw the output voltage of each rectifier for the indicated input voltages, as
shown in this figure 3.64.
2. Determine the peak value of the output voltage if the turn ratio is 0.5.
3. Consider the circuit in Figure 3.66, assuming the practical diode model.
(a) Determine the output waveform of the voltage across RL.
(b) Determine the average output voltage across RL.
(c) Determine the average output current through RL.
4. Consider the circuit in Figure 3.67, assuming the practical diode model.
(a) Determine the output waveform of the voltage across RL.
(b) Determine the average output voltage across RL.
(c) Determine the average output current through RL.
6. Consider the circuit in Figure 3.69, assuming the practical diode model.
(a) Determine the average output voltage across RL.
(b) Sketch the output voltage waveform across RL.
(c) What is the PIV for each diode?
15 : 2
120 Vrms
60 Hz
+
RL = 10
Vout
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7. (a) Consider the circuit in Figure 3.70 (a), assuming the practical diode model.
Sketch the output voltage waveform across RL. Assume Von = 0.7 V for each diode.
(b) Consider the circuit in Figure 3.70 (b), assuming the practical diode model.
Sketch the output voltage waveform across RL. Assume Von = 0.7 V for each diode.
120 Vrms
45 turns
10
30 turns
45 turns
RL = 15
VOUT
(a)
120 Vrms
10
60 turns
30 turns
30 turns
RL = 15
VOUT
(b)
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8. (a) Consider the circuit in Figure 3.71(a), assuming the CVD model. Sketch the
output voltage waveform across 10 resistor, and then find the average voltage
(Vav). Assume Von = 0.7 V for each diode.
(b) Consider the circuit in Figure 3.71(b), assuming the CVD model. Sketch the
output voltage waveform across 10 resistor, and then find the average voltage
(Vav). Assume Von = 0.7 V for each diode.
(a)
(b)
Figure 3.71 For problem 8.
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9. Consider the Center-tapped full wave rectifier circuits in Figure 3.72 (a) and that
in Figure 3.72 (b), then sketch the output waveform of the voltage across R L (VOUT)
in both circuits.
5 :
1
Si Diode
100 Vrms
+
Si Diode
1 k
VOUT
(a)
5 :
2 k
15
Si Diode
100 Vrms
Si Diode
+
1 k
VOUT
(b)
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10. Determine the peak output voltage for the bridge rectifier in this figure.
Assuming the practical model, what PIV rating is required for the diode? Assume
that the primary voltage of the transformer is 200 VP-P and the transformer turns
ratio n = 0.25.
11. Using practical diode model, find the output voltage across R L, PIV of each
diode and plot the output waveform of output voltage across RL.
10 : 1
1
150 Vrms
60 Hz
+
RL = 10
Vout
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12. (a) Sketch the output voltage of the bridge rectifier in Figure 3.75. Notice that
all the Si diodes are reversed from the normal full-wave bridge rectifier circuits.
(b) Determine the average output voltage (Vav) across RL.
4:1
120 V(p-p)
RL
+
Vout
-
Ge
60 turns
5V
15 turns
Ge
200 Vp-p
60 Hz
Si
Si
+
100
VOUT
During the first quarter of the next cycle, as illustrated in Figure 3.78 (c),
the diode will again become forward-biased when the input voltage exceeds the
capacitor voltage by 0.7 V.
Ripple Voltage:
As you have seen, the capacitor quickly charges at the beginning of a
cycle and slowly discharges through RL after the positive peak of the input voltage
(when the diode is reverse-biased). The variation in the capacitor voltage due to the
charging and discharging is called the ripple voltage. Generally, ripple is
undesirable; thus, the smaller the ripple, the better the filtering action, as illustrated
in Figure 3.79.
Figure 3.80 The period of a full-wave rectified voltage is half that of a half-wave
rectified voltage. The output frequency of a full-wave rectifier is twice that of
a half-wave rectifier. [5]
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Figure 3.81 Comparison of ripple voltages for half-wave and full-wave rectified
voltages with the same filter capacitor and load and derived from the same
sinusoidal input voltage. [5]
Ripple Factor:
The ripple factor (r) is an indication of the effectiveness of the filter and
is defined as
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From Figure 3.82, Vr(pp) is the peak-to-peak ripple voltage and VDC is the
dc (average) value of the filters output voltage. The lower the ripple factor, the
better the filter. The ripple factor can be lowered by increasing the value of the
filter capacitor or increasing the load resistance.
Example 15: Determine the ripple factor for the filtered bridge rectifier with a
load as indicated in Figure 3.83.
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Solution :
or
Example 16:
Consider the filtered half-wave rectifier in Figure 3.84. Assume fline = 60 Hz and
Von = 0.7 V. Given the following conditions:
(1) VDC = 15 V when RL = 1 k
(2) VDC = 20 V when RL = 1.5 k
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Determine
(a) Filter capacity (C)
(b) Maximum ripple voltage (Vp(rect) or VM)
(c) Turn ratio (N1 : N2)
(b)
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When the output terminals of the zener regulator are open (R L= ), the
load current is zero and all of the current is through the zener. When a load resistor
RL is connected, part of the total current is through the zener and part through R L.
As RL is decreased, the load current IL increases and IZ decreases. The zener diode
continues to regulate the voltage until I Z reaches its minimum value, IZK. At this
point the load current is maximum. The total current trough R remains essentially
constant.
Example 17: Determine the minimum and the maximum load currents for which
the zener diode will maintain regulation. What is the minimum value of R L that can
be used? VZ = 12 V, IZK = 1 mA, and IZM = 50 mA. Assume ZZ = 0 and VZ
remains a constant 12 V over the range of current values, for simplicity.
Solution :
Using KCL, we get
Since IZ(max) < IZM, 0 A is an acceptable minimum value of IL because the Zener can
handle all of the 25.5 mA
IL(min) = 0 A
The maximum value of IL occurs when IZ is minimum (IZ = IZK), so solve for
IL(max):
*** Notice that if RL is less than 490 , RL will make more current away from
the zener diode and IZ will be reduced below IZK. This will cause the zener to lose
regulation.***
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Example 18: Determine the values of VDC, Vr(out), and IL for the power supply
shown in Figure 3.97.
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Solution :
The dc output voltage (VDC) will equal the value of VZ, by formula:
= = 30 V
And
Here,
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Example 19:
(a) Determine the values of VDC, Vr(out) , and IL for the power supply
shown in Figure 3.98.
(b) Can we use the zener diode in this circuit as the voltage regulator or
not? Why?
Solution :
(a)
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(b)
IRS=IZ + IL
Here
*** As IZ < IZM (195.5 mA < 300 mA), we can use this zener diode as the
voltage regulator ***
Homework 5
1. Consider the filtered full-wave rectifier. Assume fline = 60 Hz and Von = 0.7 V.
Given the following conditions:
(1) VDC = 10 V when RL = 500
(2) VDC = 12 V when RL = 1500
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Determine
(a) Filter capacity (C)
(b) Maximum ripple voltage (Vp(rect) or VM)
2. Calculate the dc output voltage (VDC), dc output current (IDC) values and the
output ripple voltage (Vr(out)).
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3. Calculate the dc output voltage (VDC), dc output current (IDC) values and the
output ripple voltage (Vr(out)).
110 Vrms
fline = 60 Hz
+
2000 F
VDC
_
IL
RL
1 k
6. (a) Determine the values of VDC, Vr(out), and IL for the power supply shown in
Figure 3.103.
(b) Can we use the zener diode in this circuit as the voltage regulator or not?
Why?
Solution:
The diode is forward-biased and conducts when the input voltage goes
below 0.7 V. So, for the negative limiter, determine the peak output voltage
across RL by the following equation:
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Biased Limiters:
The level to which an AC voltage is limited can be adjusted by adding a
bias voltage, VBIAS, in series with the diode, as shown in Figure 3.108. The voltage
at point A must equal VBIAS + 0.7 V before the diode will become forward-biased
and conduct. Once the diode begins to conduct, the voltage at point A is limited to
VBIAS + 0.7 V so that all input voltage above this level is clipped off.
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To limit a voltage to a specified negative level, the diode and bias voltage
must be connected as in Figure 3.109. In this case, the voltage at point A must go
below VBIAS 0.7 V to forward-bias the diode and initiate limiting action as
shown.
Example 21: Figure 3.110 shows a circuit combining a positive limiter with a
negative limiter. Determine the output voltage waveform.
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Solution:
When the voltage at point A reaches +5.7 V, diode D1 conducts and limits
the waveform to +5.7 V. Diode D2 does not conduct until the voltage reaches
5.7 V. Therefore, positive voltages above + 5.7 V and negative voltages below
5.7 V are clipped off. The resulting output voltage waveform is
Homework 6
1. Draw the voltage waveform of VOUT and V10 in this circuit. Assume D1 and D2
are Si diode.
+ V10
+ 15 V
10
20
VIN
5V
+
VOUT
_
15 V
2. Sketch the output waveforms of VOUT1, VOUT2. And determine the minimum and
maximum voltage of both waveforms.
+ 20 V
VOUT1 _
D1, D2: Si diode
2 k
VIN
+
D1
+
_
3 k
_ OUT2
D2
- 20 V
3. Sketch the output waveforms of VOUT1, VOUT2. And determine the minimum and
maximum voltage of both waveforms.
+
+ 20 V
VOUT1 _
D1, D2: Si diode
2 k
VIN
+
_
D1
+
3 k
_ OUT2
D2
- 20 V
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4. Determine the output waveform for the circuit in Figure 3.115(a) for each input
voltage in (b), (c), and (d).
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5. Determine the RL voltage waveform for each circuit in Figure 3.116(a), (b) and
(c).
6. Draw the output voltage waveform for each circuit in Figure 3.117(a) and (b).
7. Sketch the output waveforms of VOUT 1, VOUT 2, and VOUT 3 in this circuit shown
in Figure 3.118. And also determine Vmax and Vmin of each voltage waveform.
Assuming CVD model, and D1 and D2 are Si diodes.
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