1 Introduction 8086

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EC 1402: MICROPROCESSORS
Module I
Introduction to microprocessors: Microcomputers and microprocessors, 8/ 16/ 32/ 64bit microprocessor families.
Internal architecture of Intel 8086 microprocessor: Block diagram, Registers, Internal

Bus Organization, Functional details of pins, Control signals, External Address / Data
bus multiplexing, De-multiplexing, Memory Address space and data organisation,
Memory segmentation and segment registers, IO Address space.
Basic 8086/8088 configuration, Minimum mode and maximum mode. Comparison of

8086 and 8088
16-bit Processors and Segmentation (1978)

the 8086 and 8088.
20-bit addressing, 1-Mbyte address space.
The Intel 286 Processor (1982)
24-bit addressing, 16 Mbytes address space.
The Intel386 Processor (1985)

32-bit addressing, 4-Gbytes address space.
The Intel486 Processor (1989)
Expanded instruction decode and execution units into five
pipelined stages.
The Intel Pentium Processor (1993)
added a second execution pipeline to achieve superscalar
performance.
Branch prediction has added.
The P6 Family of Processors (1995-1999)
Intel Pentium Pro processor

Intel Pentium II processor
Pentium II Xeon processor
Intel Celeron processor
Intel Pentium III processor
Pentium III Xeon processor
The Intel Pentium 4 Processor Family (2000-2005)

based on Intel NetBurst microarchitecture.
aim:- i)
to execute legacy IA-32 applications based on singleinstruction, multiple-data (SIMD) technology at high throughput
ii)
to operate at high clock rates and to scale to higher
performance and clock rates in the future
The Intel Xeon Processor (2001-2005)
introduced support for Hyper-Threading Technology
The Intel Pentium M Processor (2003-2005)

designed for extending battery life
The Intel Pentium Processor Extreme Edition (2005)

64-bit addressing, 1024-Gbytes address space.
Find out whats new ??

i3,i5,i7,. etc
Introduction to Intel 8086 microprocessor

Intel 8086 CPU Architecture
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Key Features:
Released by Intel in 1978

Produced from 1978 to 1990s
A 16-bit microprocessor chip.
Max. CPU clock rate :
5 MHz to 10 MHz
Instruction set: x86-16
Intel 8086 Microprocessor
Package: 40 pin DIP
The 8086 gave rise to
the x86 architecture of Intel's future processors.
Common manufacturer(s): Intel, AMD, NEC, Fujitsu, Harris
(Intersil), OKI, Siemens AG, Texas Instruments, Mitsubishi.
The Intel 8088, released in 1979, was a slightly modified chip with
an external 8-bit data bus and is notable as the processor used in
the original IBM PC.
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Fig1: 8086 CPU Chip in DIP Package
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Fig2: CPU Chip
The architecture was defined by Stephen P. Morse with some help and assistance
by Bruce Ravenel (the architect of the 8087) in refining the final revisions. Logic
designer Jim McKevitt and John Bayliss were the lead engineers of the hardwarelevel development team and William Pohlman the manager for the project.
The legacy of the 8086 is enduring in the basic instruction set of today's personal
computers and servers; the 8086 also lent its last two digits to later extended
versions of the design, such as the Intel 286 and the Intel 386, all of which
eventually became known as the x86 family.
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It was implemented using depletion-load nMOS circuitry with

approximately 20,000 active transistors (29,000 counting all ROM and
PLA sites).
It was soon moved to a new refined nMOS manufacturing process called
HMOS (for High performance MOS) that Intel originally developed for
manufacturing of fast static RAM products.
This was followed by HMOS-II, HMOS-III versions, and, eventually, a
fully static CMOS version for battery-powered devices, manufactured
using Intel's CHMOS processes.
The original chip measured 33 mm (assume a square of side
length=0.57cm) and minimum feature size was 3.2 m.
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How it works, what is its architecture, what is its instruction set architecture,
how it is programmed, how it is interfaced with other devices etc. etc.
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8086 is first x86 microprocessor.

The term x86 refers to a family of instruction set architectures based on the Intel 8086
CPU. The 8086 was launched in 1978 as a fully 16-bit extension of Intel's early 8-bit
based microprocessors and also introduced segmentation to overcome the 16-bit
addressing barrier of earlier chips. The term x86 derived from the fact that early
successors to the 8086 also had names ending in "86". Many additions and extensions
have been added to the x86 instruction set over the years, almost consistently with full
backward compatibility.The architecture has been implemented in processors from
Intel, Cyrix, AMD, VIA, and many others.
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The PC market which uses Intel based devices takes up some 60% of the total
microprocessor market! The other main processor used by industry is the
Motorola 68000 family of microprocessors.
The 8086 is/was probably the most commonly used 16-bit microprocessor of
all time, with the upwardly compatible families of microprocessors developed
from it now at the heart of the virtually all personal computers. This makes the
8086 the number one choice as a platform for teaching microprocessor
principles.
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x86-32: EP80579 Intel CE Atom

x86-64: Atom (some) Celeron
Pentium (Dual-Core) Core (i3 i5 i7)
Xeon
Other: Itanium
x86 Assemblers: A86/A386 FASM
GAS HLA MASM NASM TASM
WASM YASM
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Key features of a trainer kit are :
8086/8088 CPU operating at 2.5/5 MHz.

16 KB RAM with Battery backup expandable upto 256 KB.
16 KB powerful monitor EPROM.
24 I/O lines using 8255.
16 bit Timer/Counter using 8253.
RS-232C Interface using 8251.
8259 Interrupt Controller.
27 Series EPROM Programmer.
Printer Interface [Optional].
These kits are prepared and supplied by

many suppliers in India also for training and
education purpose.
Fig: 8086 kit

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Address Bus 20 lines A19 A0

Address
Bus
Data Bus 16 lines D15 D0
Microprocessor
8086
16 bit- microprocessor ?
16-bits data bus?
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Data
Bus
Control
signals
17
It can address any one of

1,048,576 (=220 ) memory
locations/addresses.
Each memory location is
one byte wide.
To store a word of 16 bit 2
memory
locations
are
required.
If the first byte of the
word is at even address
8086 can read the entire
word in one operation.
If the first byte of the word
is at an odd address, the
8086 will read the first byte
with one bus operation and
the second byte with
another bus operation.
A19A0
0.0
00000H
1.1
FFFFFH
00000H
Memory
Address
Space
1,048,576 memory locations=1MBytes

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FFFFFH
18
2 units are:
1. BIU
2. EU
Fig: 8086 Internal block diagram .

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BIU (bus interface unit) sends out addresses,

fetches instructions from memory, reads data
from ports and memory, and writes data to
ports and memory. In other words, the BIU
handles all transfers of data and addresses on
the buses for the execution unit.
EU (execution unit) of the 8086 tells the BIU
where to fetch instructions or data from,
decodes
instructions,
and
executes
instructions.
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21
8086 Architecture
8086 Microprocessor is divided into two

independent functional parts.
The Execution Unit (EU).
Bus Interface Unit (BIU).
This division into two units speeds up

processing.
The Execution Unit

EU contains control circuitry which directs
internal operations.
A decoder in the EU translates instructions
fetched from memory into a series of
actions which EU carries out.
EU consists of GPRs and other Pointer
and Index registers.
EU consists of 16 bit ALU which carries out
addition, subtraction, AND, OR, XOR,
increment, decrement, complement, or shift
binary numbers.
Bus Interface Unit

The BIU sends out addresses, fetches
instructions from memory, reads data
from ports and memory, and writes data
to ports and memory.
In other words BIU handles all transfer
of data and addresses on the buses for
the execution unit.
Instruction QUEUE
While an EU is decoding an instruction or executing an instruction

which does not require use of the buses, the BIU fetches upto 6
instructions bytes for the following instruction.
The BIU stores these prefetched bytes in a FIFO register set called
a queue.
When EU is ready for its next instruction, it simply reads the queue
in the BIU.
This is much faster than sending out the address to the memory
and waiting for the memory to send back the next instruction byte.
Machine Cycle
Each time CPU executes an instruction it takes some steps, called

machine cycle.
A machine cycle can be broken down into smaller cycles such as

instruction cycle and execution cycle.
Fetching: Before the CPU can execute an instruction, the control unit must
retrieve (or fetch) a command or data from the computers memory.

Decoding: Before a command can be executed, the control unit must break
down (or decode) the command into instructions.
Machine Cycle
Executing: Part of the execution cycle. When the command is executed,
the CPU carries out the instructions in order by converting them into
microcode.
Storing: The CPU maybe required to store the results of an instruction in
memory.
Pipelining
Fetching the next instruction while the current instruction executes

is called pipelining.
The control unit begins a new machine cycle, that is it begins

executing a new instruction before the current cycle is completed.
Executions are performed in stages, when the first instruction

completes the fetching stage, it moves to the decode stage, and a
new instruction is fetched.
Using this technology, new microprocessors can execute up to six

instructions simultaneously
Stack Addressing
The 8086 let you set aside an entire 64Kb

segment as a stack.
The upper 16bits of the starting address for this

segment are kept in the stack segment register.
The stack pointer register holds the offset (16 bit).
The memory location where a word was most

recently stored is called the top pf stack.
Stack Addressing
The physical address for a stack read or
a stack write is produced by adding the
contents of the stack pointer register to
the stack segment register.
Example:
SS = 5000H * 10H = 50000H
SP = FFE0H
SS + SP = 50000H + FFE0H
= 5FFE0H
Immediate Addressing Mode

Suppose that in a program you need to put the
number 437BH in the CX register.
The MOV CX, 437BH instruction can be used to
do this.
When it executes this instruction will put the
immediate hexadecimal number 437BH in the
16-Bit CX register.
This is referred to as immediate addressing
mode.
Register Addressing Mode

Register addressing mode means that the
register is the source of an operand for an
instruction.
Example: The instruction MOV CX,AX.
The destination location is specified before the
comma and the source is specified after the
comma.
Note that the content of AX are just copied to CX,
not moved.
Direct Addressing Mode
For the simplest memory addressing mode, the

effective address is just a 16-Bit number written
directly in the instruction.
Example: MOV BL, [437AH].
The square brackets around the 437AH are shorthand
for the content of the memory location.
When executed the content of that memory location
will be copied in the BL register.
The BIU calculates the 20-Bit physical address by
adding the effective address 437AH to the segment
base address.
This is called direct addressing mode.

1 Introduction 8086

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12/12/2013

Internal architecture of Intel 8086 microprocessor: Block diagram, Registers, Internal

Basic 8086/8088 configuration, Minimum mode and maximum mode. Comparison of

16-bit Processors and Segmentation (1978)

The Intel 286 Processor (1982)

24-bit addressing, 16 Mbytes address space.

The Intel386 Processor (1985)

The Intel486 Processor (1989)

Expanded instruction decode and execution units into five

The Intel Pentium Processor (1993)

added a second execution pipeline to achieve superscalar

The P6 Family of Processors (1995-1999)

Intel Pentium Pro processor

The Intel Pentium 4 Processor Family (2000-2005)

The Intel Xeon Processor (2001-2005)

introduced support for Hyper-Threading Technology

The Intel Pentium M Processor (2003-2005)

The Intel Pentium Processor Extreme Edition (2005)

Find out whats new ??

Introduction to Intel 8086 microprocessor

Released by Intel in 1978

Fig1: 8086 CPU Chip in DIP Package

Fig2: CPU Chip

It was implemented using depletion-load nMOS circuitry with

8086 is first x86 microprocessor.

x86-32: EP80579 Intel CE Atom

Key features of a trainer kit are :

8086/8088 CPU operating at 2.5/5 MHz.

These kits are prepared and supplied by

Fig: 8086 kit

Address Bus 20 lines A19 A0

It can address any one of

1,048,576 memory locations=1MBytes

Fig: 8086 Internal block diagram .

BIU (bus interface unit) sends out addresses,

8086 Microprocessor is divided into two

This division into two units speeds up

The Execution Unit

Bus Interface Unit

While an EU is decoding an instruction or executing an instruction

Each time CPU executes an instruction it takes some steps, called

A machine cycle can be broken down into smaller cycles such as

retrieve (or fetch) a command or data from the computers memory.

down (or decode) the command into instructions.

Executing: Part of the execution cycle. When the command is executed,

Fetching the next instruction while the current instruction executes

The control unit begins a new machine cycle, that is it begins

Executions are performed in stages, when the first instruction

Using this technology, new microprocessors can execute up to six

The 8086 let you set aside an entire 64Kb

The upper 16bits of the starting address for this

The stack pointer register holds the offset (16 bit).

The memory location where a word was most

Immediate Addressing Mode

Register Addressing Mode

Direct Addressing Mode

For the simplest memory addressing mode, the

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