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module logic_gates(a,b,y1,y2,y3,y4,y5,y6,y7,y8);
input a,b;
output y1,y2,y3,y4,y5,y6,y7,y8;
buf (y1,a);
not (y2,a);
or (y3,a,b);
nor (y4,a,b);
and (y5,a,b);
nand (y6,a,b);
xor (y7,a,b);
xnor (y8,a,b);
endmodule
HALF ADDER & FULL ADDER
module half_adder(a,b,sum,carry);
input a,b;
output sum,carry;
xor (sum,a,b);
and (carry,a,b);
endmodule
module full_adder(a,b,c,sum,carry);
input a,b,c;
output sum,carry;
assign sum = a^b^c;
assign carry = (a&b)|(b&c)|(c&a);
endmodule
PARALLEL ADDER
module parallel_adder(a,b,cin,sum,cout);
input [3:0] a,b;
input cin;
output [3:0] sum;
output cout;
assign {cout,sum}= a + b + cin;
endmodule
PARALLEL SUBTRACTOR
module parallel_subtractor(x,y,bin,difference,bout);
input [3:0] x,y;
input bin;
output [3:0] difference;
output bout;
assign {bout,difference}= x - y - bin;
endmodule
CARRY LOOK AHEAD ADDER
module CLA_adder (a,b,cin,sum,cout);
input [3:0]a,b;
input cin;
output[3:0]sum;
output cout;
wire po,p1,p2,p3,g0,g1,g2,g3;
wire c1,c2,c3,c4;
assign p0 = (a[0] ^ b[0]),
p1 = (a[1] ^ b[1]),
p2 = (a[2] ^ b[2]),
p3 = (a[3] ^ b[3]);
assign g0 = (a[0] & b[0]),
g1 = (a[1] & b[1]),
g2 = (a[2] & b[2]),
g3 = (a[3] & b[3]);
assign c0=cin,
c1=g0 | (p0 & cin),
c2 = g1 | (p0 & g0) | (p1 & p0 & cin),
c3 = g2 | (p2 & g1) | (p2 & p1 & g0) | (p2 & p1 & p0 & cin),
c4 = g3 | (p3 & g2) | (p3 & p2 & g1) | (p3 & p2 & p1 & g0) | (p3 & p2 & p1 & p0
& cin);
assign sum[0]=p0 ^ c0,
sum[1]=p1 ^ c1,
sum[2]=p2 ^ c2,
sum[3]=p3 ^ c3;
assign cout = c4;
endmodule
module mux16(out,sel,a);
output out;
input [15:0]a;
input [3:0]sel;
wire w1,w2,w3,w4;
not(s0,sel[0]);
not(s1,sel[1]);
not(s2,sel[2]);
not(s3,sel[3]);
mux41 mux1(w1,sel[0],sel[1],a[3],a[2],a[1],a[0]);
mux41 mux2(w2,sel[0],sel[1],a[7],a[6],a[5],a[4]);
mux41 mux3(w3,sel[0],sel[1],a[11],a[10],a[9],a[8]);
mux41 mux4(w4,sel[0],sel[1],a[15],a[14],a[13],a[12]);
mux41 mux5(out,sel[2],sel[3],w1,w2,w3,w4);
endmodule
8 BIT MULTIPLIER
module multiplier_8_bit (a,b,c);
input [7:0]a;
input [7:0]b;
output [15:0]c;
assign c[15:0] = a[7:0]*b[7:0];
endmodule
D FLIPFLOP
module D_FF (D,clk,reset,Q);
input D,clk,reset;
output Q;
reg Q;
always @ (posedge reset or negedge clk)
if (reset)
Q = 1'b0;
else
Q = D;
endmodule
T FLIPFLOP
module T_FF (T,clk,reset,Q);
input T,clk,reset;
output Q;
wire w;
assign w = T^Q;
D_FF dff1(w,clk,reset,Q);
endmodule
module D_FF (D,clk,reset,Q);
input D,clk,reset;
output Q;
reg Q;
always @ (posedge reset or negedge clk)
if (reset)
Q = 1'b0;
else
Q = D;
endmodule
JK FLIPFLOP
module JK_FF (J,K,clk,reset,Q);
input J,K,clk,reset;
output Q;
wire w;
assign w = (J&~Q)|(~K&Q);
D_FF dff1(w,clk,reset,Q);
endmodule
module D_FF (D,clk,reset,Q);
input D,clk,reset;
output Q;
reg Q;
always @ (posedge reset or negedge clk)
if (reset)
Q = 1'b0;
else
Q = D;
endmodule
input LFin,RTin;
// serial inputs
input clk,reset;
input[3:0]PIin;
// parallel input
output q3,q2,q1,q0; // register output
reg q3,q2,q1,q0;
always @ (posedge clk or posedge reset)
if (reset)
{q3,q2,q1,q0}=4'b0000;
else
case ({s1,s0})
2'b00:{q3,q2,q1,q0}={q3,q2,q1,q0};
2'b01:{q3,q2,q1,q0}={RTin,q3,q2,q1};
2'b10:{q3,q2,q1,q0}={q2,q1,q0,LFin};
2'b11:{q3,q2,q1,q0}=PIin;
endcase
endmodule
// No change
// Shift right
// Shift left
// Parallel load input
RING COUNTER
reg run;
always @(posedge clk)
begin
if (reset== 1)
begin
q<=0;
run <= 0;
end
else if (reset == 0)
begin
run <= 1;
end
if (run)
begin
q[3:1] <= q[2:0];
q[0] <= (!q[3]);
end
end
endmodule
SHIFT REGISTER
CMOS INVERTER
module my_inv(in,out);
input in;
output out;
supply1 pwr;
supply0 gnd;
pmos ( out,pwr,in);
nmos (out,gnd,in);
endmodule
CMOS NOR GATE
module my_nor(a,b,out);
input a,b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos ( c,pwr,b);
pmos (out,c,a);
nmos(out,gnd,a);
nmos(out,gnd,b);
endmodule
CMOS NAND GATE
module my_nand(a,b,out);
input a,b;
output out;
wire c;
supply1 pwr;
supply0 gnd;
pmos ( out,pwr,a);
pmos (out,pwr,b);
nmos(out,c,a);
nmos(c,gnd,b);
endmodule
SR FLIPFLOP
module sr_flipflop(s,r,clk,q,qbar);
input s,r,clk;
output q,qbar;
reg q,qbar;
always@(posedge clk)
begin
case ({s,r})
2'b00:q=q;
2'b01:q=1'b0;
2'b10:q=1'b1;
2'b11:q=1'bx;
endcase
qbar=~q;
end
endmodule
SERIAL ADDER
module serial_adder(count2,count1,count0,clk,a0,a1,a2,a3,a4,a5,a6,a7,a8,result,add);
input count2,count1,count0;
input clk;
input a0,a1,a2,a3,a4,a5,a6,a7,a8;
output [3:0]add ,result;
reg [3:0]result,add;
always @ (posedge clk )
case ({count2,count1,count0})
3'b000 :begin
add=a0+a1;
end
3'b001 :begin
add=add+a2;
end
3'b010 :begin
add=add+a3;
end
3'b011 :begin
add=add+a4;
end
3'b100 :begin
add=add+a5;
end
3'b101 :begin
add=add+a6;
end
3'b110 :begin
add=add+a7;
end
3'b111 :begin
result=add+a8;
end
endcase
endmodule
3'b011 :begin
r0=0;
y0=1;
g0=0;
p0=0;
r1=0;
y1=1;
g1=0;
p1=0;
end
3'b100 :begin
r0=1;
y0=0;
g0=0;
p0=0;
r1=0;
y1=0;
g1=1;
p1=0;
end
3'b101 :begin
r0=1;
y0=0;
g0=0;
p0=0;
r1=0;
y1=1;
g1=0;
p1=0;
end
default :begin
r0=0;
y0=0;
g0=0;
p0=0;
r1=0;
y1=0;
g1=0;
p1=0;
end
endcase
endmodule