Cairo

University
Faculty of
Engineering

Electronics and
Electrical
Communications
Engineering Department

EEC 605 VLSI CAD Elective Course

M.Sc. Program in Electronics and Electrical Communications
1436/1437 H (2015/2016) Term 1
Final Exam Rabia Al-Akhar 1437 H (January 2016) - 3 Hours
Question 1 Layout Compaction
a. [4 marks] Sketch the Constraint Graph of 1D compaction generated from the irredundant constraints
in the X-direction of the shown modules, given that the minimum module width is (a), and that the
minimum separation between modules is (b).
4

7
1

Illustrate how the minimum width of the floorplan can be determined from the graph.
b. [4 marks] Explain how the maximum wire-width is represented in the Constraint Graph of the 1D
layout compaction problem. Explain the impact of the presence of maximum-distance constraints on
the topology of the Constraint Graph problem representation.
c. [4 marks] Write the mutually exclusive Mixed
Integer
Linear
Programming
(MILP)
constraints that describe the 2D minimum
spacing of the two metal areas shown in the
following figure, where , , and are the
three binary variables used to enable or
disable the horizontal, vertical, and diagonal
constraints, respectively. Assume that the
positive directions of the x-axis and the y-axis
in the figure are left-to-right and up-to-down,
respectively. Explain how mutual exclusion
of these constraints is expressed in MILP in
terms of , , and .

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Question 2 Placement and Partitioning

a. [4 marks] Explain briefly the constructive, iterative, and nondeterministic approaches used for
solving the VLSI placement problem, and how these approaches are combined to improve the quality
of the estimated solution.
b. [8 marks] Perform one pass of the Kernighan and Lin heuristic algorithm to illustrate the
optimization of the shown 2-way graph partitioning into = {, , } and = {, , }.

c
a

3
2

Question 3 Floorplanning
a. [4 marks] Find the best shape(s) for the V-Cut Slicing floorplan of the two flexible-shape modules A
and B, where A is 37 or 46 or 55, and B is 36 or 45 or 54.
b. [4 marks] Consider the floorplanning problem of eight modules: A and B are 124, C and D are 88,
E and F are 84, and finally G and H are 44. Sketch the tree representation of the slicing floorplan
expressed by the polish expression ABC|D|EFG|H | , and estimate the total area of the
floorplan.
c. [8 marks] Consider extending the Wong-Liu simulated-annealing algorithm such that a new floorplan
is generated from the present floorplan by applying an ordered set of one or more move operators.
Starting with the polish expression in part (b), write the polish expression of the floorplan, and
estimate its total area after applying each of the following ordered sets of move operators:
1.
2.
3.
4.

S1 = {OP1(F, G), OP1(E, G)}

S2 = {OP1(D, G), OP1(D, E)}
S3 = {OP1(C, G), OP1(C, E)}
S4 = {OP1(B, G), OP1(B, E), OP1(B, C), OP1(B, D), OP1(B, F)}

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Question 4 Global Routing

a. [4 marks] Explain briefly the constraints of the VLSI routing problem.
b. [4 marks] Explain briefly how starting-point selection, double fan-out, and framing improve the run
time of the Lees Maze routing algorithm.
c. [4 marks] Use Hadlocks routing algorithm to find the shortest path
between and in the following grid graph.

d. [2 marks] Compare the computation time and space requirement of the line-search global routing
algorithms to grid-search global routing algorithms.
Question 5 Detailed Routing
a. [4 marks] Explain briefly the difference between reserved and unreserved layer models in multiplelayer routing, and describe briefly the three types of three-layer routing.
b.

[4 marks] Find a feasible net ordering and detailed routing of the four
nets a, b, c, and d shown in figure based on ascending order of the
number of pins in the bounding box.

a
b

d
c
c
d
a
b

c. [2 marks] Explain how the extended channel intersection graphs are used to represent the channel
routing problem.
d. [8 marks] Use the left-edge algorithm to solve the following 2-layer channel routing problem, and
find the minimum number of tracks.
10402653056007

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23405007010004

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