Faculty of Engineering and Science

UEEP2613 Microelectronic Fabrication

Assignment Report

NAME: LOW CHI YANG

STUDENT ID: 1402951
LECTURER: Dr Lim Soo King

Objectives:
A.) To design a 2 input NAND gate using P-CMOS and N-CMOS
B.) To create the masks for the fabrication process of 2 input Quad NAND gate
Design of the NAND Gate
2 input NAND gate can be implement as below,

Figure 1: Circuit Diagram of NAND Gate

As show above, NAND gate can be designed using two P MOS arrange parallel and N MOS
arrange in series. Left P MOS gate and top N MOS gate are connected to input a and remaining
gates are connected to input b. The response of the circuit can summarized as below.

Figure 2 : A=0 B=0 Output=1

Figure 3 : A=1 B=0 Output=1

Figure 4: A=0 B=0 Output =1

Figure 5 A=1 B=1 Output =0

The results can be tabulated in a truth table.

A
0
1
0
1

B
0
0
1
1

Output
1
1
1
0

The truth table is a truth table of NAND gate, thus circuit above is a NAND Gate
Next, one can design the IC of the device using Microwind software. The design is shown below.

Figure 6 IC design of the 4 2 input NAND gate

The analogue simulation the design is given below

Figure 7 Analog simulation of the device

From the design from the previous picture, one can design the mask for the fabrication process.
The fabrication process would be a 41steps SAJI process however for the assignment purpose
some steps will be omitted. It is worth mentioning that Vss is shorted top substrate and VDD is
shorted to the n well to prevent the parasitic NPN and PNP transistor from affecting the
performance of the device.

Mask Design and Fabrication Process

The mask used positive photoresist. The first step of the process is to fabricate the n-well in the p
type substrate. It is done by growing a thin layer oxide, then use the mask #1 to etch the oxide
proceed with ion implantation. Then the oxide layer is removed.

Figure 8: Mask #1
The next step of the fabrication process is to grow a field oxide layer follow by Silicon Nitride
on the active area. It can be done by using mask #2. First, the whole wafer was cover with oxide
layer then top with a layer of silicon later. Then etch away the unwanted part of the oxide and
Silicon Nitride using the mask #2. In addition , the part of the unmasked p substrate will be
etched way to form isolation. At this point of the process , the threshold voltage of the field oxide
can be controlled by ion implantation.

Figure 9: mask #2

The next step is to fabricate the gate of the device. It is done by growing an oxide layer first then
follow by a polysilicon layer. Next mask #3 is used to etch away the unwanted part of the
polysilicon layer.

Figure 10: Mask #3

The next step of the fabrication process is the light doping process Mask #4 is used to dope the p
drain and source of the p MOS and Mask #5 is used to dope n drain and source of the n MOS.
Next step is to grow a layer of oxide to prepare for self-align junction for heavily doped drains
and sources. It begins with simply growing an oxide layer over the top of the gate. Next is to
create a spacer using etch back so that there is a thick layer oxide around the polysilicon gate.
Next using then mask #4 and mask#5 to heavily doped the exposed part. Since the dopant cannot
penetrate the thick layer oxide around the polysilicon gate, there is a lightly doped region around
the polysilicon gate.

Figure 11 : Mask #4

Figure 12: Mask#5

The next step is to create via for connection. The process starts with growing an oxide layer.
Then mask #6 is used to etch away the oxide to form a via. Next, the photoresist is removed and
the via is filled with metal.

Figure 13: Mask #6

The next step of the fabrication process is to etch away the unwanted part of the metal to form a
proper connection between via. Mask #7 is used to achieved this. Hence concluded the first layer
metal connection.

Figure 14: Mask #7

Next step is to form second layer connection by using Mask #8 and Mask #9. The process
is similar to the process for the first layer metal connection,
Conclusions
The 2 input 4 NAND gate basically is the 10 pin IC devices used in UTAR lab. The various mask
designed for the lithography process in the fabrication of the device.