FPGA IMPLEMENTATION OF IDEA

M.Ananthi
Lecturer, Department of Electrical and Electronics Engineering
OXFORD ENGINEERING COLLEGE, TRICHY.
E-mail : anandhimanivannan1990@gmail.com
Contact No: 9790395578.

FPGA IMPLEMENTATION OF IDEA

ABSTRACT:
This paper describes three types of architectures in the IDEA cryptographic algorithm
and these are implemented on FPGA. The three types of architectures are,
1. Combinational logic
2. Sequential coarse grain pipelining
3. Sequential fine grain pipelining
The high speed and low power has been achieved by using the pipelining concept.
1. INTRODUCTION:
IDEA stands for International Data Encryption Algorithm, which uses algebraic
operations completely and it entirely avoids the use of any lookup tables or S-boxes. The
algebraic operations are,
1. Bit-by Bit XOR
2. Modulo addition
3. Modulo multiplication
Modulo multiplication increases the strength of the IDEA. The IDEA is a symmetric,
block oriented encryption algorithm, which operates on a 64-bit plaintext and uses a 128 bit
length key. In this 128 bit key, generate 8 Subkeys first. This 64-bit plaintext block is divided
into 4 portions of plain text (each of size 16 bits). There are 8 such rounds. In each round, 6 subkeys are used. These sub-keys are applied to the 4 input blocks P1 to P4. Thus, for the 1 st round
there are 6 sub-keys K1 to K6. To generate the rest of the sub -keys for the remaining rounds the
original key left circularly by 25 bits to avoid the repetition. For the 2 nd round, there are keys K7
to K12. Finally, we will have keys K43 to K48. The final step consists of an Output
Transformation, which uses just 4 sub-keys. It totally consists of 8 and half rounds , which
shown in the fig 2.1.The final output produced is the output produced by the Output
Transformation round. The decryption is also similar to the encryption. The same 52 key sub
blocks generated for encryption are rearranged and inverted accordingly to produce the
decryption key schedule.

2. BLOCK DIAGRAM OF IDEA:

Fig. 2.1: Block Diagram of IDEA

3. ARCHITECTURES OF IDEA:
3.1. COMBINATIONAL LOGIC:
Final
transformation
6 subkeys
for 1st
round

Fig. 3.1.1: RTL viewer of combinational logic

3.3. SEQUENTIAL COARSE LEVEL PIPELINING:

round:a1
clk
pt[63..0]
k[127..0]

clk

round:a2

pt[63..0]
s1[15..0]
s2[15..0]
s3[15..0]
s4[15..0]
s5[15..0]
s6[15..0]

clk
ct[63..0]

round:a3

pt[63..0]
s1[15..0]
s2[15..0]
s3[15..0]

clk
ct[63..0]

s4[15..0]
s5[15..0]
s6[15..0]

pt[63..0]

round:a4

s1[15..0]
s2[15..0]

clk
ct[63..0]

s3[15..0]

pt[63..0]

round:a5

s1[15..0]

s4[15..0]

s2[15..0]

s5[15..0]

s3[15..0]

s6[15..0]

clk
ct[63..0]

pt[63..0]

s4[15..0]

s2[15..0]

s5[15..0]

s3[15..0]

s6[15..0]

round:a6

s1[15..0]
clk
ct[63..0]

s4[15..0]
s5[15..0]
s6[15..0]

pt[63..0]

round:a7

s1[15..0]
s2[15..0]
s3[15..0]

clk
ct[63..0]

pt[63..0]

round:a8

s1[15..0]

s4[15..0]

s2[15..0]

s5[15..0]

s3[15..0]

s6[15..0]

s4[15..0]
s5[15..0]
s6[15..0]

clk
ct[63..0]

pt[63..0]

mod:s1

s1[15..0]
s2[15..0]

ct[63..0]

s3[15..0]

a[15..0]

c[15..0]

b[15..0]

s4[15..0]
s5[15..0]
s6[15..0]

Add0
A [15..0]
B [15..0]

+
ADDER

Add1

ct[63..0]

A [15..0]
B [15..0]

+
ADDER

mod:s2
a[15..0]

c[15..0]

b[15..0]

Fig. 3.3.1: RTL viewer of sequential coarse level pipelining

ARCHITECTURES

AREA
ALUT

REG

POWER
Memo

Static

Dynamic

FREQ
I/O

ry

Combinational Logic

2467

Coarse level

0
2478

102

pipelining
Fine level pipelining

9
2479

4
1120

Transitio
ns

371.07mW

4.95mW

38.75m

3446

0.729

580.89mW

5438.64m

W
73.75m

1172597

24.6

588.44mW

W
5681.51m

W
69.16m

1172316

24.7

4. RESULT:
Table.4.1: Comparison of Architectures in area, power, frequency

100%
80%
60%

AREA Memory

40%

AREA REG

20%

AREA ALUT

0%
Combinational Logic

Coarse level pl

Fine level pl

Fig.4.1: Comparison of area

FREQUENCY(in MHz)
30
FREQUENCY(in MHz)

20
10
0
Combinational Logic

Coarse level pipelining

Fine level pipelining

Fig.4.2: Comparison of frequency

Fine level pl

POWER I/O(in mW)

Coarse level pl

POWER Dynamic(in mW)

POWER Static (in mW)

Combinational Logic

0%

20%

40%

60%

80%

Fig.4.3: Comparison of power

100%

5. CONCLUSION:
In this paper the three types of Architectures have been implemented and the speed is
increased in fine level pipelining compared with other architectures. By using the modulo
multiplication, the strength of the IDEA have been increased. The big process, inverse modulo
multiplication have been done in the decryption.
REFERENCES:
Atul Kahate Cryptography and Network Security Tata McGraw-Hill Education,
2003.
William Stallings Cryptography and Network Security Principles and Practices 3rd
edition.
Rahul Ranjan1 and I. Ponguzhali2,VLSI Implementation of IDEA Encryption
Algorithm.
web page:www.quadibloc.com/crypto/co040302.html.
Wep page:http://www.shodor.org/interactivate/discussions/CryptographyCipher/
M. Thaduri1, S.-M. Yoo2, R. Gaede3,An efficient VLSI implementation of IDEA
encryption algorithm using VHDL.
,P Kitsos1, O Koufopavlou2, G Selimis3 and N Sklavos4, Low power cryptography
Nick Hoffman1,A Simplified IDEA Algorithm.
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implementation of ICE encryption algorithm.
Rachit Agarwal1, Emanuel Popovici2, Brendan OFlynn3, Coml. OKeeffe4,Low Power
Hardware and Software Implementation of IDEA NXT Algorithm.