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Core Features:
Memory:
Operating Characteristics:
Operating Voltage Range:
- 1.8V to 3.6V (PIC12LF1571/2)
- 2.3V to 5.5V (PIC12F1571/2)
Temperature Range:
- Industrial: -40C to +85C
- Extended: -40C to +125C
Internal Voltage Reference module
In-Circuit Serial Programming (ICSP) via
Two Pins
Digital Peripherals:
16-Bit PWM:
- Three 16-bit PWMs with independent timers
- Multiple Output modes (Edge-Aligned,
Center-Aligned, Set and Toggle on
Register Match)
- User settings for phase, duty cycle, period,
offset and polarity
- 16-bit timer capability
- Interrupts generated based on timer matches
with Offset, Duty Cycle, Period and Phase
registers
Complementary Waveform Generator (CWG):
- Rising and falling edge dead-band control
- Multiple signal sources
Enhanced Universal Synchronous Asynchronous
Receiver Transceiver (EUSART):
- Supports LIN applications
DS40001723D-page 1
PIC12(L)F1571/2
Analog Peripherals:
Clocking Structure:
High-Endurance
Flash (bytes)
I/O Pins
8-Bit/16-Bit Timers
Comparators
16-Bit PWM
5-Bit DAC
CWG
EUSART
Debug(1)
XLP
PIC12(L)F1571
128
128
2/4(2)
PIC12(L)F1572
256
128
2/4(2)
Device
Note 1:
2:
DS40001723
DS40001723D-page 2
PIC12(L)F1571/2 Data Sheet, 8-Pin Flash, 8-Bit MCU with High-Precision 16-Bit PWM.
PIC12(L)F1571/2
PIN DIAGRAMS
RA5
RA4
RA3/MCLR/VPP
PIC12(L)F1572
VDD
PIC12(L)F1571
VSS
RA0/ICSPDAT
RA1/ICSPCLK
RA2
8-Pin PDIP/SOIC/MSOP/DFN/UDFN
ADC
Reference
Comparator
Timers
PWM
EUSART(2)
CWG
Interrupt
Pull-up
Basic
I/O
TABLE 1:
RA0
AN0
DAC1OUT
C1IN+
PWM2
TX(2)
CK(2)
CWG1B
IOC
ICSPDAT
ICDDAT
RA1
AN1
VREF+
C1IN0-
PWM1
RX(2)
DT(2)
IOC
ICSPCLK
ICDCLK
RA2
AN2
C1OUT
T0CKI
PWM3
CWG1FLT
CWG1A
IOC
INT
RA3
T1G(1)
IOC
MCLR
VPP
RA4
AN3
C1IN1-
T1G
PWM2(1)
TX(1,2)
CK(1,2)
CWG1B(1)
IOC
CLKOUT
RA5
T1CKI
PWM1(1)
RX(1,2)
DT(1,2)
CWG1A(1)
IOC
CLKIN
VDD
VDD
Vss
VSS
Note 1:
2:
Alternate pin function selected with the APFCON (Register 11-1) register.
PIC12(L)F1572 only.
DS40001723D-page 3
PIC12(L)F1571/2
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7
2.0 Enhanced Mid-Range CPU ........................................................................................................................................................ 13
3.0 Memory Organization ................................................................................................................................................................. 15
4.0 Device Configuration .................................................................................................................................................................. 41
5.0 Oscillator Module........................................................................................................................................................................ 47
6.0 Resets ........................................................................................................................................................................................ 59
7.0 Interrupts .................................................................................................................................................................................... 69
8.0 Power-Down Mode (Sleep) ........................................................................................................................................................ 83
9.0 Watchdog Timer (WDT) ............................................................................................................................................................. 87
10.0 Flash Program Memory Control ................................................................................................................................................. 91
11.0 I/O Ports ................................................................................................................................................................................... 109
12.0 Interrupt-On-Change ................................................................................................................................................................ 119
13.0 Fixed Voltage Reference (FVR) ............................................................................................................................................... 123
14.0 Temperature Indicator Module ................................................................................................................................................. 127
15.0 Analog-to-Digital Converter (ADC) Module .............................................................................................................................. 129
16.0 5-Bit Digital-to-Analog Converter (DAC) Module ...................................................................................................................... 143
17.0 Comparator Module.................................................................................................................................................................. 147
18.0 Timer0 Module ......................................................................................................................................................................... 155
19.0 Timer1 Module with Gate Control............................................................................................................................................. 159
20.0 Timer2 Module ......................................................................................................................................................................... 171
21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 175
22.0 16-Bit Pulse-Width Modulation (PWM) Module ........................................................................................................................ 203
23.0 Complementary Waveform Generator (CWG) Module ............................................................................................................ 231
24.0 In-Circuit Serial Programming (ICSP) ............................................................................................................................... 243
25.0 Instruction Set Summary .......................................................................................................................................................... 245
26.0 Electrical Specifications............................................................................................................................................................ 259
27.0 DC and AC Characteristics Graphs and Charts ....................................................................................................................... 283
28.0 Development Support............................................................................................................................................................... 305
29.0 Packaging Information.............................................................................................................................................................. 309
Appendix A: Data Sheet Revision History.......................................................................................................................................... 327
The Microchip Web Site ..................................................................................................................................................................... 329
Customer Change Notification Service .............................................................................................................................................. 329
Customer Support .............................................................................................................................................................................. 329
Product Identification System............................................................................................................................................................. 331
DS40001723D-page 4
PIC12(L)F1571/2
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip
products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and
enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via
E-mail at docerrors@microchip.com. We welcome your feedback.
Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current
devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision
of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
Microchips Worldwide Web site; http://www.microchip.com
Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are
using.
DS40001723D-page 5
PIC12(L)F1571/2
NOTES:
DS40001723D-page 6
PIC12(L)F1571/2
1.0
DEVICE OVERVIEW
1.1
Peripheral
PIC12(L)F1572
DEVICE PERIPHERAL
SUMMARY
PIC12(L)F1571
TABLE 1-1:
Enhanced Universal
Synchronous/Asynchronous
Receiver/Transmitter (EUSART)
REGISTER NAMES
1.1.2
BIT NAMES
1.1.2.1
Temperature Indicator
C1
PWM1
PWM2
PWM3
Timer0
Timer1
Timer2
Comparators
PWM Modules
Timers
1.1.1
DS40001723D-page 7
PIC12(L)F1571/2
1.1.2.2
1.1.2.3
Bit Fields
1.1.3
1.1.3.1
1.1.3.2
Legacy Peripherals
COG1CON0bits.MD = 0x5;
Individual bits in a bit field can also be accessed with
long and short bit names. Each bit is the field name
appended with the number of the bit position within the
field. For example, the Most Significant mode bit has
the short bit name, MD2, and the long bit name is
G1MD2. The following two examples demonstrate
assembly program sequences for setting the COG1 to
Push-Pull mode:
Example 1:
MOVLW
ANDWF
MOVLW
IORWF
~(1<<G1MD1)
COG1CON0,F
1<<G1MD2 | 1<<G1MD0
COG1CON0,F
Example 2:
BSF
BCF
BSF
COG1CON0,G1MD2
COG1CON0,G1MD1
COG1CON0,G1MD0
DS40001723D-page 8
PIC12(L)F1571/2
FIGURE 1-1:
Program
Flash Memory
RAM
PORTA
CLKOUT
Timing
Generation
CPU
CLKIN
INTRC
Oscillator
(Note 3)
MCLR
TMR2
TMR1
CWG1
Note 1:
2:
3:
4:
TMR0
C1
Temp
Indicator
ADC
10-bit
PWM3
DAC
PWM2
FVR
PWM1
EUSART(4)
DS40001723D-page 9
PIC12(L)F1571/2
TABLE 1-2:
Name
RA0/AN0/C1IN+/DACOUT/
TX(2)/CK(2)/CWG1B/PWM2/
ICSPDAT/ICDDAT
Function
Input
Type
Output
Type
RA0
AN0
C1IN+
DACOUT
TX
(4)
CK
PWM2
PWM output.
ICSPDAT
ICDDAT
RA1
AN1
VREF+
C1IN0RX
(4)
DT
PWM output.
ICSPCLK
ICDCLK
RA2
AN2
C1OUT
Comparator output.
T0CKI
(3)
(4)
CWG1FLT
PWM3
PWM output.
INT
External interrupt.
RA3
VPP
(3)
(4)
T1G
Programming voltage.
Timer1 gate input.
Master Clear with internal pull-up.
MCLR
RA4/AN3/C1IN1-/T1G/TX(1,2)/
CK(1,2)/CWG1B(1)/PWM2(1)/
CLKOUT
CWG1A
RA3/VPP/T1G(1)/MCLR
PWM1
RA2/AN2/C1OUT/T0CKI/
CWG1FLT/CWG1A/PWM3/INT
CWG1B
RA1/AN1/VREF+/C1IN0-/RX(2)/
DT(2)/PWM1/ICSPCLK/ICDCLK
Description
RA4
AN3
C1IN1-
T1G
TX
CK
CWG1B
PWM2
CLKOUT
(4)
DS40001723D-page 10
OD = Open-Drain
I2C = Schmitt Trigger input with I2C
levels
PIC12(L)F1571/2
TABLE 1-2:
Name
RA5/T1CKI/RX(1,2)/DT(1,2)/
CWG1A(1)/PWM1(1)/CLKIN
Function
Input
Type
Output
Type
General purpose I/O.
RA5
T1CKI
RX
DT
Description
(4)
CWG1A
PWM1
PWM output.
CLKIN
VDD
VDD
Power
Positive supply.
VSS
VSS
Power
Ground reference.
OD = Open-Drain
I2C = Schmitt Trigger input with I2C
levels
DS40001723D-page 11
PIC12(L)F1571/2
NOTES:
DS40001723D-page 12
PIC12(L)F1571/2
2.0
FIGURE 2-1:
15
Configuration
15
MUX
Flash
Program
Memory
Data Bus
16-Level Stack
(15-bit)
RAM
14
Program
Bus
Program Counter
12
Program Memory
Read (PMR)
RAM Addr
Addr MUX
Instruction Reg
Direct Addr
7
5
Indirect
Addr
12
12
BSR Reg
15
FSR0 Reg
15
FSR1 Reg
STATUS Reg
Instruction
Decode and
Control
CLKIN
CLKOUT
Timing
Generation
Internal
Oscillator
Block
Power-up
Timer
Power-on
Reset
Watchdog
Timer
Brown-out
Reset
VDD
MUX
ALU
W Reg
VSS
DS40001723D-page 13
PIC12(L)F1571/2
2.1
2.2
DS40001723D-page 14
2.3
2.4
Instruction Set
There are 49 instructions for the enhanced midrange CPU to support the features of the CPU. See
Section 25.0 Instruction Set Summary for more
details.
PIC12(L)F1571/2
3.0
MEMORY ORGANIZATION
3.2
TABLE 3-1:
3.1
High-Endurance Flash
High-Endurance Flash
Memory Address Range(1)
PIC12(L)F1571
1,024
03FFh
0380h-03FFh
PIC12(L)F1572
2,048
07FFh
0780h-07FFh
Device
Note 1:
High-endurance Flash applies to the low byte of each address in the range.
DS40001723D-page 15
PIC12(L)F1571/2
FIGURE 3-1:
FIGURE 3-2:
Rev. 10-000040D
7/30/2013
PC<14:0>
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
PC<14:0>
15
CALL, CALLW
RETURN, RETLW
Interrupt, RETFIE
Stack Level 0
Stack Level 0
Stack Level 1
Stack Level 1
Stack Level 15
On-chip
Program
Memory
Stack Level 15
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
Rollover to Page 0
03FFh
0400h
Rollover to Page 0
7FFFh
DS40001723D-page 16
15
On-chip
Program
Memory
Reset Vector
0000h
Interrupt Vector
0004h
0005h
Page 0
Rollover to Page 0
07FFh
0800h
Rollover to Page 0
7FFFh
PIC12(L)F1571/2
3.2.1
3.2.1.2
EXAMPLE 3-1:
There are two methods of accessing constants in program memory. The first method is to use tables of
RETLW instructions. The second method is to set an
FSR to point to the program memory.
3.2.1.1
RETLW Instruction
constants
BRW
RETLW
RETLW
RETLW
RETLW
DATA0
DATA1
DATA2
DATA3
RETLW INSTRUCTION
;Add Index in W to
;program counter to
;select data
;Index0 data
;Index1 data
my_function
; LOTS OF CODE
MOVLW
DATA_INDEX
call constants
; THE CONSTANT IS IN W
EXAMPLE 3-2:
ACCESSING PROGRAM
MEMORY VIA FSR
constants
DW
DATA0
;First constant
DW
DATA1
;Second constant
DW
DATA2
DW
DATA3
my_function
; LOTS OF CODE
MOVLW DATA_INDEX
ADDLW LOW constants
MOVWF FSR1L
MOVLW HIGH constants ;MSb is set
automatically
MOVWF FSR1H
BTFSC STATUS,C
;carry from ADDLW?
INCF
FSR1H,f
;yes
MOVIW 0[FSR1]
;THE PROGRAM MEMORY IS IN W
DS40001723D-page 17
PIC12(L)F1571/2
3.3
12 Core Registers
20 Special Function Registers (SFR)
Up to 80 bytes of General Purpose RAM (GPR)
16 bytes of Common RAM
DS40001723D-page 18
3.3.1
CORE REGISTERS
TABLE 3-2:
CORE REGISTERS
Addresses
BANKx
x00h or x80h
x01h or x81h
x02h or x82h
x03h or x83h
x04h or x84h
x05h or x85h
x06h or x86h
x07h or x87h
x08h or x88h
x09h or x89h
x0Ah or x8Ah
x0Bh or x8Bh
INDF0
INDF1
PCL
STATUS
FSR0L
FSR0H
FSR1L
FSR1H
BSR
WREG
PCLATH
INTCON
PIC12(L)F1571/2
3.3.1.1
STATUS Register
REGISTER 3-1:
U-0
U-0
U-0
R-1/q
R-1/q
R/W-0/u
R/W-0/u
R/W-0/u
TO
PD
DC(1)
C(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Z: Zero bit
1 = The result of an arithmetic or logic operation is zero
0 = The result of an arithmetic or logic operation is not zero
bit 1
DC: Digit Carry/Digit Borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1)
1 = A carry-out from the 4th low-order bit of the result occurred
0 = No carry-out from the 4th low-order bit of the result
bit 0
Note 1:
For Borrow, the polarity is reversed. A subtraction is executed by adding the twos complement of the
second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high-order or low-order
bit of the source register.
DS40001723D-page 19
PIC12(L)F1571/2
3.3.2
3.3.3
3.3.3.1
FIGURE 3-3:
BANKED MEMORY
PARTITIONING
Rev. 10-000041A
7/30/2013
Core Registers
(12 bytes)
0Bh
0Ch
Special Function Registers
(20 bytes maximum)
1Fh
20h
3.3.4
Memory Region
COMMON RAM
3.3.5
6Fh
70h
Common RAM
(16 bytes)
7Fh
DS40001723D-page 20
TABLE 3-3:
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
INLVLA
00Dh
08Dh
10Dh
18Dh
20Dh
28Dh
30Dh
38Dh
00Eh
08Eh
10Eh
18Eh
20Eh
28Eh
30Eh
38Eh
00Fh
08Fh
10Fh
18Fh
20Fh
28Fh
30Fh
38Fh
010h
090h
110h
190h
210h
290h
310h
390h
011h
PIR1
091h
PIE1
111h
CM1CON0
191h
PMADRL
211h
291h
311h
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1CON1
192h
PMADRH
212h
292h
312h
392h
IOCAN
013h
PIR3
093h
PIE3
113h
193h
PMDATL
213h
293h
313h
393h
IOCAF
014h
094h
114h
194h
PMDATH
214h
294h
314h
394h
015h
TMR0
095h
OPTION_REG
115h
CMOUT
195h
PMCON1
215h
295h
315h
395h
016h
TMR1L
096h
PCON
116h
BORCON
196h
PMCON2
216h
296h
316h
396h
017h
TMR1H
097h
WDTCON
117h
FVRCON
197h
VREGCON(1)
217h
297h
317h
397h
018h
T1CON
098h
OSCTUN E
118h
DACxCON0
198h
218h
298h
318h
398h
019h
T1GCON
099h
OSCCON
119h
DACxCON1
199h
219h
299h
319h
399h
01Ah
TMR2
09Ah
OSCSTAT
11Ah
19Ah
21Ah
29Ah
31Ah
39Ah
01Bh
PR2
09Bh
ADRESL
11Bh
19Bh
21Bh
29Bh
31Bh
39Bh
01Ch
T2CON
09Ch
ADRESH
11Ch
19Ch
21Ch
29Ch
31Ch
39Ch
01Dh
09Dh
ADCON0
11Dh
APFCON
19Dh
21Dh
29Dh
31Dh
39Dh
01Eh
09Eh
ADCON1
11Eh
19Eh
21Eh
29Eh
31Eh
39Eh
01Fh
09Fh
ADCON2
11Fh
19Fh
21Fh
29Fh
31Fh
39Fh
020h
0C0h
06Fh
0EFh
070h
0F0h
Common RAM
DS40001723D-page 21
07Fh
0FFh
Unimplemented
Read as 0
Common RAM
(Accesses
70h-7Fh)
120h
1A0h
Unimplemented
Read as 0
16Fh
170h
17Fh
220h
Unimplemented
Read as 0
1EFh
1F0h
Common RAM
(Accesses
70h-7Fh)
Legend:
= Unimplemented data memory locations, read as 0.
Note 1: PIC12F1571 only.
1FFh
2A0h
Unimplemented
Read as 0
26Fh
270h
Common RAM
(Accesses
70h-7Fh)
27Fh
320h
Unimplemented
Read as 0
2FFh
Unimplemented
Read as 0
36Fh
2EFh
2F0h
Common RAM
(Accesses
70h-7Fh)
3A0h
3EFh
370h
Common RAM
(Accesses
70h-7Fh)
37Fh
Unimplemented
Read as 0
3F0h
Common RAM
(Accesses
70h-7Fh)
3FFh
Common RAM
(Accesses
70h-7Fh)
PIC12(L)F1571/2
General
Purpose
Register
80 Bytes
BANK 0
000h
BANK 1
080h
Core Registers
(Table 3-2)
00Bh
BANK 2
100h
Core Registers
(Table 3-2)
08Bh
BANK 3
180h
Core Registers
(Table 3-2)
10Bh
BANK 4
200h
Core Registers
(Table 3-2)
18Bh
BANK 5
280h
Core Registers
(Table 3-2)
20Bh
BANK 6
300h
Core Registers
(Table 3-2)
28Bh
BANK 7
380h
Core Registers
(Table 3-2)
30Bh
Core Registers
(Table 3-2)
38Bh
00Ch
PORTA
08Ch
TRISA
10Ch
LATA
18Ch
ANSELA
20Ch
WPUA
28Ch
ODCONA
30Ch
SLRCONA
38Ch
INLVLA
00Dh
08Dh
10Dh
18Dh
20Dh
28Dh
30Dh
38Dh
00Eh
08Eh
10Eh
18Eh
20Eh
28Eh
30Eh
38Eh
00Fh
08Fh
10Fh
18Fh
20Fh
28Fh
30Fh
38Fh
010h
090h
110h
190h
210h
290h
310h
390h
011h
PIR1
091h
PIE1
111h
CM1CON0
191h
PMADRL
211h
291h
311h
391h
IOCAP
012h
PIR2
092h
PIE2
112h
CM1CON1
192h
PMADRH
212h
292h
312h
392h
IOCAN
013h
PIR3
093h
PIE3
113h
193h
PMDATL
213h
293h
313h
393h
IOCAF
014h
094h
114h
194h
PMDATH
214h
294h
314h
394h
015h
TMR0
095h
OPTION_REG
115h
CMOUT
195h
PMCON1
215h
295h
315h
395h
016h
TMR1L
096h
PCON
116h
BORCON
196h
PMCON2
216h
296h
316h
396h
017h
TMR1H
097h
WDTCON
117h
FVRCON
197h
VREGCON(1)
217h
297h
317h
397h
018h
T1CON
098h
OSCTUNE
118h
DAC1CON0
198h
218h
298h
318h
398h
019h
T1GCON
099h
OSCCON
119h
DAC1CON1
199h
RCREG
219h
299h
319h
399h
01Ah
TMR2
09Ah
OSCSTAT
11Ah
19Ah
TXREG
21Ah
29Ah
31Ah
39Ah
01Bh
PR2
09Bh
ADRESL
11Bh
19Bh
SPBRG
21Bh
29Bh
31Bh
39Bh
01Ch
T2CON
09Ch
ADRESH
11Ch
19Ch
SPBRGH
21Ch
29Ch
31Ch
39Ch
01Dh
09Dh
ADCON0
11Dh
APFCON
19Dh
RCSTA
21Dh
29Dh
31Dh
39Dh
01Eh
09Eh
ADCON1
11Eh
19Eh
TXSTA
21Eh
29Eh
31Eh
39Eh
01Fh
09Fh
0A0h
ADCON2
11Fh
19Fh
BAUDCON
21Fh
29Fh
31Fh
39Fh
020h
General
Purpose
Register
80 Bytes
06Fh
General
Purpose
Register
80 Bytes
0EFh
0F0h
070h
0FFh
220h
1A0h
General
Purpose
Register
80 Bytes
16Fh
170h
Accesses
70h-7Fh
Common RAM
07Fh
120h
Unimplemented
Read as 0
1EFh
1F0h
Accesses
70h-7Fh
17Fh
Legend:
= Unimplemented data memory locations, read as 0.
Note 1: PIC12F1572 only.
Unimplemented
Read as 0
26Fh
270h
Accesses
70h-7Fh
1FFh
2A0h
Unimplemented
Read as 0
Unimplemented
Read as 0
Unimplemented
Read as 0
3EFh
370h
Accesses
70h-7Fh
2FFh
3A0h
36Fh
2EFh
2F0h
Accesses
70h-7Fh
27Fh
320h
3F0h
Accesses
70h-7Fh
37Fh
Accesses
70h-7Fh
3FFh
PIC12(L)F1571/2
DS40001723D-page 22
TABLE 3-4:
TABLE 3-5:
BANK 8
400h
40Bh
40Ch
40Dh
40Eh
40Fh
410h
411h
412h
413h
414h
415h
416h
417h
418h
419h
41Ah
41Bh
41Ch
41Dh
41Eh
41Fh
420h
Core Registers
(Table 3-2)
BANK 9
480h
48Bh
48Ch
48Dh
48Eh
48Fh
490h
491h
492h
493h
494h
495h
496h
497h
498h
499h
49Ah
49Bh
49Ch
49Dh
49Eh
49Fh
4A0h
Unimplemented
Read as 0
46Fh
470h
Core Registers
(Table 3-2)
56Fh
570h
4FFh
DS40001723D-page 23
80Bh
80Ch
88Bh
88Ch
Unimplemented
Read as 0
86Fh
870h
Unimplemented
Read as 0
8EFh
8F0h
Accesses
70h-7Fh
87Fh
Legend:
96Fh
970h
Accesses
70h-7Fh
8FFh
9EFh
9F0h
Accesses
70h-7Fh
97Fh
Accesses
70h-7Fh
9FFh
A7Fh
AFFh
7FFh
BANK 23
B80h
Core Registers
(Table 3-2)
B0Bh
B0Ch
Core Registers
(Table 3-2)
B8Bh
B8Ch
Unimplemented
Read as 0
B6Fh
B70h
Accesses
70h-7Fh
Unimplemented
Read as 0
BEFh
BF0h
Accesses
70h-7Fh
B7Fh
Accesses
70h-7Fh
BANK 22
Unimplemented
Read as 0
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h-7Fh
Core Registers
(Table 3-2)
Accesses
70h-7Fh
78Bh
78Ch
78Dh
78Eh
78Fh
790h
791h
792h
793h
794h
795h
796h
797h
798h
799h
79Ah
79Bh
79Ch
79Dh
79Eh
79Fh
7A0h
7EFh
7F0h
B00h
AEFh
AF0h
BANK 15
780h
Unimplemented
Read as 0
BANK 21
A8Bh
A8Ch
A6Fh
A70h
77Fh
A80h
Unimplemented
Read as 0
Core Registers
(Table 3-2)
76Fh
770h
6FFh
A0Bh
A0Ch
70Bh
70Ch
70Dh
70Eh
70Fh
710h
711h
712h
713h
714h
715h
716h
717h
718h
719h
71Ah
71Bh
71Ch
71Dh
71Eh
71Fh
720h
Accesses
70h-7Fh
Core Registers
(Table 3-2)
Unimplemented
Read as 0
CWG1DBR
CWG1DBF
CWG1CON0
CWG1CON1
CWG1CON2
BANK 14
700h
Unimplemented
Read as 0
BANK 20
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
6EFh
6F0h
A00h
98Bh
98Ch
68Bh
68Ch
68Dh
68Eh
68Fh
690h
691h
692h
693h
694h
695h
696h
697h
698h
699h
69Ah
69Bh
69Ch
69Dh
69Eh
69Fh
6A0h
Accesses
70h-7Fh
BANK 19
Unimplemented
Read as 0
67Fh
980h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
BANK 13
680h
Unimplemented
Read as 0
Accesses
70h-7Fh
BANK 18
90Bh
90Ch
60Bh
60Ch
60Dh
60Eh
60Fh
610h
611h
612h
613h
614h
615h
616h
617h
618h
619h
61Ah
61Bh
61Ch
61Dh
61Eh
61Fh
620h
66Fh
670h
5FFh
900h
Core Registers
(Table 3-2)
BANK 12
600h
Unimplemented
Read as 0
Accesses
70h-7Fh
BANK 17
Core Registers
(Table 3-2)
5EFh
5F0h
57Fh
880h
Core Registers
(Table 3-2 )
58Bh
58Ch
58Dh
58Eh
58Fh
590h
591h
592h
593h
594h
595h
596h
597h
598h
599h
59Ah
59Bh
59Ch
59Dh
59Eh
59Fh
5A0h
Unimplemented
Read as 0
Accesses
70h-7Fh
BANK 16
Core Registers
(Table 3-2)
BANK 11
580h
Accesses
70h-7Fh
BFFh
PIC12(L)F1571/2
Accesses
70h-7Fh
800h
50Bh
50Ch
50Dh
50Eh
50Fh
510h
511h
512h
513h
514h
515h
516h
517h
518h
519h
51Ah
51Bh
51Ch
51Dh
51Eh
51Fh
520h
Unimplemented
Read as 0
4EFh
4F0h
47Fh
BANK 10
500h
BANK 24
C00h
BANK 25
Core Registers
(Table 3-2)
C0Bh
C0Ch
C0Dh
C0Eh
C0Fh
C10h
C11h
C12h
C13h
C14h
C15h
C16h
C17h
C18h
C19h
C1Ah
C1Bh
C1Ch
C1Dh
C1Eh
C1Fh
C20h
Core Registers
(Table 3-2)
C8Bh
C8Ch
C8Dh
C8Eh
C8Fh
C90h
C91h
C92h
C93h
C94h
C95h
C96h
C97h
C98h
C99h
C9Ah
C9Bh
C9Ch
C9Dh
C9Eh
C9Fh
CA0h
Unimplemented
Read as 0
C6Fh
C70h
Legend:
CEFh
CF0h
D0Bh
D0Ch
D0Dh
D0Eh
D0Fh
D10h
D11h
D12h
D13h
D14h
D15h
D16h
D17h
D18h
D19h
D1Ah
D1Bh
D1Ch
D1Dh
D1Eh
D1Fh
D20h
BANK 28
E00h
D8Bh
D8Ch
D6Fh
D70h
E0Bh
E0Ch
E0Dh
E0Eh
E0Fh
E10h
E11h
E12h
E13h
E14h
E15h
E16h
E17h
See Table 3-7 for E18h
Register Mapping
E19h
Details
E1Ah
E1Bh
E1Ch
E1Dh
E1Eh
E1Fh
E20h
Accesses
70h-7Fh
E6Fh
E70h
Accesses
70h-7Fh
DFFh
E8Bh
E8Ch
E8Dh
E8Eh
E8Fh
E90h
E91h
E92h
E93h
E94h
E95h
E96h
E97h
E98h
E99h
E9Ah
E9Bh
E9Ch
E9Dh
E9Eh
E9Fh
EA0h
EEFh
EF0h
F0Bh
F0Ch
F0Dh
F0Eh
F0Fh
F10h
F11h
F12h
F13h
F14h
F15h
F16h
F17h
F18h
F19h
F1Ah
F1Bh
F1Ch
F1Dh
F1Eh
F1Fh
F20h
Core Registers
(Table 3-2)
F8Bh
F8Ch
Unimplemented
Read as 0
F6Fh
F70h
Accesses
70h-7Fh
EFFh
BANK 31
F80h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h-7Fh
E7Fh
BANK 30
F00h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
DEFh
DF0h
D7Fh
BANK 29
E80h
Core Registers
(Table 3-2)
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h-7Fh
CFFh
BANK 27
D80h
Core Registers
(Table 3-2)
Unimplemented
Read as 0
Accesses
70h-7Fh
CFFh
BANK 26
D00h
C80h
FEFh
FF0h
Accesses
70h-7Fh
F7Fh
Accesses
70h-7Fh
FFFh
PIC12(L)F1571/2
DS40001723D-page 24
TABLE 3-6:
PIC12(L)F1571/2
TABLE 3-7:
PIC12(L)F1571/2 MEMORY
MAP, BANK 27
TABLE 3-8:
PIC12(L)F1571/2 MEMORY
MAP, BANK 31
Bank 31
D8Ch
D8Dh
D8Eh
D8Fh
D90h
D91h
D92h
D93h
D94h
D95h
D96h
D97h
D98h
D99h
D9Ah
D9Bh
D9Ch
D9Dh
D9Eh
D9Fh
DA0h
DA1h
DA2h
DA3h
DA4h
DA5h
DA6h
DA7h
DA8h
DA9h
DAAh
DABh
DACh
DADh
DAEh
DAFh
DB0h
DB1h
DB2h
DB3h
DB4h
DB5h
DB6h
DB7h
DB8h
DB9h
DBAh
DBBh
DBCh
DBDh
DBEh
DBFh
DC0h
PWMEN
PWMLD
PWMOUT
PWM1PHL
PWM1PHH
PWM1DCL
PWM1DCH
PWM1PRL
PWM1PRH
PWM1OFL
PWM1OFH
PWM1TMRL
PWM1TMRH
PWM1CON
PWM1INTE
PWM1INTF
PWM1CLKCON
PWM1LDCON
PWM1OFCON
PWM2PHL
PWM2PHH
PWM2DCL
PWM2DCH
PWM2PRL
PWM2PRH
PWM2OFL
PWM2OFH
PWM2TMRL
PWM2TMRH
PWM2CON
PWM2INTE
PWM2INTF
PWM2CLKCON
PWM2LDCON
PWM2OFCON
PWM3PHL
PWM3PHH
PWM3DCL
PWM3DCH
PWM2PRL
PWM3PRH
PWM3OFL
PWM3OFH
PWM3TMRL
PWM3TMRH
PWM3CON
PWM3INTE
PWM3INTF
PWM3CLKCON
PWM3LDCON
PWM3OFCON
Bank 31
F8Ch
Unimplemented
Read as 0
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
Legend:
STATUS_SHAD
WREG_SHAD
BSR_SHAD
PCLATH_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
STKPTR
TOSL
TOSH
DC1h
DEFh
Legend:
DS40001723D-page 25
PIC12(L)F1571/2
3.3.6
TABLE 3-9:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on All
Other Resets
Bank 0-31
x00h or
INDF0
x80h
xxxx xxxx
uuuu uuuu
x01h or
INDF1
x81h
xxxx xxxx
uuuu uuuu
x02h or
PCL
x82h
0000 0000
0000 0000
---1 1000
---q quuu
x03h or
STATUS
x83h
TO
PD
DC
x04h or
FSR0L
x84h
0000 0000
uuuu uuuu
x05h or
FSR0H
x85h
0000 0000
0000 0000
x06h or
FSR1L
x86h
0000 0000
uuuu uuuu
x07h or
FSR1H
x87h
0000 0000
0000 0000
---0 0000
---0 0000
0000 0000
uuuu uuuu
-000 0000
-000 0000
0000 0000
0000 0000
x08h or
BSR
x88h
x09h or
WREG
x89h
BSR<4:0>
Working Register
x0Ah or
PCLATH
x8Ah
x0Bh or
INTCON
x8Bh
GIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
DS40001723D-page 26
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 0
00Ch
PORTA
RA<5:0>
00Dh
Unimplemented
00Eh
Unimplemented
00Fh
Unimplemented
010h
Unimplemented
011h
PIR1
TMR1GIF
012h
PIR2
013h
PIR3
PWM3IF
014h
RCIF(2)
ADIF
TXIF(2)
TMR2IF
TMR1IF
C1IF
PWM2IF
PWM1IF
Unimplemented
015h
TMR0
016h
TMR1L
Holding Register for the Least Significant Byte of the 16-Bit TMR1 Count
017h
TMR1H
Holding Register for the Most Significant Byte of the 16-Bit TMR1 Count
018h
T1CON
019h
T1GCON
TMR1CS<1:0>
TMR1GE
T1CKPS<1:0>
T1GPOL
01Ah
TMR2
01Bh
PR2
01Ch
T2CON
T1GTM
T1GSPM
T1SYNC
T1GGO/
DONE
T1GVAL
TMR1ON
T1GSS<1:0>
T2OUTPS<3:0>
TMR2ON
T2CKPS<1:0>
01Dh
Unimplemented
01Eh
Unimplemented
01Fh
Unimplemented
Bank 1
08Ch
TRISA
TRISA<5:4>
(2)
TRISA<2:0>
08Dh
Unimplemented
08Eh
Unimplemented
08Fh
Unimplemented
090h
Unimplemented
091h
PIE1
TMR1GIE
092h
PIE2
093h
PIE3
PWM3IE
RCIE(2)
ADIE
TXIE(2)
TMR2IE
TMR1IE
C1IE
PWM2IE
PWM1IE
PSA
094h
095h
OPTION_REG
WPUEN
INTEDG
TMR0CS
TMR0SE
096h
PCON
STKOVF
STKUNF
RWDT
097h
WDTCON
098h
OSCTUNE
099h
OSCCON
SPLLEN
09Ah
OSCSTAT
09Bh
ADRESL
09Ch
ADRESH
09Dh
ADCON0
09Eh
ADCON1
ADFM
09Fh
ADCON2
Legend:
Note 1:
2:
3:
Unimplemented
PS<2:0>
RMCLR
RI
POR
WDTPS<4:0>
BOR
SWDTEN
TUN<5:0>
IRCF<3:0>
PLLR
OSTS
HFIOFR
MFIOFR
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
HFIOFL
SCS<1:0>
LFIOFR
GO/DONE
HFIOFS
ADON
ADPREF<1:0>
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 27
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 2
10Ch
LATA
LATA<5:4>
LATA<2:0>
10Dh
Unimplemented
10Eh
Unimplemented
10Fh
Unimplemented
110h
Unimplemented
111h
CM1CON0
112h
CM1CON1
C1ON
C1OUT
C1INTP
C1INTN
C1OE
C1POL
C1PCH<1:0>
C1SP
C1HYS
C1SYNC
C1NCH<2:0>
113h
Unimplemented
114h
Unimplemented
115h
CMOUT
MC1OUT
BORRDY
116h
BORCON
SBOREN
BORFS
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
118h
DAC1CON0
DACEN
DACOE
DACPSS<1:0>
119h
DAC1CON1
11Ah
to
11Ch
ADFVR<1:0>
DACR<4:0>
Unimplemented
11Dh
APFCON
11Eh
Unimplemented
11Fh
Unimplemented
T1GSEL
TXCKSEL
P2SEL
P1SEL
Bank 3
18Ch
ANSELA
18Dh
Unimplemented
18Eh
Unimplemented
18Fh
Unimplemented
190h
Unimplemented
191h
PMADRL
192h
PMADRH
193h
PMDATL
194h
PMDATH
195h
PMCON1
(3)
CFGS
196h
PMCON2
197h
VREGCON(1)
198h
ANSA4
ANSA<2:0>
FREE
WRERR
WREN
WR
RD
VREGPM
Reserved
Unimplemented
199h
RCREG
19Ah
TXREG
19Bh
SPBRGL
19Ch
SPBRGH
19Dh
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
19Eh
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
19Fh
BAUDCON
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
Legend:
Note 1:
2:
3:
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 28
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 4
20Ch
WPUA
WPUA<5:0>
20Dh
Unimplemented
20Eh
to
21Fh
Unimplemented
Bank 5
28Ch
ODCONA
28Dh
to
29Fh
ODA<5:4>
ODA<2:0>
Unimplemented
Bank 6
30Ch
SLRCONA
30Dh
to
31Fh
SLRA<5:4>
SLRA<2:0>
Unimplemented
Bank 7
38Ch
INLVLA
38Dh
to
390h
INLVLA<5:0>
Unimplemented
391h
IOCAP
IOCAP<5:0>
392h
IOCAN
IOCAN<5:0>
393h
IOCAF
IOCAF<5:0>
394h
to
39Fh
Unimplemented
Unimplemented
Unimplemented
Bank 8
40Ch
to
41Fh
Bank 9
48Ch
to
49Fh
Legend:
Note 1:
2:
3:
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 29
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 10
50Ch
to
51Fh
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Bank 11
58Ch
to
59Fh
Bank 12
60Ch
to
61Fh
Bank 13
68Ch
to
690h
691h
CWG1DBR
CWG1DBR<5:0>
692h
CWG1DBF
CWG1DBF<5:0>
693h
CWG1CON0
G1EN
G1OEB
694h
CWG1CON1
695h
CWG1CON2
696h
to
69Fh
G1ASDLB<1:0>
G1ASE
G1ARSEN
G1OEA
G1POLB
G1POLA
G1ASDLA<1:0>
G1CS0
G1IS<2:0>
G1ASDSC1
G1ASDSFLT
Unimplemented
Unimplemented
Banks 14-26
x0Ch/
x8Ch
x1Fh/
x9Fh
Legend:
Note 1:
2:
3:
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 30
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 27
D8Ch
Unimplemented
D8Dh
Unimplemented
D8Eh
PWMEN
D8Fh
PWMLD
D90h
PWMOUT
D91h
PWM1PHL
PH<7:0>
D92h
PWM1PHH
PH<15:8>
D93h
PWM1DCL
DC<7:0>
D94h
PWM1DCH
DC<15:8>
D95h
PWM1PRL
PR<7:0>
D96h
PWM1PRH
PR<15:8>
D97h
PWM1OFL
OF<7:0>
D98h
PWM1OFH
OF<15:8>
D99h
PWM1TMRL
TMR<7:0>
D9Ah
PWM1TMRH
TMR<15:8>
D9Bh
PWM1CON
PWM1EN
D9Ch
PWM1INTE
PWM1OFIE
D9Dh
PWM1INTF
D9Eh
PWM1CLKCON
PWM2EN_A
PWM1MODE<1:0>
PWM1PHIE
PWM1DCIE
PWM1PRIE
---- 000
---- 000
PWM1OFIF
PWM1PHIF
PWM1DCIF
PWM1PRIF
---- 000
---- 000
PWM1OFO
PWM1PS<2:0>
PWM1LDA PWM1LDT
PWM3EN_A
PWM1CS<1:0>
PWM1LDS<1:0>
PWM1OFS<1:0>
D9Fh
PWM1LDCON
DA0h
PWM1OFCON
DA1h
PWM2PHL
PH<7:0>
DA2h
PWM2PHH
PH<15:8>
DA3h
PWM2DCL
DC<7:0>
DA4h
PWM2DCH
DC<15:8>
DA5h
PWM2PRL
PR<7:0>
DA6h
PWM2PRH
PR<15:8>
DA7h
PWM2OFL
OF<7:0>
DA8h
PWM2OFH
OF<15:8>
DA9h
PWM2TMRL
TMR<7:0>
DAAh PWM2TMRH
TMR<15:8>
PWM1OFM<1:0>
DABh PWM2CON
PWM2EN
DACh PWM2INTE
PWM2OFIE
DADh PWM2INTF
DAEh PWM2CLKCON
DAFh
PWM2LDCON
Legend:
Note 1:
2:
3:
PWM2PS<2:0>
PWM2LDA PWM2LDT
PWM2MODE<1:0>
PWM2PHIE
PWM2DCIE
PWM2PRIE
---- 000
---- 000
PWM2OFIF
PWM2PHIF
PWM2DCIF
PWM2PRIF
---- 000
---- 000
PWM2CS<1:0>
PWM2LDS<1:0>
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 31
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 27 (Continued)
DB0h
PWM2OFCON
DB1h
PWM3PHL
PWM2OFM<1:0>
PWM2OFO
PH<7:0>
DB2h
PWM3PHH
PH<15:8>
DB3h
PWM3DCL
DC<7:0>
DB4h
PWM3DCH
DC<15:8>
DB5h
PWM3PRL
PR<7:0>
DB6h
PWM3PRH
PR<15:8>
DB7h
PWM3OFL
OF<7:0>
DA8h
PWM3OFH
OF<15:8>
DA9h
PWM3TMRL
TMR<7:0>
DBAh PWM3TMRH
TMR<15:8>
DBBh PWM3CON
PWM3EN
DBCh PWM3INTE
PWM3OFIE
DBDh PWM3INTF
DBEh PWM3CLKCON
DBFh
PWM3LDCON
DC0h
PWM3OFCON
PWM3OFM<1:0>
PWM3PHIE
PWM3DCIE
PWM3PRIE
---- 000
---- 000
PWM3OFIF
PWM3PHIF
PWM3DCIF
PWM3PRIF
---- 000
---- 000
PWM3OFO
PWM3PS<2:0>
PWM3LDA PWM3LDT
PWM2OFS<1:0>
PWM3MODE<1:0>
PWM3CS<1:0>
PWM3LDS<1:0>
PWM3OFS<1:0>
Bank 28-30
58Ch
to
59Fh
Legend:
Note 1:
2:
3:
Unimplemented
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 32
PIC12(L)F1571/2
TABLE 3-10:
Addr
Name
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on
All Other
Resets
Bank 31
F8Ch
FE3h
FE4h
STATUS_
SHAD
FE5h
WREG_
SHAD
FE6h
BSR_
PCLATH_
SHAD
FE8h
FSR0L_
SHAD
FE9h
FSR0H_
SHAD
FEAh
FSR1L_
SHAD
FEBh
FSR1H_
SHAD
FECh
FEDh
STKPTR
FEEh
TOSL
FEFh
TOSH
Legend:
Note 1:
2:
3:
Z_SHAD
SHAD
FE7h
Unimplemented
DC_SHAD
C_SHAD
Unimplemented
x = unknown; u = unchanged; q = value depends on condition; = unimplemented; r = reserved. Shaded locations are unimplemented, read as 0.
PIC12F1571/2 only.
PIC12(L)F1572 only.
Unimplemented, read as 1.
DS40001723D-page 33
PIC12(L)F1571/2
3.4
3.4.2
FIGURE 3-4:
LOADING OF PC IN
DIFFERENT SITUATIONS
Rev. 10-000042A
7/30/2013
14
PCH
PCL
PC
7
PCLATH
Instruction
with PCL as
Destination
ALU result
14
PCH
PCL
PC
6
PCLATH
GOTO,
CALL
11
OPCODE <10:0>
14
PCH
PCL
PC
6
PCLATH
14
PCH
CALLW
8
W
PCL
PCL
PC
BRW
15
PC + W
14
PCH
PC
BRA
15
PC + OPCODE <8:0>
3.4.1
COMPUTED GOTO
3.4.3
3.4.4
BRANCHING
MODIFYING PCL
DS40001723D-page 34
PIC12(L)F1571/2
3.5
Stack
3.5.1
FIGURE 3-5:
TOSH:TOSL
0x0F
STKPTR = 0x1F
0x0E
0x0D
0x0C
0x0B
0x0A
After Reset, the stack is empty. The
empty stack is initialized so the Stack
Pointer is pointing at 0x1F. If the Stack
Overflow/Underflow Reset is enabled, the
TOSH/TOSL register will return 0. If the
Stack Overflow/Underflow Reset is
disabled, the TOSH/TOSL register will
return the contents of stack address
0x0F.
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
0x1F
0x0000
STKPTR = 0x1F
DS40001723D-page 35
PIC12(L)F1571/2
FIGURE 3-6:
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
This figure shows the stack configuration
after the first CALL or a single interrupt.
If a RETURN instruction is executed, the
return address will be placed in the
Program Counter and the Stack Pointer
decremented to the empty state (0x1F).
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
TOSH:TOSL
FIGURE 3-7:
Return Address
STKPTR = 0x00
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
TOSH:TOSL
DS40001723D-page 36
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
STKPTR = 0x06
PIC12(L)F1571/2
FIGURE 3-8:
Rev. 10-000043D
7/30/2013
TOSH:TOSL
3.5.2
0x0F
Return Address
0x0E
Return Address
0x0D
Return Address
0x0C
Return Address
0x0B
Return Address
0x0A
Return Address
0x09
Return Address
0x08
Return Address
0x07
Return Address
0x06
Return Address
0x05
Return Address
0x04
Return Address
0x03
Return Address
0x02
Return Address
0x01
Return Address
0x00
Return Address
OVERFLOW/UNDERFLOW RESET
3.6
STKPTR = 0x10
Indirect Addressing
DS40001723D-page 37
PIC12(L)F1571/2
FIGURE 3-9:
INDIRECT ADDRESSING
Rev. 10-000044A
7/30/2013
0x0000
0x0000
Traditional
Data Memory
0x0FFF
0x1000
0x0FFF
Reserved
0x1FFF
0x2000
Linear
Data Memory
0x29AF
0x29B0
Reserved
FSR
Address
Range
0x7FFF
0x8000
0x0000
Program
Flash Memory
0xFFFF
Note:
0x7FFF
Not all memory regions are completely implemented. Consult device memory tables for memory limits.
DS40001723D-page 38
PIC12(L)F1571/2
3.6.1
FIGURE 3-10:
Rev. 10-000056A
7/31/2013
Direct Addressing
4 BSR 0
Indirect Addressing
From Opcode
6
0
Bank Select
7
FSRxH
0 0 0 0
Location Select
0x00
00000
Bank Select
00001
00010
11111
Bank 0 Bank 1
Bank 2
Bank 31
0 7
FSRxL
Location Select
0x7F
DS40001723D-page 39
PIC12(L)F1571/2
3.6.2
FIGURE 3-11:
3.6.3
FIGURE 3-12:
PROGRAM FLASH
MEMORY MAP
Rev. 10-000057A
7/31/2013
7
FSRnH
0 0 1
Location Select
FSRnL
Rev. 10-000058A
7/31/2013
7
1
FSRnH
Location Select
0x2000
FSRnL
0x8000
0x020
Bank 0
0x06F
0x0A0
Bank 1
0x0EF
Program
Flash
Memory
(low 8 bits)
0x120
Bank 2
0x16F
0x29AF
DS40001723D-page 40
0xF20
Bank 30
0xF6F
0x0000
0xFFFF
0x7FFF
PIC12(L)F1571/2
4.0
DEVICE CONFIGURATION
4.1
Configuration Words
Note:
DS40001723D-page 41
PIC12(L)F1571/2
4.2
REGISTER 4-1:
U-1
R/P-1
CLKOUTEN
R/P-1
R/P-1
BOREN<1:0>
U-1
(1)
bit 13
R/P-1
(2)
CP
R/P-1
MCLRE
bit 8
R/P-1
PWRTE
R/P-1
(1)
R/P-1
WDTE<1:0>
U-1
R/P-1
R/P-1
FOSC<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13-12
Unimplemented: Read as 1
bit 11
bit 10-9
bit 8
Unimplemented: Read as 1
bit 7
bit 6
bit 5
bit 4-3
bit 2
Unimplemented: Read as 1
bit 1-0
Note 1:
2:
Enabling Brown-out Reset does not automatically enable the Power-up Timer.
Once enabled, code-protect can only be disabled by bulk erasing the device.
DS40001723D-page 42
PIC12(L)F1571/2
REGISTER 4-2:
LVP
R/P-1
DEBUG
R/P-1
(2)
LPBOREN
R/P-1
(3)
BORV
R/P-1
R/P-1
STVREN
PLLEN
bit 13
bit 8
U-1
U-1
U-1
U-1
U-1
U-1
R/P-1
R/P-1
WRT<1:0>
bit 7
bit 0
Legend:
R = Readable bit
P = Programmable bit
0 = Bit is cleared
1 = Bit is set
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7-2
Unimplemented: Read as 1
bit 1-0
Note 1:
2:
3:
This bit cannot be programmed to 0 when programming mode is entered via LVP.
The DEBUG bit in Configuration Words is managed automatically by device development tools, including
debuggers and programmers. For normal device operation, this bit should be maintained as a 1.
See VBOR parameter for specific trip point voltages.
DS40001723D-page 43
PIC12(L)F1571/2
4.3
Code Protection
4.3.1
4.4
Write Protection
4.5
User ID
4.6
DS40001723D-page 44
PIC12(L)F1571/2
4.7
REGISTER 4-3:
DEV<13:8>
bit 13
R
bit 8
R
DEV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
0 = Bit is cleared
bit 13-0
x = Bit is unknown
1 = Bit is set
Note 1:
REGISTER 4-4:
REV<13:8>
bit 13
R
bit 8
R
REV<7:0>
bit 7
bit 0
Legend:
R = Readable bit
0 = Bit is cleared
bit 13-0
1 = Bit is set
x = Bit is unknown
Note 1:
TABLE 4-1:
DEVICE ID VALUES
DEVICE
Device ID
Revision ID
PIC12F1571
3051h
2xxxh
PIC12LF1571
3053h
2xxxh
PIC12F1572
3050h
2xxxh
PIC12LF1572
3052h
2xxxh
DS40001723D-page 45
PIC12(L)F1571/2
NOTES:
DS40001723D-page 46
PIC12(L)F1571/2
5.0
OSCILLATOR MODULE
5.1
Overview
1.
2.
3.
4.
DS40001723D-page 47
PIC12(L)F1571/2
SIMPLIFIED PIC MCU CLOCK SOURCE BLOCK DIAGRAM
FIGURE 5-1:
Rev. 10-000155A
10/11/2013
FOSC<1:0>
01
Reserved
CLKIN
INTOSC
PLLEN
FOSC(1)
00
4x PLL(2)
Sleep
to CPU and
Peripherals
1x
SPLLEN
2
16 MHz
SCS<1:0>
8 MHz
4 MHz
500 kHz
Oscillator
MFINTOSC(1)
2 MHz
Prescaler
HFPLL
16 MHz
HFINTOSC(1)
1 MHz
*500 kHz
*250 kHz
*125 kHz
62.5 kHz
*31.25 kHz
*31 kHz
Internal Oscillator
Block
4
IRCF<3:0>
31 kHz
Oscillator
600 kHz
Oscillator
LFINTOSC(1)
FRC(1)
Note 1:
2:
3:
DS40001723D-page 48
PIC12(L)F1571/2
5.2
5.2.1
5.2.1.1
EC Mode
FIGURE 5-2:
Clock from
Ext. System
FOSC/4 or
I/O(1)
Note 1:
CLKOUT
DS40001723D-page 49
PIC12(L)F1571/2
5.2.2
The device may be configured to use the internal oscillator block as the system clock by performing one of the
following actions:
Program the FOSC<1:0> bits in the Configuration
Words to select the INTOSC clock source, which
will be used as the default system clock upon a
device Reset.
Write the SCS<1:0> bits in the OSCCON register
to switch the system clock source to the internal
oscillator during run time. See
Section 5.3 Clock Switchingfor more
information.
In INTOSC mode, CLKIN is available for general
purpose I/O. CLKOUT is available for general purpose
I/O or CLKOUT.
The function of the OSC2/CLKOUT pin is determined
by the CLKOUTEN bit in the Configuration Words.
The internal oscillator block has two independent
oscillators and a dedicated Phase-Locked Loop,
HFPLL, that can produce one of three internal system
clock sources.
1.
2.
3.
5.2.2.1
HFINTOSC
5.2.2.2
MFINTOSC
DS40001723D-page 50
PIC12(L)F1571/2
5.2.2.3
5.2.2.4
LFINTOSC
5.2.2.5
FRC
5.2.2.6
DS40001723D-page 51
PIC12(L)F1571/2
5.2.2.7
DS40001723D-page 52
5.2.2.8
5.
6.
7.
PIC12(L)F1571/2
FIGURE 5-3:
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
Oscillator Delay(1)
2-Cycle Sync
Running
LFINTOSC
0
IRCF<3:0>
=0
System Clock
HFINTOSC/
MFINTOSC
HFINTOSC/
MFINTOSC
2-Cycle Sync
Running
LFINTOSC
0
IRCF <3:0>
=0
System Clock
LFINTOSC
HFINTOSC/MFINTOSC
LFINTOSC Turns Off unless WDT is Enabled
LFINTOSC
Oscillator
Delay(1)
HFINTOSC/
MFINTOSC
IRCF <3:0>
=0
2-Cycle Sync
Running
System Clock
Note 1:
DS40001723D-page 53
PIC12(L)F1571/2
5.3
Clock Switching
5.4
5.3.1
TABLE 5-1:
Switch From
Switch To
Frequency
Oscillator Delay
Sleep/POR
LFINTOSC(1)
MFINTOSC(1)
HFINTOSC(1)
31 kHz
31.25 kHz-500 kHz
31.25 kHz-16 MHz
Sleep/POR
EC(1)
DC 32 MHz
2 cycles
LFINTOSC
EC(1)
DC 32 MHz
1 cycle of each
MFINTOSC(1)
HFINTOSC(1)
2 s (approx.)
LFINTOSC(1)
31 kHz
1 cycle of each
PLL Inactive
PLL Active
16-32 MHz
2 ms (approx.)
Note 1:
2:
PLL inactive.
See Section 26.0 Electrical Specifications.
DS40001723D-page 54
PIC12(L)F1571/2
5.5
REGISTER 5-1:
R/W-0/0
R/W-1/1
SPLLEN
R/W-1/1
R/W-1/1
U-0
IRCF<3:0>
R/W-0/0
R/W-0/0
SCS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-3
bit 2
Unimplemented: Read as 0
bit 1-0
Note 1:
DS40001723D-page 55
PIC12(L)F1571/2
REGISTER 5-2:
U-0
R-0/q
R-q/q
R-0/q
R-0/q
R-q/q
R-0/q
R-0/q
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
q = Conditional bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001723D-page 56
PIC12(L)F1571/2
REGISTER 5-3:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
TUN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
111111 =
000000 = Oscillator module is running at the factory-calibrated frequency
000001 =
011110 =
011111 = Maximum frequency
TABLE 5-2:
Name
Bit 7
Bit 6
Bit 5
OSTS
OSCCON
SPLLEN
OSCSTAT
PLLR
OSCTUNE
T1CON
TMR1CS<1:0>
Bit 4
Bit 3
Bit 2
HFIOFL
MFIOFR
IRCF<3:0>
HFIOFR
Bit 1
Bit 0
SCS<1:0>
55
LFIOFR
HFIOFS
56
TMR1ON
167
TUN<5:0>
T1CKPS<1:0>
Register
on Page
57
T1SYNC
Legend: = unimplemented location, read as 0. Shaded cells are not used by clock sources.
TABLE 5-3:
Name
CONFIG1
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CLKOUTEN
13:8
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<1:0>
Register
on Page
42
Legend: = unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS40001723D-page 57
PIC12(L)F1571/2
NOTES:
DS40001723D-page 58
PIC12(L)F1571/2
6.0
RESETS
FIGURE 6-1:
MCLRE
VPP/MCLR
Sleep
WDT
Time-out
Device
Reset
Power-on
Reset
VDD
BOR
Active(1)
Brown-out
Reset
LPBOR
Reset
Note 1:
LFINTOSC
Power-up
Timer
PWRTE
DS40001723D-page 59
PIC12(L)F1571/2
6.1
6.2
The POR circuit holds the device in Reset until VDD has
reached an acceptable level for minimum operation.
Slow rising VDD, fast operating speeds or analog
performance may require greater than minimum VDD.
The PWRT, BOR or MCLR features can be used to
extend the start-up period until all device operation
conditions have been met.
6.1.1
TABLE 6-1:
BOREN<1:0>
SBOREN
Device Mode
BOR Mode
11
Active
10
Awake
Active
Sleep
Disabled
Active
Disabled
Disabled
01
00
Note 1:
In these specific cases, release of POR and wake-up from Sleep, there is no delay in start-up. The BOR
ready flag (BORRDY = 1) will be set before the CPU is ready to execute instructions because the BOR
circuit is forced on by the BOREN<1:0> bits.
DS40001723D-page 60
PIC12(L)F1571/2
6.2.1
BOR IS ALWAYS ON
6.2.3
6.2.2
FIGURE 6-2:
BROWN-OUT SITUATIONS
VDD
Internal
Reset
VBOR
TPWRT(1)
VDD
Internal
Reset
VBOR
< TPWRT
TPWRT(1)
VDD
Internal
Reset
Note 1:
VBOR
TPWRT(1)
DS40001723D-page 61
PIC12(L)F1571/2
6.3
REGISTER 6-1:
R/W-1/u
R/W-0/u
U-0
U-0
U-0
U-0
U-0
R-q/u
SBOREN
BORFS(1)
BORRDY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-1
Unimplemented: Read as 0
bit 0
Note 1:
DS40001723D-page 62
PIC12(L)F1571/2
6.4
6.4.1
ENABLING LPBOR
TABLE 6-2:
MCLR CONFIGURATION
MCLRE
LVP
MCLR
Disabled
Enabled
Enabled
6.5.1
MCLR ENABLED
6.5.2
6.7
RESET Instruction
6.8
6.9
MCLR
6.5
6.6
MCLR DISABLED
6.10
Power-up Timer
6.11
Start-up Sequence
DS40001723D-page 63
PIC12(L)F1571/2
FIGURE 6-3:
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Int. Oscillator
FOSC
Begin Execution
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Ext. Clock (EC)
FOSC
Begin Execution
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Osc Start-Up Timer
TOST
TOST
Ext. Oscillator
FOSC
Begin Execution
code
execution (1)
code
execution (1)
VDD
Internal POR
TPWRT
Power-up Timer
MCLR
Internal RESET
Osc Start-Up Timer
TOST
TOST
Ext. Oscillator
Int. Oscillator
FOSC
Begin Execution
Code execution begins 10 FOSC cycles after the FOSC clock is released.
DS40001723D-page 64
PIC12(L)F1571/2
6.12
TABLE 6-3:
RMCLR
RI
POR
BOR
TO
PD
Condition
Power-on Reset
Brown-out Reset
WDT Reset
TABLE 6-4:
STATUS
Register
PCON
Register
Power-on Reset
0000h
---1 1000
00-- 110x
0000h
---u uuuu
uu-- 0uuu
0000h
---1 0uuu
uu-- 0uuu
WDT Reset
0000h
---0 uuuu
uu-- uuuu
PC + 1
---0 0uuu
uu-- uuuu
Condition
Brown-out Reset
0000h
---1 1uuu
00-- 11u0
PC + 1(1)
---1 0uuu
uu-- uuuu
0000h
---u uuuu
uu-- u0uu
0000h
---u uuuu
1u-- uuuu
0000h
---u uuuu
u1-- uuuu
DS40001723D-page 65
PIC12(L)F1571/2
6.13
6.14
REGISTER 6-2:
R/W/HS-0/q R/W/HS-0/q
STKOVF
STKUNF
U-0
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-1/q
R/W/HC-q/u
R/W/HC-q/u
RWDT
RMCLR
RI
POR
BOR
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001723D-page 66
PIC12(L)F1571/2
TABLE 6-5:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
BORCON
SBOREN
BORFS
BORRDY
62
PCON
STKOVF
STKUNF
RWDT
RMCLR
RI
POR
BOR
66
STATUS
TO
PD
DC
WDTCON
WDTPS<4:0>
19
SWDTEN
89
Legend: = unimplemented bit, reads as 0. Shaded cells are not used by Resets.
Note 1: Other (non Power-up) Resets include MCLR Reset and Watchdog Timer Reset during normal operation.
TABLE 6-6:
Name
CONFIG1
CONFIG2
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CLKOUTEN
Bit 10/2
13:8
7:0
CP
13:8
LVP
DEBUG
LPBOR
BORV
7:0
MCLRE PWRTE
WDTE<1:0>
Bit 9/1
BOREN<1:0>
Bit 8/0
FOSC<1:0>
STVREN
PLLEN
WRT<1:0>
Register
on Page
42
43
Legend: = unimplemented location, read as 0. Shaded cells are not used by Resets.
DS40001723D-page 67
PIC12(L)F1571/2
NOTES:
DS40001723D-page 68
PIC12(L)F1571/2
7.0
INTERRUPTS
Operation
Interrupt Latency
Interrupts during Sleep
INT Pin
Automatic Context Saving
FIGURE 7-1:
INTERRUPT LOGIC
Rev. 10-000010A
1/13/2014
TMR0IF
TMR0IE
Peripheral Interrupts
(TMR1IF) PIR1<0>
(TMR1IE) PIE1<0>
Wake-up
(If in Sleep mode)
INTF
INTE
IOCIF
IOCIE
Interrupt
to CPU
PEIE
PIRn<7>
PIEn<7>
GIE
DS40001723D-page 69
PIC12(L)F1571/2
7.1
Operation
7.2
Interrupt Latency
DS40001723D-page 70
PIC12(L)F1571/2
FIGURE 7-2:
INTERRUPT LATENCY
Fosc
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKR
Interrupt Sampled
during Q1
Interrupt
GIE
PC
Execute
PC-1
PC
1-Cycle Instruction at PC
PC+1
0004h
0005h
NOP
NOP
Inst(0004h)
PC+1/FSR
ADDR
New PC/
PC+1
0004h
0005h
Inst(PC)
NOP
NOP
Inst(0004h)
FSR ADDR
PC+1
PC+2
0004h
0005h
INST(PC)
NOP
NOP
NOP
Inst(0004h)
Inst(0005h)
FSR ADDR
PC+1
0004h
0005h
INST(PC)
NOP
NOP
Inst(0004h)
Inst(PC)
Interrupt
GIE
PC
Execute
PC-1
PC
2-Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3-Cycle Instruction at PC
Interrupt
GIE
PC
Execute
PC-1
PC
3-Cycle Instruction at PC
PC+2
NOP
NOP
DS40001723D-page 71
PIC12(L)F1571/2
FIGURE 7-3:
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
Q1
Q2
Q3
Q4
FOSC
CLKOUT
(3)
INT Pin
(1)
(1)
INTF
Interrupt Latency(2)
(4)
GIE
INSTRUCTION FLOW
PC
PC
PC + 1
PC + 1
0004h
0005h
Instruction
Fetched
Inst (PC)
Inst (PC + 1)
Inst (0004h)
Inst (0005h)
Instruction
Executed
Inst (PC 1)
Inst (PC)
Forced NOP
Forced NOP
Inst (0004h)
Note 1:
2:
3:
4:
DS40001723D-page 72
PIC12(L)F1571/2
7.3
7.4
INT Pin
7.5
W register
STATUS register (except for TO and PD)
BSR register
FSR registers
PCLATH register
DS40001723D-page 73
PIC12(L)F1571/2
7.6
REGISTER 7-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
GIE(1)
PEIE(2)
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF(3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Interrupt Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
The IOCIF Flag bit is read-only and cleared when all the Interrupt-On-Change flags in the IOCxF registers
have been cleared by software.
DS40001723D-page 74
PIC12(L)F1571/2
REGISTER 7-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
R/W-0/0
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
2:
Note:
PIC12(L)F1572 only.
Bit PEIE of the INTCON register must be set to enable any peripheral interrupt.
DS40001723D-page 75
PIC12(L)F1571/2
REGISTER 7-3:
U-0
U-0
R/W-0/0
U-0
U-0
U-0
U-0
U-0
C1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4-0
Unimplemented: Read as 0
Note:
DS40001723D-page 76
PIC12(L)F1571/2
REGISTER 7-4:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
PWM3IE
PWM2IE
PWM1IE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3-0
Unimplemented: Read as 0
Note:
DS40001723D-page 77
PIC12(L)F1571/2
REGISTER 7-5:
R/W-0/0
TMR1GIF
R-0/0
ADIF
RCIF
(1)
R/W-0/0
TXIF
(1)
U-0
U-0
R/W-0/0
R/W-0/0
TMR2IF
TMR1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
Note:
PIC12(L)F1572 only.
DS40001723D-page 78
PIC12(L)F1571/2
REGISTER 7-6:
U-0
U-0
R/W-0/0
U-0
U-0
U-0
U-0
U-0
C1IF
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5
bit 4-0
Unimplemented: Read as 0
Note:
DS40001723D-page 79
PIC12(L)F1571/2
REGISTER 7-7:
U-0
R-0/0
R-0/0
R-0/0
U-0
U-0
U-0
U-0
PWM3IF(1)
PWM2IF(1)
PWM1IF(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6
bit 5
bit 4
bit 3-0
Unimplemented: Read as 0
Note 1:
2:
These bits are read-only. They must be cleared by addressing the Flag registers inside the module.
Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding
enable bit or the Global Enable bit, GIE, of the INTCON register. User software should ensure the
appropriate interrupt flag bits are clear prior to enabling an interrupt.
DS40001723D-page 80
PIC12(L)F1571/2
TABLE 7-1:
Name
INTCON
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
OPTION_REG WPUEN
PSA
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
C1IE
76
77
TMR2IF
TMR1IF
78
79
80
PIE1
TMR1GIE
PIE2
PIE3
PIR1
TMR1GIF
ADIF
RCIF(1)
PIR2
C1IF
PIR3
PWM3IF
PWM2IF
PWM1IF
TXIF
(1)
PS<2:0>
157
Legend: = unimplemented location, read as 0. Shaded cells are not used by interrupts.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 81
PIC12(L)F1571/2
NOTES:
DS40001723D-page 82
PIC12(L)F1571/2
8.0
2.
3.
4.
5.
6.
7.
8.
9.
8.1
The first three events will cause a device Reset. The last
three events are considered a continuation of program
execution. To determine whether a device Reset or wakeup event occurred, refer to Section 6.12 Determining
the Cause of a Reset.
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is prefetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be enabled. Wake-up will
occur regardless of the state of the GIE bit. If the GIE
bit is disabled, the device continues execution at the
instruction after the SLEEP instruction. If the GIE bit is
enabled, the device executes the instruction after the
SLEEP instruction, the device will then call the Interrupt
Service Routine. In cases where the execution of the
instruction following SLEEP is not desirable, the user
should have a NOP after the SLEEP instruction.
The WDT is cleared when the device wakes up from
Sleep, regardless of the source of wake-up.
8.1.1
DS40001723D-page 83
PIC12(L)F1571/2
FIGURE 8-1:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
CLKIN(1)
TOST(3)
CLKOUT(2)
Interrupt Flag
GIE bit
(INTCON reg.)
Instruction Flow
PC
Instruction
Fetched
Instruction
Executed
Note 1:
2:
3:
4:
8.2
Processor in
Sleep
PC
PC + 1
PC + 2
PC + 2
Inst(PC) = Sleep
Inst(PC + 1)
Inst(PC + 2)
Inst(PC 1)
Sleep
Inst(PC + 1)
PC + 2
Forced NOP
0004h
0005h
Inst(0004h)
Inst(0005h)
Forced NOP
Inst(0004h)
8.2.2
8.2.1
DS40001723D-page 84
PIC12(L)F1571/2
8.3
REGISTER 8-1:
U-0
U-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-1/1
VREGPM
Reserved
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
Unimplemented: Read as 0
bit 1
bit 0
Note 1:
2:
PIC12F1571/2 only.
See Section 26.0 Electrical Specifications
TABLE 8-1:
Name
Bit 7
Bit 6
Bit 5
INTCON
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register on
Page
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
IOCAF
IOCAF5
IOCAF4
IOCAF3
IOCAF2
IOCAF1
IOCAF0
122
IOCAN
IOCAN5
IOCAN4
IOCAN3
IOCAN2
IOCAN1
IOCAN0
121
IOCAP
IOCAP5
IOCAP4
IOCAP3
IOCAP2
IOCAP1
IOCAP0
121
TXIE(1)
PIE1
TMR1GIE
ADIE
RCIE(1)
TMR2IE
TMR1IE
75
PIE2
C1IE
76
PIE3
PWM3IE
PWM2IE
PWM1IE
77
PIR1
TMR1GIF
ADIF
RCIF(1)
TXIF(1)
TMR2IF
TMR1IF
78
PIR2
C1IF
79
PIR3
PWM3IF
PWM2IF
PWM1IF
80
STATUS
TO
PD
DC
19
WDTCON
SWDTEN
89
WDTPS<4:0>
Legend: = unimplemented, read as 0. Shaded cells are not used in Power-Down mode.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 85
PIC12(L)F1571/2
NOTES:
DS40001723D-page 86
PIC12(L)F1571/2
9.0
FIGURE 9-1:
WDTE<1:0> = 01
SWDTEN
WDTE<1:0> = 11
LFINTOSC
23-%it Programmable
Prescaler WDT
WDT
Time-out
WDTE<1:0> = 10
Sleep
WDTPS<4:0>
DS40001723D-page 87
PIC12(L)F1571/2
9.1
9.3
9.2
9.2.1
WDT IS ALWAYS ON
9.2.2
9.2.3
TABLE 9-1:
WDTE<1:0>
SWDTEN
11
10
01
00
TABLE 9-2:
Device
Mode
9.4
WDT
Mode
Active
Awake
Active
Sleep
Disabled
Active
Disabled
Disabled
Time-out Period
Any Reset
CLRWDT instruction is executed
Device enters Sleep
Device wakes up from Sleep
Oscillator fails
WDT is disabled
Oscillator Start-up Timer (OST) is running
9.5
WDT
WDTE<1:0> = 00
WDTE<1:0> = 01 and SWDTEN = 0
WDTE<1:0> = 10 and enter Sleep
CLRWDT Command
Cleared
DS40001723D-page 88
PIC12(L)F1571/2
9.6
REGISTER 9-1:
U-0
U-0
R/W-0/0
R/W-1/1
R/W-0/0
R/W-1/1
R/W-1/1
WDTPS<4:0>
bit 7
R/W-0/0
SWDTEN
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-1
bit 0
Note 1:
DS40001723D-page 89
PIC12(L)F1571/2
TABLE 9-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
OSCCON
SPLLEN
PCON
STKOVF
STKUNF
RWDT
STATUS
TO
WDTCON
Bit 3
IRCF<3:0>
Bit 2
Bit 1
Bit 0
SCS<1:0>
RMCLR
RI
POR
PD
DC
WDTPS<4:0>
Register
on Page
55
BOR
66
19
SWDTEN
89
Legend: = unimplemented location, read as 0. Shaded cells are not used by the Watchdog Timer.
TABLE 9-4:
Name
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CONFIG1 13:8
CLKOUTEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
Bit 8/0
Register
on Page
42
FOSC<1:0>
Legend: = unimplemented location, read as 0. Shaded cells are not used by the Watchdog Timer.
DS40001723D-page 90
PIC12(L)F1571/2
10.0
PMCON1
PMCON2
PMDATL
PMDATH
PMADRL
PMADRH
10.1
10.1.1
10.2
DS40001723D-page 91
PIC12(L)F1571/2
See Table 10-1 for erase row size and the number of
write latches for Flash program memory.
TABLE 10-1:
FLASH MEMORY
ORGANIZATION BY DEVICE
Device
PIC12(L)F1571
PIC12(L)F1572
10.2.1
Row Erase
(words)
Write
Latches
(words)
16
16
2.
3.
FLASH PROGRAM
MEMORY READ
FLOWCHART
Rev. 10-000046A
7/30/2013
Start
Read Operation
Select
Program or Configuration Memory
(CFGS)
FIGURE 10-1:
Select
Word Address
(PMADRH:PMADRL)
End
Read Operation
DS40001723D-page 92
PIC12(L)F1571/2
FIGURE 10-2:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
PC
Flash ADDR
Flash Data
PC + 1
INSTR (PC)
INSTR(PC 1)
Executed Here
PMADRH,PMADRL
INSTR (PC + 1)
BSF PMCON1,RD
Executed Here
PC
+3
PC+3
PMDATH,PMDATL
INSTR(PC + 1)
Instruction Ignored,
Forced NOP
Executed Here
PC + 5
PC + 4
INSTR (PC + 3)
INSTR(PC + 2)
Instruction Ignored,
Forced NOP
Executed Here
INSTR (PC + 4)
INSTR(PC + 3)
Executed Here
INSTR(PC + 4)
Executed Here
RD bit
PMDATH
PMDATL
Register
EXAMPLE 10-1:
PMADRL
PROG_ADDR_LO
PMADRL
PROG_ADDR_HI
PMADRH
BCF
BSF
NOP
NOP
PMCON1,CFGS
PMCON1,RD
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
DS40001723D-page 93
PIC12(L)F1571/2
10.2.2
FIGURE 10-3:
FLASH PROGRAM
MEMORY UNLOCK
SEQUENCE FLOWCHART
Rev. 10-000047A
7/30/2013
Start
Unlock Sequence
Write 0x55 to
PMCON2
Write 0xAA to
PMCON2
Initiate
Write or Erase operation
(WR = 1)
End
Unlock Sequence
DS40001723D-page 94
PIC12(L)F1571/2
10.2.3
FIGURE 10-4:
FLASH PROGRAM
MEMORY ERASE
FLOWCHART
Rev. 10-000048A
7/30/2013
Start
Erase Operation
Disable Interrupts
(GIE = 0)
Select
Program or Configuration Memory
(CFGS)
Unlock Sequence
(See Note 1)
Re-enable Interrupts
(GIE = 1)
End
Erase Operation
DS40001723D-page 95
PIC12(L)F1571/2
EXAMPLE 10-2:
Required
Sequence
BCF
BANKSEL
MOVF
MOVWF
MOVF
MOVWF
BCF
BSF
BSF
INTCON,GIE
PMADRL
ADDRL,W
PMADRL
ADDRH,W
PMADRH
PMCON1,CFGS
PMCON1,FREE
PMCON1,WREN
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
BCF
BSF
DS40001723D-page 96
PMCON1,WREN
INTCON,GIE
; Disable writes
; Enable interrupts
PIC12(L)F1571/2
10.2.4
1.
2.
3.
DS40001723D-page 97
0 7
PMADRH
-
rA
r9
r8
r7
r6
PMADRL
r5
r4
r3
r2
r1
r0
c3
c2
c1
5
-
PMDATH
PMDATL
c0
Rev. 10-000004B
7/25/2013
0
8
14
11
14
Write Latch #0
00h
14
14
14
Write Latch #1
01h
PMADRL<3:0>
14
CFGS = 0
PMADRH<6:0>:
PMADRL<7:4>
Row
Address
Decode
14
14
14
Row
Addr
Addr
Addr
Addr
000h
0000h
0001h
000Eh
000Fh
001h
0010h
0011h
001Eh
001Fh
002h
0020h
0021h
002Eh
002Fh
7FEh
7FE0h
7FE1h
7FEEh
7FEFh
7FFh
7FF0h
7FF1h
7FFEh
7FFFh
800h
CFGS = 1
8000h - 8003h
8004h 8005h
8006h
8007h 8008h
8009h - 801Fh
USER ID 0 - 3
reserved
DEVICE ID
Dev / Rev
Configuration
Words
reserved
Configuration Memory
PIC12(L)F1571/2
DS40001723D-page 98
FIGURE 10-5:
PIC12(L)F1571/2
FIGURE 10-6:
Start
Write Operation
Disable Interrupts
(GIE = 0)
Select
Program or Config. Memory
(CFGS)
Enable Write/Erase
Operation (WREN = 1)
Last word to
write ?
Yes
No
Unlock Sequence
(Figure10-3
x-x)
Figure
Increment Address
(PMADRH:PMADRL++)
Unlock Sequence
(Figure10-3
x-x)
Figure
Disable
Write/Erase Operation
(WREN = 0)
Re-enable Interrupts
(GIE = 1)
End
Write Operation
DS40001723D-page 99
PIC12(L)F1571/2
EXAMPLE 10-3:
;
;
;
;
;
;
;
INTCON,GIE
PMADRH
ADDRH,W
PMADRH
ADDRL,W
PMADRL
LOW DATA_ADDR
FSR0L
HIGH DATA_ADDR
FSR0H
PMCON1,CFGS
PMCON1,WREN
PMCON1,LWLO
;
;
;
;
;
;
;
;
;
;
;
;
;
MOVIW
MOVWF
MOVIW
MOVWF
FSR0++
PMDATL
FSR0++
PMDATH
MOVF
XORLW
ANDLW
BTFSC
GOTO
PMADRL,W
0x1F
0x1F
STATUS,Z
START_WRITE
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
PMADRL,F
LOOP
PMCON1,LWLO
55h
PMCON2
0AAh
PMCON2
PMCON1,WR
;
;
;
;
;
;
;
;
;
;
;
;
;
Required
Sequence
LOOP
NOP
INCF
GOTO
Required
Sequence
START_WRITE
BCF
MOVLW
MOVWF
MOVLW
MOVWF
BSF
NOP
NOP
BCF
BSF
DS40001723D-page 100
PMCON1,WREN
INTCON,GIE
PIC12(L)F1571/2
10.3
FIGURE 10-7:
FLASH PROGRAM
MEMORY MODIFY
FLOWCHART
Rev. 10-000050A
7/30/2013
Start
Modify Operation
Read Operation
(See Note 1)
Modify Image
The words to be modified are
changed in the RAM image
Erase Operation
(See Note 2)
Write Operation
Use RAM image
(See Note 3)
End
Modify Operation
DS40001723D-page 101
PIC12(L)F1571/2
10.4
TABLE 10-2:
Address
Function
Read Access
Write Access
8000h-8003h
User IDs
Yes
Yes
8006h/8005h
Device ID/Revision ID
Yes
No
8007h-8008h
Yes
No
EXAMPLE 10-4:
* This code block will read 1 word of program memory at the memory address:
*
PROG_ADDR_LO (must be 00h-08h) data will be returned in the variables;
*
PROG_DATA_HI, PROG_DATA_LO
BANKSEL
MOVLW
MOVWF
CLRF
PMADRL
PROG_ADDR_LO
PMADRL
PMADRH
BSF
BCF
BSF
NOP
NOP
BSF
PMCON1,CFGS
INTCON,GIE
PMCON1,RD
INTCON,GIE
;
;
;
;
;
;
MOVF
MOVWF
MOVF
MOVWF
PMDATL,W
PROG_DATA_LO
PMDATH,W
PROG_DATA_HI
;
;
;
;
DS40001723D-page 102
PIC12(L)F1571/2
10.5
Write Verify
FIGURE 10-8:
FLASH PROGRAM
MEMORY VERIFY
FLOWCHART
Rev. 10-000051A
7/30/2013
Start
Verify Operation
Read Operation
(See Note 1)
PMDAT =
RAM image ?
No
Yes
Fail
Verify Operation
No
Last word ?
Yes
End
Verify Operation
DS40001723D-page 103
PIC12(L)F1571/2
10.6
REGISTER 10-1:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMDAT<7:0>: Read/Write Value for Least Significant bits of Program Memory bits
REGISTER 10-2:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PMDAT<13:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
PMDAT<13:8>: Read/Write Value for Most Significant bits of Program Memory bits
DS40001723D-page 104
PIC12(L)F1571/2
REGISTER 10-3:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
PMADR<7:0>: Specifies Least Significant bits for Program Memory Address bits
REGISTER 10-4:
U-1
R/W-0/0
R/W-0/0
R/W-0/0
(1)
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
PMADR<14:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-0
PMADR<14:8>: Specifies the Most Significant bits for Program Memory Address bits
Note 1:
Unimplemented, read as 1.
DS40001723D-page 105
PIC12(L)F1571/2
REGISTER 10-5:
U-1
R/W-0/0
(1)
CFGS
R/W-0/0
R/W/HC-0/0 R/W/HC-x/q(2)
(3)
LWLO
FREE
WRERR
R/W-0/0
R/S/HC-0/0
R/S/HC-0/0
WREN
WR
RD
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
2:
3:
DS40001723D-page 106
PIC12(L)F1571/2
REGISTER 10-6:
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
W-0/0
bit 0
Legend:
R = Readable bit
W = Writable bit
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
TABLE 10-3:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PMCON1
(1)
CFGS
LWLO
FREE
WRERR
WREN
WR
RD
106
PMCON2
107
PMADRL
PMADRL<7:0>
105
PMADRH
(1)
PMADRH<6:0>
PMDATL
105
PMDATL<7:0>
PMDATH
104
PMDATH<5:0>
104
Legend: = unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
Note 1: Unimplemented, read as 1.
TABLE 10-4:
Name
CONFIG1
CONFIG2
Bits
Bit -/7
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
13:8
CLKOUTEN
7:0
CP
MCLRE
PWRTE
13:8
LVP
DEBUG
LPBOR
BORV
7:0
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<1:0>
STVREN
PLLEN
WRT<1:0>
Register
on Page
42
43
Legend: = unimplemented location, read as 0. Shaded cells are not used by Flash program memory.
DS40001723D-page 107
PIC12(L)F1571/2
NOTES:
DS40001723D-page 108
PIC12(L)F1571/2
11.0
I/O PORTS
FIGURE 11-1:
Read LATx
TRISx
Write LATx
Write PORTx
VDD
CK
Device
PORTA
TABLE 11-1:
Data Register
Data bus
I/O pin
Read PORTx
To digital peripherals
PIC12(L)F1571
ANSELx
PIC12(L)F1572
To analog peripherals
VSS
DS40001723D-page 109
PIC12(L)F1571/2
11.1
RX/DT
TX/CK
CWGOUTA
CWGOUTB
PWM2
PWM1
11.2
REGISTER 11-1:
R/W-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
RXDTSEL
CWGASEL
CWGBSEL
T1GSEL
TXCKSEL
P2SEL
P1SEL
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001723D-page 110
PIC12(L)F1571/2
11.3
11.3.1
PORTA Registers
DATA REGISTER
11.3.2
DIRECTION CONTROL
11.3.3
OPEN-DRAIN CONTROL
11.3.4
11.3.5
11.3.6
ANALOG CONTROL
EXAMPLE 11-1:
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
CLRF
BANKSEL
MOVLW
MOVWF
INITIALIZING PORTA
PORTA
PORTA
LATA
LATA
ANSELA
ANSELA
TRISA
B'00111000'
TRISA
;
;Init PORTA
;Data Latch
;
;
;digital I/O
;
;Set RA<5:3> as inputs
;and set RA<2:0> as
;outputs
DS40001723D-page 111
PIC12(L)F1571/2
11.3.7
TABLE 11-2:
RA0
ICSPDAT
CWG1B(3)
DAC1OUT
TX(2,3)
PWM2(3)
RA0
RA1
PWM1(3)
RA1
RA2
CWG1A
CWG1FLT
C1OUT
PWM3
RA2
RA3
None
RA4
CLKOUT
CWG1B
TX(2)
PWM2
RA4
RA5
CWG1A
PWM1
RA5
Note 1:
2:
3:
DS40001723D-page 112
Function Priority(1)
Pin Name
PIC12(L)F1571/2
11.4
REGISTER 11-2:
U-0
U-0
R/W-x/x
R/W-x/x
R-x/x
R/W-x/x
R/W-x/x
R/W-x/x
RA<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are
the return of actual I/O pin values.
REGISTER 11-3:
U-0
U-0
R/W-1/1
R/W-1/1
TRISA<5:4>
U-1
(1)
R/W-1/1
R/W-1/1
R/W-1/1
TRISA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
bit 2-0
Note 1:
Unimplemented, read as 1.
DS40001723D-page 113
PIC12(L)F1571/2
REGISTER 11-4:
U-0
U-0
R/W-x/u
R/W-x/u
U-0
LATA<5:4>(1)
R/W-x/u
R/W-x/u
R/W-x/u
LATA<2:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
Note 1:
Writes to PORTA are actually written to corresponding LATA register. Reads from the PORTA register are
the return of actual I/O pin values.
REGISTER 11-5:
U-0
U-0
U-0
R/W-1/1
U-0
ANSA4
R/W-1/1
R/W-1/1
R/W-1/1
ANSA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4
ANSA4: Analog Select Between Analog or Digital Function on RA4 Pins (respectively) bit
1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
bit 3
Unimplemented: Read as 0
bit 2-0
ANSA<2:0>: Analog Select Between Analog or Digital Function on RA<2:0> pins (respectively) bits
1 = Analog input; pin is assigned as analog input, digital input buffer is disabled(1)
0 = Digital I/O; pin is assigned to port or digital special function
Note 1:
When setting a pin to an analog input, the corresponding TRISx bit must be set to Input mode in order to
allow external control of the voltage on the pin.
DS40001723D-page 114
PIC12(L)F1571/2
REGISTER 11-6:
U-0
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUA<5:0>
R/W-1/1
R/W-1/1
(1,2,3)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
Note 1:
2:
3:
Global WPUEN bit of the OPTION_REG register must be cleared for individual pull-ups to be enabled.
The weak pull-up device is automatically disabled if the pin is configured as an output.
For the WPUA3 bit, when MCLRE = 1, the weak pull-up is internally enabled, but not reported here.
REGISTER 11-7:
U-0
U-0
R/W-0/0
R/W-0/0
ODA<5:4>
U-0
R/W-0/0
R/W-0/0
R/W-0/0
ODA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
DS40001723D-page 115
PIC12(L)F1571/2
REGISTER 11-8:
U-0
U-0
R/W-1/1
R/W-1/1
U-0
SLRA<5:4>
R/W-1/1
R/W-1/1
R/W-1/1
SLRA<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
REGISTER 11-9:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
INLVLA5
INLVLA4
INLVLA3
INLVLA2
INLVLA1
INLVLA0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001723D-page 116
PIC12(L)F1571/2
TABLE 11-3:
Name
ANSELA
APFCON
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
ANSA4
Bit 2
Bit 1
Bit 0
ANSA<2:0>
T1GSEL TXCKSEL
P2SEL
Register
on Page
114
P1SEL
INLVLA<5:0>
110
INLVLA
LATA
LATA<5:4>
LATA<2:0>
114
ODCONA
ODA<5:4>
ODA<2:0>
115
PS<2:0>
157
WPUEN
INTEDG
PORTA
SLRCONA
SLRA<5:4>
SLRA<2:0>
116
TRISA
TRISA<5:4>
(1)
TRISA<2:0>
113
WPUA
OPTION_REG
TMR0CS
TMR0SE
116
PSA
RA<5:0>
113
WPUA<5:0>
115
Legend: = unimplemented location, read as 0. Shaded cells are not used by PORTA.
Note 1: Unimplemented, read as 1.
TABLE 11-4:
Name
CONFIG1
Bits
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
IESO
CLKOUTEN
13:8
FCMEN
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
BOREN<1:0>
Bit 8/0
FOSC<2:0>
Register
on Page
42
Legend: = unimplemented location, read as 0. Shaded cells are not used by PORTA.
DS40001723D-page 117
PIC12(L)F1571/2
NOTES:
DS40001723D-page 118
PIC12(L)F1571/2
12.0
INTERRUPT-ON-CHANGE
12.1
12.3
Interrupt Flags
12.4
12.2
EXAMPLE 12-1:
MOVLW
XORWF
ANDWF
12.5
CLEARING INTERRUPT
FLAGS (PORTA EXAMPLE)
0xff
IOCAF, W
IOCAF, F
Operation in Sleep
DS40001723D-page 119
PIC12(L)F1571/2
FIGURE 12-1:
IOCANx
Q4Q1
edge
detect
RAx
IOCAPx
data bus =
0 or 1
to data bus
IOCAFx
write IOCAFx
IOCIE
Q2
IOC interrupt
to CPU core
from all other
IOCnFx individual
pin detectors
FOSC
Q1
Q1
Q2
Q2
Q2
Q3
Q3
Q4
Q4Q1
Q1
Q3
Q4
Q4Q1
DS40001723D-page 120
Q4
Q4Q1
Q4Q1
PIC12(L)F1571/2
12.6
REGISTER 12-1:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAP<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 12-2:
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
IOCAN<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001723D-page 121
PIC12(L)F1571/2
REGISTER 12-3:
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
R/W/HS-0/0
IOCAF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
TABLE 12-1:
Name
Bit 6
Bit 5
Bit 4
Bit 3
ANSELA
ANSA4
INTCON
TMR0IE
INTE
IOCIE
Bit 2
Bit 1
Bit 0
ANSA<2:0>
GIE
PEIE
IOCAF<5:0>
122
IOCAN
IOCAN<5:0>
121
IOCAP
IOCAP<5:0>
121
TRISA
TRISA<5:4>
INTF
114
IOCAF
(1)
TMR0IF
Register
on Page
IOCIF
TRISA<2:0>
74
113
Legend: = unimplemented location, read as 0. Shaded cells are not used by Interrupt-On-Change.
Note 1: Unimplemented, read as 1.
DS40001723D-page 122
PIC12(L)F1571/2
13.0
13.1
13.2
FIGURE 13-1:
Rev. 10-000053A
8/6/2013
ADFVR<1:0>
CDAFVR<1:0>
FVREN
Note 1
2
1x
2x
4x
FVR_buffer1
(To ADC Module)
1x
2x
4x
FVR_buffer2
(To Comparators)
+
_
FVRRDY
Note 1: Any peripheral requiring the Fixed Voltage Reference (see Table 13-1).
DS40001723D-page 123
PIC12(L)F1571/2
TABLE 13-1:
Peripheral
HFINTOSC
BOR
LDO
Conditions
Description
BOREN<1:0> = 11
DS40001723D-page 124
PIC12(L)F1571/2
13.3
REGISTER 13-1:
R/W-0/0
R-q/q
R/W-0/0
R/W-0/0
FVREN(1)
FVRRDY(2)
TSEN(3)
TSRNG(3)
R/W-0/0
R/W-0/0
R/W-0/0
CDAFVR<1:0>(1)
R/W-0/0
ADFVR<1:0>(1)
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Note 1:
2:
3:
4:
To minimize current consumption when the FVR is disabled, the FVR buffers should be turned off by
clearing the Buffer Gain Selection bits.
FVRRDY is always 1 for the PIC12F1571/2 devices.
See Section 14.0 Temperature Indicator Module for additional information.
Fixed Voltage Reference output cannot exceed VDD.
TABLE 13-2:
Name
FVRCON
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR>1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on Page
125
DS40001723D-page 125
PIC12(L)F1571/2
NOTES:
DS40001723D-page 126
PIC12(L)F1571/2
14.0
TEMPERATURE INDICATOR
MODULE
FIGURE 14-1:
Rev. 10-000069A
7/31/2013
VDD
TSEN
14.1
TEMPERATURE CIRCUIT
DIAGRAM
TSRNG
VOUT
Temp. Indicator
To ADC
Circuit Operation
EQUATION 14-1:
VOUT RANGES
14.2
TABLE 14-1:
3.6V
1.8V
14.3
Temperature Output
14.4
DS40001723D-page 127
PIC12(L)F1571/2
TABLE 14-2:
Name
FVRCON
Bit 6
Bit 5
Bit 4
FVREN
FVRRDY
TSEN
TSRNG
Bit 3
Bit 2
CDAFVR<1:0>
Bit 1
Bit 0
ADFVR<1:0>
Register
on Page
118
DS40001723D-page 128
PIC12(L)F1571/2
15.0
ANALOG-TO-DIGITAL
CONVERTER (ADC) MODULE
FIGURE 15-1:
ADPREF
Rev. 10-000033A
7/30/2013
Positive
Reference
Select
VDD
VREF+ pin
External
Channel
Inputs
ANa
VRNEG VRPOS
.
.
.
ADC_clk
sampled
input
ANz
Internal
Channel
Inputs
ADCS<2:0>
VSS
AN0
ADC
Clock
Select
FOSC/n Fosc
Divider
FRC
FOSC
FRC
Temp Indicator
DACx_output
FVR_buffer1
ADC
Sample Circuit
CHS<4:0>
ADFM
Write to bit
GO/DONE
10-bit Result
GO/DONE
Q1
Q4
16
start
ADRESH
Q2
TRIGSEL<3:0>
10
complete
ADRESL
Enable
Trigger Select
ADON
. . .
VSS
Trigger Sources
AUTO CONVERSION
TRIGGER
DS40001723D-page 129
PIC12(L)F1571/2
15.1
ADC Configuration
Port configuration
Channel selection
ADC voltage reference selection
ADC conversion clock source
Interrupt control
Result formatting
15.1.1
PORT CONFIGURATION
15.1.2
CHANNEL SELECTION
AN<3:0> pins
Temperature Indicator
DAC1_output
FVR_buffer1
15.1.4
CONVERSION CLOCK
FOSC/2
FOSC/4
FOSC/8
FOSC/16
FOSC/32
FOSC/64
FRC (internal Fast RC oscillator)
15.1.3
DS40001723D-page 130
PIC12(L)F1571/2
TABLE 15-1:
ADCS<2:0>
20 MHz
16 MHz
8 MHz
4 MHz
1 MHz
Fosc/2
000
100 ns
125 ns
250 ns
500 ns
2.0 s
Fosc/4
100
200 ns
250 ns
500 ns
1.0 s
4.0 s
Fosc/8
001
400 ns
500 ns
1.0 s
2.0 s
8.0 s
Fosc/16
101
800 ns
1.0 s
2.0 s
4.0 s
16.0 s
Fosc/32
010
1.6 s
2.0 s
4.0 s
8.0 s
32.0 s
Fosc/64
110
3.2 s
4.0 s
8.0 s
16.0 s
64.0 s
FRC
x11
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
1.0-6.0 s
The TAD period when using the FRC clock source can fall within a specified range (see TAD parameter).
The TAD period when using the FOSC-based clock source can be configured for a more precise TAD period.
However, the FRC clock source must be used when conversions are to be performed with the device in
Sleep mode.
FIGURE 15-2:
TAD1
TAD2
TAD3
TAD4
TAD5
TAD6
TAD7
TAD8
TAD9
TAD10
TAD11
b9
b8
b7
b6
b5
b4
b3
b2
b1
b0
THCD
Conversion Starts
TACQ
DS40001723D-page 131
PIC12(L)F1571/2
15.1.5
INTERRUPTS
15.1.6
RESULT FORMATTING
FIGURE 15-3:
ADRESH
ADRESL
(ADFM = 0) MSB
LSB
bit 7
bit 0
bit 7
(ADFM = 1)
bit 0
Unimplemented: Read as 0
MSB
bit 7
Unimplemented: Read as 0
DS40001723D-page 132
LSB
bit 0
bit 7
bit 0
10-bit ADC Result
PIC12(L)F1571/2
15.2
15.2.1
ADC Operation
STARTING A CONVERSION
15.2.2
COMPLETION OF A CONVERSION
15.2.3
TERMINATING A CONVERSION
15.2.5
FIGURE 15-4:
15.2.4
OFx_match
PWMxOFIE
PHx_match
PWMxPHIE
AUTO-CONVERSION TRIGGER
PWMx_interrupt
DCx_match
PWMxDCIE
PRx_match
PWMxPRIE
TABLE 15-2:
AUTO-CONVERSION
SOURCES
Source Peripheral
Signal Name
Timer0
T0_overflow
Timer1
T1_overflow
Timer2
T2_match
Comparator C1
C1OUT_sync
PWM1
PWM1_OF_match
PWM1
PWM1_interrupt
PWM2
PWM2_OF_match
PWM2
PWM2_interrupt
PWM3
PWM3_OF_match
PWM3
PWM3_interrupt
DS40001723D-page 133
PIC12(L)F1571/2
15.2.6
2.
3.
4.
5.
6.
7.
8.
Configure port:
Disable pin output driver (refer to the
TRISx register)
Configure pin as analog (refer to the
ANSELx register)
Disable weak pull-ups either globally (refer to
the OPTION_REG register) or individually
(refer to the appropriate WPUx register)
Configure the ADC module:
Select ADC conversion clock
Configure voltage reference
Select ADC input channel
Turn on ADC module
Configure ADC interrupt (optional):
Clear ADC interrupt flag
Enable ADC interrupt
Enable peripheral interrupt
Enable global interrupt(1)
Wait the required acquisition time.(2)
Start conversion by setting the GO/DONE bit.
Wait for ADC conversion to complete by one of
the following:
Polling the GO/DONE bit
Waiting for the ADC interrupt (interrupts
enabled)
Read ADC result.
Clear the ADC interrupt flag (required if interrupt
is enabled).
EXAMPLE 15-1:
ADC CONVERSION
DS40001723D-page 134
PIC12(L)F1571/2
15.3
REGISTER 15-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
CHS<4:0>
R/W-0/0
R/W-0/0
R/W-0/0
GO/DONE
ADON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-2
bit 1
bit 0
Note 1:
2:
3:
DS40001723D-page 135
PIC12(L)F1571/2
REGISTER 15-2:
R/W-0/0
R/W-0/0
ADFM
R/W-0/0
R/W-0/0
ADCS<2:0>
U-0
U-0
R/W-0/0
bit 7
R/W-0/0
ADPREF<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
Note 1:
When selecting the VREF+ pin as the source of the positive reference, be aware that a minimum voltage
specification exists. See Section 26.0 Electrical Specifications for details.
DS40001723D-page 136
PIC12(L)F1571/2
REGISTER 15-3:
R/W-0/0
R/W-0/0
R/W-0/0
TRIGSEL<3:0>
R/W-0/0
(1)
U-0
U-0
U-0
U-0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
bit 3-0
Unimplemented: Read as 0
Note 1:
2:
DS40001723D-page 137
PIC12(L)F1571/2
REGISTER 15-4:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:2>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 15-5:
R/W-x/u
R/W-x/u
ADRES<1:0>
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-0
DS40001723D-page 138
PIC12(L)F1571/2
REGISTER 15-6:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<9:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-2
bit 1-0
REGISTER 15-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
ADRES<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 139
PIC12(L)F1571/2
15.4
EQUATION 15-1:
Assumptions:
T ACQ = Amplifier Settling Time + Hold Capacitor Charging Time + Temperature Coefficient
= T AMP + T C + T COFF
= 2s + T C + Temperature - 25C 0.05s/C
The value for TC can be approximated with the following equations:
1
= V CHOLD
V AP P LI ED 1 -------------------------n+1
2
1
TC
----------
RC
V AP P LI ED 1 e = V CHOLD
Tc
---------
1
RC
;combining [1] and [2]
V AP P LI ED 1 e = V A PP LIE D 1 -------------------------n
+
1
2
1
T C = C HOLD R IC + R SS + R S ln(1/2047)
= 12.5pF 1k + 7k + 10k ln(0.0004885)
= 1.715 s
Therefore:
T AC Q = 2s + 1.715 s + 50C- 25C 0.05 s/C
= 4.96s
Note 1: The Reference Voltage (VRPOS) has no effect on the equation, since it cancels itself out.
2: The Charge Holding Capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k. This is required to meet the pin
leakage specification.
DS40001723D-page 140
PIC12(L)F1571/2
FIGURE 15-5:
VDD
RS
Analog
Input pin
VT 0.6V
RIC 1K
Sampling
switch
SS
RSS
ILEAKAGE(1)
VA
Legend: CHOLD
CPIN
ILEAKAGE
RIC
RSS
SS
VT
Note 1:
FIGURE 15-6:
CPIN
5pF
CHOLD = 12.5 pF
VT 0.6V
Ref-
= Sample/Hold Capacitance
= Input Capacitance
= Leakage Current at the pin due to varies injunctions
= Interconnect Resistance
= Resistance of Sampling switch
= Sampling Switch
= Threshold Voltage
VDD
6V
5V
4V
3V
2V
RSS
5 6 7 8 9 10 11
Sampling Switch
(k )
Full-Scale Range
3FFh
3FEh
3FDh
3FCh
3FBh
03h
02h
01h
00h
Ref-
Zero-Scale
Transition
1.5 LSB
Full-Scale
Transition
Ref+
DS40001723D-page 141
PIC12(L)F1571/2
TABLE 15-3:
Name
ADCON0
ADCON1
ADFM
ADCON2
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
CHS<4:0>
ADCS<2:0>
TRIGSEL<3:0>
Bit 1
Bit 0
Register
on Page
GO/DONE
ADON
135
ADPREF<1:0>
136
137
ADRESH
138, 139
ADRESL
138, 139
ANSELA
ANSA4
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
ANSA<2:0>
INTF
IOCIF
114
(2)
(2)
74
PIE1
TMR1GIE
ADIE
RCIE
TXIE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF(2)
TXIF(2)
TMR2IF
TMR1IF
78
TRISA5
TRISA4
(1)
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
TRISA
FVRCON
TRISA<2:0>
ADFVR<1:0>
113
125
Legend: = unimplemented, read as 0. Shaded cells are not used for the ADC module.
Note 1: Unimplemented, read as 1.
2: PIC12(L)F1572 only.
DS40001723D-page 142
PIC12(L)F1571/2
16.0
5-BIT DIGITAL-TO-ANALOG
CONVERTER (DAC) MODULE
FIGURE 16-1:
VDD
00
01
VREF+
FVR_buffer2
10
Reserved
11
VSOURCE+
5
DACR<4:0>
DACPSS
DACEN
32-to-1 MUX
32
Steps
DACx_output
To Peripherals
DACxOUT1 (1)
DACOE1
R
VSS
VSOURCE-
DS40001723D-page 143
PIC12(L)F1571/2
16.1
16.2
16.3
EQUATION 16-1:
16.4
16.5
Effects of a Reset
IF DACEN = 1
DACR 4:0
DACx_output = VSOURCE+ VSOURCE- ----------------------------+ VSOURCE5
2
Note:
See the DACxCON0 register for the available VSOURCE+ and VSOURCE- selections.
DS40001723D-page 144
PIC12(L)F1571/2
16.6
REGISTER 16-1:
R/W-0/0
U-0
R/W-0/0
U-0
DACEN
DACOE
R/W-0/0
R/W-0/0
U-0
U-0
DACPSS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
Unimplemented: Read as 0
bit 5
bit 4
Unimplemented: Read as 0
bit 3-2
bit 1-0
Unimplemented: Read as 0
REGISTER 16-2:
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
DACR<4:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-5
Unimplemented: Read as 0
bit 4-0
TABLE 16-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
DACxCON0
DACEN
DACOE
DACxCON1
Bit 3
Bit 2
DACPSS<1:0>
DACR<4:0>
Bit 1
Bit 0
Register
on Page
145
145
DS40001723D-page 145
PIC12(L)F1571/2
NOTES:
DS40001723D-page 146
PIC12(L)F1571/2
17.0
COMPARATOR MODULE
17.1
Comparator Overview
FIGURE 17-1:
TABLE 17-1:
AVAILABLE COMPARATORS
Device
C1
PIC12(L)F1571
PIC12(L)F1572
CxNCH<2:0>
CxON(1)
000
CxIN0CxIN1-
001
Reserved
010
Reserved
011
Reserved
100
Reserved
101
FVR_buffer2
110
CxON(1)
CxVN
00
DAC_out
01
FVR_buffer2
10
Note 1:
Interrupt
Falling
Edge
CxINTN
set bit
CxIF
CxOUT
MCxOUT
Q1
CxSP CxHYS
CxPOL
CxOUT_async
to
peripherals
CxOUT_sync
to
peripherals
CxSYNC
CxOE
0
TRIS bit
CxOUT
11
CxPCH<1:0>
CxINTP
Cx
CxVP
111
CxIN+
Interrupt
Rising
Edge
CxON(1)
When CxON = 0, all multiplexer inputs are disconnected and the Comparator will produce a 0 at the output.
DS40001723D-page 147
PIC12(L)F1571/2
FIGURE 17-2:
SINGLE COMPARATOR
17.2.2
VIN+
VIN-
Output
VINVIN+
17.2
Output
Note:
Comparator Control
17.2.3
Enable
Output selection
Output polarity
Speed/power selection
Hysteresis enable
Output synchronization
Interrupt enable
Interrupt edge polarity
Positive input channel selection
Negative input channel selection
17.2.1
COMPARATOR ENABLE
17.2.4
DS40001723D-page 148
PIC12(L)F1571/2
17.2.5
TABLE 17-2:
COMPARATOR OUTPUT
STATE VS. INPUT CONDITIONS
Input Condition
CxVN > CxVP
CxVN < CxVP
CxVN > CxVP
CxVN < CxVP
17.2.6
CxPOL
CxOUT
0
0
1
1
0
1
1
0
17.3
COMPARATOR SPEED/POWER
SELECTION
The trade-off between speed or power can be optimized during program execution with the CxSP control
bit. The default state for this bit is 1, which selects the
Normal Speed mode. Device power consumption can
be optimized at the cost of slower comparator
propagation delay by clearing the CxSP bit to 0.
FIGURE 17-3:
Rev. 10-000071A
8/2/2013
VDD
RS < 10K
Analog
Input pin
VT 0.6V
RIC
To Comparator
ILEAKAGE(1)
CPIN
5pF
VA
VT 0.6V
VSS
Legend: CPIN
ILEAKAGE
RIC
RS
VA
VT
Note 1:
= Input Capacitance
= Leakage Current at the pin due to various junctions
= Interconnect Resistance
= Source Impedance
= Analog Voltage
= Threshold Voltage
DS40001723D-page 149
PIC12(L)F1571/2
17.4
Comparator Hysteresis
17.5
17.5.1
COMPARATOR OUTPUT
SYNCHRONIZATION
17.6
An interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising
edge detector and a falling edge detector are present.
When either edge detector is triggered and its associated enable bit is set (CxINTP and/or CxINTN bits of
the CMxCON1 register), the corresponding interrupt
flag bit (CxIF bit of the PIR2 register) will be set.
To enable the interrupt, you must set the following bits:
CxON and CxPOL bits of the CMxCON0 register
CxIE bit of the PIE2 register
CxINTP bit of the CMxCON1 register (for a rising
edge detection)
CxINTN bit of the CMxCON1 register (for a falling
edge detection)
PEIE and GIE bits of the INTCON register
The associated interrupt flag bit, CxIF bit of the PIR2
register, must be cleared in software. If another edge is
detected while this flag is being cleared, the flag will still
be set at the end of the sequence.
Note:
DS40001723D-page 150
Comparator Interrupt
17.7
PIC12(L)F1571/2
17.8
REGISTER 17-1:
R/W-0/0
R-0/0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
CxON
CxOUT
CxOE
CxPOL
CxSP
CxHYS
CxSYNC
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
DS40001723D-page 151
PIC12(L)F1571/2
REGISTER 17-2:
R/W-0/0
R/W-0/0
CxINTP
CxINTN
R/W-0/0
R/W-0/0
CxPCH<1:0>
U-0
R/W-0/0
R/W-0/0
R/W-0/0
CxNCH<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
REGISTER 17-3:
U-0
U-0
U-0
U-0
U-0
U-0
R-0/0
MC1OUT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-1
Unimplemented: Read as 0
bit 0
DS40001723D-page 152
PIC12(L)F1571/2
TABLE 17-3:
Name
ANSELA
Bit 6
Bit 5
Bit 4
Bit 3
ANSA4
C1OE
C1POL
Bit 2
C1ON
C1OUT
CM1CON1
C1NTP
C1INTN
DACEN
DACOE
DACPSS<1:0>
CDAFVR<1:0>
CMOUT
DAC1CON0
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
INTCON
DAC1CON1
C1SP
Bit 0
ANSA<2:0>
CM1CON0
C1PCH<1:0>
Bit 1
114
C1HYS
C1SYNC
C1NCH<2:0>
Register
on Page
151
152
MC1OUT
152
145
DACR<4:0>
145
ADFVR<1:0>
125
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PIE2
C1IE
76
PIR2
C1IF
PORTA
RA5
RA4
RA3
LATA
LATA5
LATA4
TRISA
TRISA5
TRISA4
79
RA<2:0>
113
LATA<2:0>
114
(1)
TRISA<2:0>
113
Legend: = unimplemented location, read as 0. Shaded cells are unused by the comparator module.
Note 1: Unimplemented, read as 1.
DS40001723D-page 153
PIC12(L)F1571/2
NOTES:
DS40001723D-page 154
PIC12(L)F1571/2
18.0
TIMER0 MODULE
18.1.2
18.1
Timer0 Operation
18.1.1
FIGURE 18-1:
TMR0CS
Fosc/4
T0CKI(1)
PSA
0
1
TMR0SE
1
write
to
TMR0
Prescaler
R
0 FOSC/2
T0CKI
Sync Circuit
PS<2:0>
T0_overflow
TMR0
Q1
set bit
TMR0IF
Note 1: The T0CKI prescale output frequency should not exceed FOSC/8.
DS40001723D-page 155
PIC12(L)F1571/2
18.1.3
SOFTWARE PROGRAMMABLE
PRESCALER
18.1.4
18.1.5
18.1.6
TIMER0 INTERRUPT
DS40001723D-page 156
PIC12(L)F1571/2
18.2
REGISTER 18-1:
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
R/W-1/1
WPUEN
INTEDG
TMR0CS
TMR0SE
PSA
R/W-1/1
R/W-1/1
R/W-1/1
PS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
TABLE 18-1:
Name
Bit 7
TRISA
000
001
010
011
100
101
110
111
1:2
1:4
1:8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 6
Bit 5
Bit 4
TRIGSEL<3:0>
GIE
OPTION_REG WPUEN
TMR0
Timer0 Rate
ADCON2
INTCON
Bit Value
PEIE
TMR0IE
INTE
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
137
IOCIE
TMR0IF
INTF
IOCIF
74
PSA
PS<2:0>
157
TRISA5
TRISA4
155*
(1)
TRISA2
TRISA1
TRISA0
113
Legend: = unimplemented location, read as 0. Shaded cells are not used by the Timer0 module.
* Page provides register information.
Note 1: Unimplemented, read as 1.
DS40001723D-page 157
PIC12(L)F1571/2
NOTES:
DS40001723D-page 158
PIC12(L)F1571/2
19.0
FIGURE 19-1:
T1GSS<1:0>
Rev. 10-000018D
8/5/2013
T1G
00
T0_overflow
01
C1OUT_sync
10
Reserved
11
T1GSPM
0
1
D
1
Single Pulse
Acq. Control
T1GVAL
Q1
T1GGO/DONE
T1GPOL
CK
Interrupt
TMR1ON
R
set bit
TMR1GIF
det
T1GTM
TMR1GE
set flag bit
TMR1IF
TMR1ON
EN
T1_overflow
TMR1(2)
TMR1H
TMR1L
T1CLK
T1SYNC
TMR1CS<1:0>
LFINTOSC
(1)
11
10
T1CKI
Fosc
Internal Clock
01
00
Fosc/4
Internal Clock
Prescaler
1,2,4,8
Synchronize(3)
det
2
T1CKPS<1:0>
Fosc/2
Internal
Clock
Sleep
Input
DS40001723D-page 159
PIC12(L)F1571/2
19.1
Timer1 Operation
19.2
TABLE 19-1:
TIMER1 ENABLE
SELECTIONS
19.2.1
Timer1
Operation
TMR1ON
TMR1GE
Off
Off
Always On
Count Enabled
19.2.2
TABLE 19-2:
TMR1CS<1:0>
T1OSCEN(1)
11
LFINTOSC
10
01
00
Note 1:
Clock Source
DS40001723D-page 160
PIC12(L)F1571/2
19.3
Timer1 Prescaler
19.4
Timer1 Operation in
Asynchronous Counter Mode
19.4.1
19.5
Timer1 Gate
19.5.1
TABLE 19-3:
T1CLK
T1GPOL
T1G
Counts
Holds Count
Holds Count
Counts
19.5.2
Timer1 Operation
TABLE 19-4:
T1GSS<1:0>
00
01
10
11
Reserved
Note 1:
DS40001723D-page 161
PIC12(L)F1571/2
19.5.2.1
19.5.2.2
When Timer0 increments from FFh to 00h, a low-tohigh pulse will automatically be generated and
internally supplied to the Timer1 gate circuitry.
19.5.3
19.5.4
19.5.5
19.5.6
When Timer1 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a
gate event. When the falling edge of T1GVAL occurs,
the TMR1GIF flag bit in the PIR1 register will be set. If
the TMR1GIE bit in the PIE1 register is set, then an
interrupt will be recognized.
The TMR1GIF flag bit operates even when the Timer1
gate is not enabled (TMR1GE bit is cleared).
DS40001723D-page 162
PIC12(L)F1571/2
19.6
Timer1 Interrupt
19.7
19.7.1
FIGURE 19-2:
T1CKI = 1
when TMR1
is Enabled
T1CKI = 0
when TMR1
is Enabled
Note 1:
2:
DS40001723D-page 163
PIC12(L)F1571/2
FIGURE 19-3:
TMR1GE
T1GPOL
t1g_in
T1CKI
T1GVAL
Timer1
FIGURE 19-4:
N+1
N+2
N+3
N+4
TMR1GE
T1GPOL
T1GTM
t1g_in
T1CKI
T1GVAL
Timer1
DS40001723D-page 164
N+4
N+8
PIC12(L)F1571/2
FIGURE 19-5:
TMR1GE
T1GPOL
T1GSPM
T1GGO/
DONE
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
Counting Enabled on
Rising Edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
Cleared by Software
N+1
N+2
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
DS40001723D-page 165
PIC12(L)F1571/2
FIGURE 19-6:
TMR1GE
T1GPOL
T1GSPM
T1GTM
T1GGO/
DONE
Cleared by Hardware on
Falling Edge of T1GVAL
Set by Software
Counting Enabled on
Rising Edge of T1G
t1g_in
T1CKI
T1GVAL
Timer1
TMR1GIF
DS40001723D-page 166
Cleared by Software
N+1
N+2
N+3
N+4
Set by Hardware on
Falling Edge of T1GVAL
Cleared by
Software
PIC12(L)F1571/2
19.8
REGISTER 19-1:
R/W-0/u
R/W-0/u
R/W-0/u
TMR1CS<1:0>
R/W-0/u
T1CKPS<1:0>
U-0
R/W-0/u
U-0
R/W-0/u
T1SYNC
TMR1ON
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2
bit 1
Unimplemented: Read as 0
bit 0
DS40001723D-page 167
PIC12(L)F1571/2
REGISTER 19-2:
R/W-0/u
R/W-0/u
R/W-0/u
R/W-0/u
R/W/HC-0/u
R-x/x
TMR1GE
T1GPOL
T1GTM
T1GSPM
T1GGO/
DONE
T1GVAL
R/W-0/u
bit 7
R/W-0/u
T1GSS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1-0
DS40001723D-page 168
PIC12(L)F1571/2
TABLE 19-5:
Name
ANSELA
APFCON
INTCON
OSCSTAT
Bit 6
Bit 5
Bit 4
ANSA4
T1GSEL
Bit 3
Bit 2
Bit 1
Bit 0
ANSA<2:0>
TXCKSEL
P2SEL
Register
on Page
114
P1SEL
110
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
PLLR
OSTS
HFIOFR
HFIOFL
MFIOFR
LFIOFR
HFIOFS
56
(2)
(2)
PIE1
TMR1GIE
ADIE
RCIE
TXIE
TMR2IE
TMR1IE
75
PIR1
TMR1GIF
ADIF
RCIF(2)
TXIF(2)
TMR2IF
TMR1IF
79
TMR1H
Holding Register for the Most Significant Byte of the 16-bit TMR1 Count
163*
TMR1L
Holding Register for the Least Significant Byte of the 16-bit TMR1 Count
163*
TRISA
T1CON
TMR1CS<1:0>
T1GCON
Legend:
*
Note 1:
2:
TMR1GE
T1GPOL
TRISA<5:4>
T1CKPS<1:0>
T1GTM
T1GSPM
(1)
TRISA<2:0>
113
T1SYNC
TMR1ON
T1GGO/
DONE
T1GVAL
T1GSS<1:0>
167
168
= unimplemented location, read as 0. Shaded cells are not used by the Timer1 module.
Page provides register information.
Unimplemented, read as 1.
PIC12(L)F1572 only.
DS40001723D-page 169
PIC12(L)F1571/2
NOTES:
DS40001723D-page 170
PIC12(L)F1571/2
20.0
TIMER2 MODULE
FIGURE 20-1:
T2_match
Prescaler
1:1, 1:4, 1:16, 1:64
Fosc/4
TMR2
To Peripherals
2
T2CKPS<1:0>
Postscaler
1:1 to 1:16
Comparator
set bit
TMR2IF
4
T2OUTPS<3:0>
PR2
FIGURE 20-2:
FOSC/4
1:4
Prescale
0x03
PR2
TMR2
0x00
0x01
0x02
0x03
0x00
0x01
0x02
Pulse Width(1)
T2_match
Note 1: The Pulse Width of T2_match is equal to the scaled input of TMR2.
DS40001723D-page 171
PIC12(L)F1571/2
20.1
Timer2 Operation
20.2
20.3
FIGURE 20-3:
T2_MATCH TIMING
DIAGRAM
Rev. 10-000021A
7/30/2013
Q1
Q2
Q3
Q4
Q1
FOSC
TCY1
FOSC/4
T2_match
TMR2 = 0
TMR2 = PR2
match
PRESCALE = 1:1
(T2CKPS<1:0> = 00)
TCY1
TCY2 ...
...
T2_match
TCYX
...
FOSC/4
Timer2 Interrupt
Timer2 Output
TMR2 = PR2
match
TMR2 = 0
PRESCALE = 1:X
(T2CKPS<1:0> = 01,10,11)
20.4
DS40001723D-page 172
PIC12(L)F1571/2
20.5
REGISTER 20-1:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
T2OUTPS<3:0>
R/W-0/0
R/W-0/0
TMR2ON
R/W-0/0
T2CKPS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-3
bit 2
bit 1-0
TABLE 20-1:
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TXIE(1)
TMR2IE
TMR1IE
75
TXIF(1)
TMR2IF
TMR1IF
78
PIE1
TMR1GIE
ADIE
RCIE(1)
PIR1
TMR1GIF
ADIF
RCIF(1)
PR2
T2CON
TMR2
T2OUTPS<3:0>
171*
TMR2ON
T2CKPS<1:0>
173
171*
Legend: = unimplemented location, read as 0. Shaded cells are not used for Timer2 module.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 173
PIC12(L)F1571/2
NOTES:
DS40001723D-page 174
PIC12(L)F1571/2
21.0
ENHANCED UNIVERSAL
SYNCHRONOUS
ASYNCHRONOUS RECEIVER
TRANSMITTER (EUSART)
FIGURE 21-1:
Data bus
TXIE
Interrupt
TXREG register
TXIF
8
MSb
LSb
(8)
TX/CK
Pin Buffer
and Control
TXEN
Baud Rate Generator
TRMT
FOSC
TX9
BRG16
TX9D
+1
Multiplier
x4
x16
x64
SYNC
1 x 0 0
BRGH
x 1 1 0
BRG16
x 1 0 1
SPBRGH SPBRGL
DS40001723D-page 175
PIC12(L)F1571/2
FIGURE 21-2:
CREN
OERR
RCIDL
SPEN
RSR Register
MSb
RX/DT pin
Pin Buffer
and Control
Baud Rate Generator
Data
Recovery
FOSC
Stop (8)
LSb
1
Start
n
RX9
BRG16
+1
Multiplier
x4
x16
x64
SYNC
1 x 0 0
BRGH
x 1 1 0
BRG16
x 1 0 1
SPBRGH SPBRGL
FIFO
FERR
RX9D
RCREG Register
8
Data Bus
RCIF
RCIE
Interrupt
DS40001723D-page 176
PIC12(L)F1571/2
21.1
21.1.1.2
Transmitting Data
21.1.1.3
21.1.1
21.1.1.4
EUSART ASYNCHRONOUS
TRANSMITTER
21.1.1.1
DS40001723D-page 177
PIC12(L)F1571/2
21.1.1.5
TSR Status
21.1.1.7
1.
2.
3.
21.1.1.6
4.
5.
6.
7.
8.
FIGURE 21-3:
ASYNCHRONOUS TRANSMISSION
Write to TXREG
Word 1
BRG Output
(Shift Clock)
Start bit
TX/CK Pin
bit 0
bit 1
bit 7/8
Stop bit
Word 1
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
Word 1
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
FIGURE 21-4:
Write to TXREG
BRG Output
(Shift Clock)
Word 1
Word 2
Start bit
TX/CK Pin
bit 0
1 TCY
TXIF bit
(Transmit Buffer
Reg. Empty Flag)
bit 1
Word 1
bit 7/8
Stop bit
Start bit
Word 2
bit 0
1 TCY
Word 1
Transmit Shift Reg.
Word 2
Transmit Shift Reg.
TRMT bit
(Transmit Shift
Reg. Empty Flag)
Note: This timing diagram shows two consecutive transmissions.
DS40001723D-page 178
PIC12(L)F1571/2
TABLE 21-1:
Name
BAUDCON
INTCON
PIE1
PIR1
RCSTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
TMR1GIF
ADIF
(1)
RCIF
TXIF
(1)
TMR2IF
TMR1IF
78
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
185*
SPBRGL
BRG<7:0>
187*
SPBRGH
BRG<15:8>
187*
TXREG
TXSTA
TX9
TXEN
177
SYNC
SENDB
BRGH
TRMT
TX9D
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for asynchronous transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 179
PIC12(L)F1571/2
21.1.2
EUSART ASYNCHRONOUS
RECEIVER
21.1.2.1
21.1.2.2
Receiving Data
21.1.2.3
Receive Interrupts
DS40001723D-page 180
PIC12(L)F1571/2
21.1.2.4
21.1.2.5
21.1.2.6
21.1.2.7
Address Detection
DS40001723D-page 181
PIC12(L)F1571/2
21.1.2.8
21.1.2.9
1.
FIGURE 21-5:
ASYNCHRONOUS RECEPTION
Start
bit
RX/DT Pin
bit 0
bit 1
Start
bit
Word 1
RCREG
bit 0
Start
bit
bit 7/8
Stop
bit
Word 2
RCREG
RCIDL
Read Rcv
Buffer Reg. (RCREG)
RCIF
(Interrupt Flag)
OERR bit
CREN
Note:
This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
DS40001723D-page 182
PIC12(L)F1571/2
TABLE 21-2:
Name
BAUDCON
INTCON
PIE1
PIR1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
ADIF
(1)
(1)
TMR2IF
TMR1IF
TMR1GIF
RCIF
RCREG
TXIF
RCSTA
SPEN
RX9
SREN
CREN
SPBRGL
FERR
OERR
RX9D
BRG<7:0>
SPBRGH
TXSTA
ADDEN
TX9
TXEN
SYNC
SENDB
185*
187*
BRG<15:8>
CSRC
78
180*
187*
BRGH
TRMT
TX9D
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for asynchronous reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
21.2
DS40001723D-page 183
PIC12(L)F1571/2
21.3
REGISTER 21-1:
R/W-/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-1/1
R/W-0/0
CSRC
TX9
TXEN(1)
SYNC
SENDB
BRGH
TRMT
TX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001723D-page 184
PIC12(L)F1571/2
REGISTER 21-2:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R-0/0
R-0/0
R-0/0
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
DS40001723D-page 185
PIC12(L)F1571/2
REGISTER 21-3:
R-0/0
R-1/1
U-0
R/W-0/0
R/W-0/0
U-0
R/W-0/0
R/W-0/0
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
Unimplemented: Read as 0
bit 4
bit 3
bit 2
Unimplemented: Read as 0
bit 1
bit 0
DS40001723D-page 186
PIC12(L)F1571/2
21.4
EXAMPLE 21-1:
CALCULATING BAUD
RATE ERROR
DS40001723D-page 187
PIC12(L)F1571/2
TABLE 21-3:
Configuration Bits
SYNC
BRG16
BRGH
BRG/EUSART Mode
8-bit/Asynchronous
8-bit/Asynchronous
16-bit/Asynchronous
16-bit/Asynchronous
8-bit/Synchronous
16-bit/Synchronous
FOSC/[16 (n+1)]
FOSC/[4 (n+1)]
TABLE 21-4:
Name
BAUDCON
RCSTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
SPBRGL
BRG<7:0>
SPBRGH
TXSTA
BRG<15:8>
CSRC
TX9
TXEN
SYNC
SENDB
185
187*
187*
BRGH
TRMT
TX9D
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for the Baud Rate Generator.
* Page provides register information.
DS40001723D-page 188
PIC12(L)F1571/2
TABLE 21-5:
BAUD
RATE
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300
1200
1221
1.73
255
1200
0.00
239
1202
0.16
207
1200
0.00
143
2400
2404
0.16
129
2400
0.00
119
2404
0.16
103
2400
0.00
71
9600
9470
-1.36
32
9600
0.00
29
9615
0.16
25
9600
0.00
17
10417
10417
0.00
29
10286
-1.26
27
10417
0.00
23
10165
-2.42
16
19.2k
19.53k
1.73
15
19.20k
0.00
14
19.23k
0.16
12
19.20k
0.00
57.6k
57.60k
0.00
57.60k
0.00
115.2k
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
300
300
0.16
207
300
0.00
191
300
0.16
51
1200
1202
0.16
103
1202
0.16
51
1200
0.00
47
1202
0.16
12
2400
2404
0.16
51
2404
0.16
25
2400
0.00
23
9600
9615
0.16
12
9600
0.00
10417
10417
0.00
11
10417
0.00
19.2k
19.20k
0.00
57.6k
57.60k
0.00
115.2k
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
300
1200
2400
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.82k
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.64k
-1.36
10
115.2k
0.00
111.1k
-3.55
115.2k
0.00
DS40001723D-page 189
PIC12(L)F1571/2
TABLE 21-5:
BAUD
RATE
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
207
300
300
0.16
1200
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19231
0.16
25
19.23k
0.16
12
19.2k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300
300.0
-0.01
4166
300.0
0.00
3839
300.03
0.01
3332
300.0
0.00
2303
1200
1200
-0.03
1041
1200
0.00
959
1200.5
0.04
832
1200
0.00
575
2400
2399
-0.03
520
2400
0.00
479
2398
-0.08
416
2400
0.00
287
9600
9615
0.16
129
9600
0.00
119
9615
0.16
103
9600
0.00
71
10417
10417
0.00
119
10378
-0.37
110
10417
0.00
95
10473
0.53
65
19.2k
19.23k
0.16
64
19.20k
0.00
59
19.23k
0.16
51
19.20k
0.00
35
57.6k
56.818
-1.36
21
57.60k
0.00
19
58.82k
2.12
16
57.60k
0.00
11
115.2k
113.636
-1.36
10
115.2k
0.00
111.11k
-3.55
115.2k
0.00
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300
299.9
-0.02
1666
300.1
0.04
832
300.0
0.00
767
300.5
0.16
207
1200
1199
-0.08
416
1202
0.16
207
1200
0.00
191
1202
0.16
51
2400
2404
0.16
207
2404
0.16
103
2400
0.00
95
2404
0.16
25
9600
9615
0.16
51
9615
0.16
25
9600
0.00
23
10417
10417
0.00
47
10417
0.00
23
10473
0.53
21
10417
0.00
19.2k
19.23k
0.16
25
19.23k
0.16
12
19.20k
0.00
11
57.6k
55556
-3.55
57.60k
0.00
115.2k
115.2k
0.00
DS40001723D-page 190
PIC12(L)F1571/2
TABLE 21-5:
BAUD
RATE
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300
300.0
0.00
16665
300.0
0.00
15359
300.0
0.00
13332
300.0
0.00
9215
1200
1200
-0.01
4166
1200
0.00
3839
1200.1
0.01
3332
1200
0.00
2303
2400
2400
0.02
2082
2400
0.00
1919
2399.5
-0.02
1666
2400
0.00
1151
9600
9597
-0.03
520
9600
0.00
479
9592
-0.08
416
9600
0.00
287
10417
10417
0.00
479
10425
0.08
441
10417
0.00
383
10433
0.16
264
19.2k
19.23k
0.16
259
19.20k
0.00
239
19.23k
0.16
207
19.20k
0.00
143
57.6k
57.47k
-0.22
86
57.60k
0.00
79
57.97k
0.64
68
57.60k
0.00
47
115.2k
116.3k
0.94
42
115.2k
0.00
39
114.29k
-0.79
34
115.2k
0.00
23
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
Actual
Rate
%
Error
SPBRG
Value
(decimal)
300
300.0
0.00
6666
300.0
0.01
3332
300.0
0.00
3071
300.1
0.04
832
1200
1200
-0.02
1666
1200
0.04
832
1200
0.00
767
1202
0.16
207
2400
2401
0.04
832
2398
0.08
416
2400
0.00
383
2404
0.16
103
9600
9615
0.16
207
9615
0.16
103
9600
0.00
95
9615
0.16
25
10417
10417
191
10417
0.00
95
10473
0.53
87
10417
0.00
23
19.2k
19.23k
0.16
103
19.23k
0.16
51
19.20k
0.00
47
19.23k
0.16
12
57.6k
57.14k
-0.79
34
58.82k
2.12
16
57.60k
0.00
15
115.2k
117.6k
2.12
16
111.1k
-3.55
115.2k
0.00
DS40001723D-page 191
PIC12(L)F1571/2
21.4.1
AUTO-BAUD DETECT
FIGURE 21-6:
BRG Value
TABLE 21-6:
BRG16
BRGH
BRG Base
Clock
BRG ABD
Clock
FOSC/64
FOSC/512
FOSC/16
FOSC/128
FOSC/16
FOSC/128
FOSC/4
FOSC/32
1
Note:
0000h
001Ch
Start
RX Pin
Edge #1
bit 1
bit 0
Edge #2
bit 3
bit 2
Edge #3
bit 5
bit 4
Edge #4
bit 7
bit 6
Edge #5
Stop bit
BRG Clock
Auto Cleared
Set by User
ABDEN bit
RCIDL
RCIF bit
(Interrupt)
Read
RCREG
SPBRGL
XXh
1Ch
SPBRGH
XXh
00h
Note 1:
The ABD sequence requires the EUSART module to be configured in Asynchronous mode.
DS40001723D-page 192
PIC12(L)F1571/2
21.4.2
AUTO-BAUD OVERFLOW
21.4.3.1
Special Considerations
Break Character
1.
2.
3.
21.4.3
AUTO-WAKE-UP ON BREAK
DS40001723D-page 193
PIC12(L)F1571/2
FIGURE 21-7:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1Q2 Q3 Q4
OSC1
WUE bit
Auto-Cleared
RX/DT
Line
RCIF
Note 1:
FIGURE 21-8:
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Q1
Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
OSC1
WUE bit
Auto Cleared
RX/DT
Line
Note 1
RCIF
Sleep Command Executed
Note 1:
2:
Sleep Ends
If the wake-up event requires long oscillator warm-up time, the automatic clearing of the WUE bit can occur while the stposc signal
is still active. This sequence should not depend on the presence of Q clocks.
The EUSART remains in Idle while the WUE bit is set.
DS40001723D-page 194
PIC12(L)F1571/2
21.4.4
21.4.4.1
21.4.5
FIGURE 21-9:
Write to TXREG
BRG Output
(Shift Clock)
TX (pin)
Start bit
bit 0
bit 1
bit 11
Stop bit
Break
TXIF bit
(Transmit
Interrupt Flag)
TRMT bit
(Transmit Shift
Empty Flag)
SENDB
(send Break
control bit)
Auto Cleared
DS40001723D-page 195
PIC12(L)F1571/2
21.5
21.5.1
SYNC = 1
CSRC = 1
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
21.5.1.1
Master Clock
DS40001723D-page 196
21.5.1.2
Clock Polarity
21.5.1.3
21.5.1.4
1.
2.
3.
4.
5.
6.
7.
8.
PIC12(L)F1571/2
FIGURE 21-10:
SYNCHRONOUS TRANSMISSION
RX/DT
Pin
bit 0
bit 1
bit 2
bit 7
bit 0
TX/CK Pin
(SCKP = 0)
bit 7
bit 1
Word 1
Word 2
TX/CK Pin
(SCKP = 1)
Write to
TXREG Reg
Write Word 1
Write Word 2
TXIF bit
(Interrupt Flag)
TRMT bit
TXEN bit
Note:
FIGURE 21-11:
RX/DT Pin
bit 0
bit 1
bit 2
bit 6
bit 7
TX/CK Pin
Write to
TXREG Reg.
TXIF bit
TRMT bit
TXEN bit
TABLE 21-7:
Name
BAUDCON
INTCON
PIE1
PIR1
RCSTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
TMR1GIF
ADIF
(1)
RCIF
TXIF
(1)
TMR2IF
TMR1IF
78
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
185
SPBRGL
BRG<7:0>
187*
SPBRGH
BRG<15:8>
187*
TXREG
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
177*
TRMT
TX9D
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous master transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 197
PIC12(L)F1571/2
21.5.1.5
21.5.1.6
Slave Clock
DS40001723D-page 198
21.5.1.7
21.5.1.8
21.5.1.9
1.
PIC12(L)F1571/2
FIGURE 21-12:
RX/DT
Pin
bit 0
bit 1
bit 2
bit 3
bit 4
bit 5
bit 6
bit 7
TX/CK Pin
(SCKP = 0)
TX/CK Pin
(SCKP = 1)
Write to
SREN bit
SREN bit
CREN bit 0
RCIF bit
(Interrupt)
Read
RCREG
Note:
Timing diagram demonstrates Sync Master mode with bit SREN = 1 and bit BRGH = 0.
TABLE 21-8:
Name
BAUDCON
INTCON
PIE1
PIR1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
ADIF
RCIF(1)
TXIF(1)
TMR2IF
TMR1IF
TMR1GIF
RCREG
RCSTA
RX9
SREN
SPBRGL
ADDEN
FERR
OERR
RX9D
BRG<7:0>
SPBRGH
TXSTA
CREN
TX9
TXEN
SYNC
SENDB
185
187*
BRG<15:8>
CSRC
78
180*
187*
BRGH
TRMT
TX9D
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous master reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 199
PIC12(L)F1571/2
21.5.2
1.
SYNC = 1
CSRC = 0
SREN = 0 (for transmit); SREN = 1 (for receive)
CREN = 0 (for transmit); CREN = 1 (for receive)
SPEN = 1
2.
3.
4.
21.5.2.1
5.
21.5.2.2
1.
2.
3.
4.
5.
6.
7.
8.
TABLE 21-9:
Name
BAUDCON
INTCON
PIE1
PIR1
RCSTA
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ABDOVF
RCIDL
SCKP
BRG16
WUE
ABDEN
186
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
74
TMR1GIE
ADIE
RCIE(1)
TXIE(1)
TMR2IE
TMR1IE
75
TMR1GIF
ADIF
(1)
RCIF
TXIF
(1)
TMR2IF
TMR1IF
78
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
185
CSRC
TX9
TXEN
TRMT
TX9D
TXREG
TXSTA
SENDB
BRGH
177*
184
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous slave transmission.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 200
PIC12(L)F1571/2
21.5.2.3
21.5.2.4
1.
2.
3.
Sleep
CREN bit is always set, therefore, the receiver is
never Idle
SREN bit, which is a dont care in Slave mode
A character may be received while in Sleep mode by
setting the CREN bit prior to entering Sleep. Once the
word is received, the RSR register will transfer the data
to the RCREG register. If the RCIE enable bit is set, the
interrupt generated will wake the device from Sleep
and execute the next instruction. If the GIE bit is also
set, the program will branch to the interrupt vector.
4.
5.
6.
7.
8.
9.
Bit 7
Bit 6
ABDOVF
GIE
Bit 2
Bit 1
Bit 0
Register
on Page
BRG16
WUE
ABDEN
186
IOCIE
TMR0IF
INTF
IOCIF
74
TXIE(1)
TMR2IE
TMR1IE
75
TXIF(1)
TMR2IF
TMR1IF
78
Bit 5
Bit 4
Bit 3
RCIDL
SCKP
PEIE
TMR0IE
INTE
PIE1
TMR1GIE
ADIE
RCIE(1)
PIR1
TMR1GIF
ADIF
RCIF(1)
RCSTA
SPEN
RX9
SREN
CREN
ADDEN
FERR
OERR
RX9D
185
TXSTA
CSRC
TX9
TXEN
SYNC
SENDB
BRGH
TRMT
TX9D
184
RCREG
180*
Legend: = unimplemented location, read as 0. Shaded cells are not used for synchronous slave reception.
* Page provides register information.
Note 1: PIC12(L)F1572 only.
DS40001723D-page 201
PIC12(L)F1571/2
NOTES:
DS40001723D-page 202
PIC12(L)F1571/2
22.0
16-BIT PULSE-WIDTH
MODULATION (PWM) MODULE
PWMxPH register
PWMxDC register
PWMxPR register
PWMxOF register
Independent Run
Slave Run with Synchronous Start
One-Shot Slave with Synchronous Start
Continuous Run Slave with Synchronous Start
and Timer Reset
Standard
Set On Match
Toggle On Match
Center-Aligned
FIGURE 22-1:
PWM Control
Unit
DCx_match
OF3_match(1)
11
OF2_match(1)
10
(1)
OF1_match
Reserved
Rev. 10-000152A
4/21/2014
Q4
PWMxOUT
CK
PWMxPOL
PWMx_output
OF_match
01
Offset
Control
PRx_match
To Peripherals
PWMxOE
00
PWMx
OFM<1:0>
E
OFS
Comparator
PWM_clock
PRx_match
set PRIF
PWMxPR
Comparator
Note 1:
PHx_match
set PHIF
PWMxPH
U/D
PWMxTMR
TRIS Control
Comparator
OFx_match
set OFIF
PWMxOF
Comparator
DCx_match
set DCIF
PWMxDC
A PWM module cannot trigger from its own offset match event.
The input corresponding to a PWM modules own offset match is reserved.
DS40001723D-page 203
PIC12(L)F1571/2
FIGURE 22-2:
LD3_trigger(1)
11
(1)
10
LD1_trigger(1)
01
Reserved
00
LD2_trigger
1
0
PWMxLDS
LDx_trigger
22.1
PWM_clock
Fundamental Operation
FIGURE 22-3:
PWMxCS<1:0>
Note:
PRx_match
PWMxLDT
Note
PWMxLDA(2)
22.1.1
FOSC
00
HFINTOSC
01
LFINTOSC
10
Reserved
11
PWMxPS<2:0>
Prescaler
PWMx_clock
22.1.2
DS40001723D-page 204
PIC12(L)F1571/2
22.2
PWM Modes
22.2.1
STANDARD MODE
EQUATION 22-1:
PWM PERIOD IN
STANDARD MODE
PWMxPR + 1 Prescale
Period = -------------------------------------------------------------------PWMxCLK
EQUATION 22-2:
PWMxDC PWMx PH
Duty Cycle = -----------------------------------------------------------------
PWMxPR + 1
22.2.2
22.2.3
The Toggle On Match mode (MODE<1:0> = 10) generates a 50% duty cycle PWM with a period twice as long
as that computed for the Standard PWM mode. Duty
cycle count has no effect in this mode. The phase count
determines how many PWMxTMR periods, after a
period event, the output will toggle.
Writes to the OUT bit of the PWMxCON register will
have no effect in this mode.
A detailed timing diagram for Toggle On Match mode is
shown in Figure 22-6.
22.2.4
CENTER-ALIGNED MODE
EQUATION 22-3:
PWM PERIOD IN
CENTER-ALIGNED MODE
PWMxPR + 1 Prescale 2
Period = --------------------------------------------------------------------------PWMxCLK
Equation 22-4 is used to calculate the PWM duty cycle
ratio in Center-Aligned mode.
EQUATION 22-4:
PWMxDC 2
Duty Cycle = ------------------------------------------------ PWMx PR + 1 2
Writes to the OUT bit will have no effect in this mode.
A detailed timing diagram for Center-Aligned mode is
shown in Figure 22-7.
DS40001723D-page 205
Period
Duty Cycle
Phase
PWMxCLK
PWMxPR
10
PWMxPH
PWMxDC
PWMxTMR
10
PWMxOUT
FIGURE 22-5:
Rev. 10-000143A
9/5/2013
Period
Phase
PWMxCLK
PWMxPR
10
PWMxPH
PWMxTMR
PWMxOUT
10
PIC12(L)F1571/2
DS40001723D-page 206
FIGURE 22-4:
FIGURE 22-6:
Rev. 10-000144A
9/5/2013
Period
Phase
PWMxCLK
PWMxPR
10
PWMxPH
PWMxTMR
10
PWMxOUT
FIGURE 22-7:
Period
Period
PWMxPR
PWMxPR
66
PWMxDC
PWMxDC
44
DS40001723D-page 207
PWMxTMR
PWMxTMR
PWMxOUT
PWMxOUT
00
11
22
33
44
55
66
66
55
44
33
22
11
00
00
11
22
33
PIC12(L)F1571/2
Duty
DutyCycle
Cycle
PWMxCLK
PWMxCLK
PIC12(L)F1571/2
22.3
Offset Modes
The Offset modes provide the means to adjust the waveform of a slave PWM module relative to the waveform of
a master PWM module in the same device.
22.3.1
22.3.2
22.3.3
22.3.4
22.3.5
OFFSET MATCH IN
CENTER-ALIGNED MODE
DS40001723D-page 208
FIGURE 22-8:
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
PWMxDC
PWMxOF
PWMxTMR
10
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
DS40001723D-page 209
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
Note: PWMx = Master, PWMy = Slave
PIC12(L)F1571/2
PWMyTMR
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
PWMxDC
PWMxOF
PWMxTMR
10
PWMxOUT
OFx_match
PWMyTMR
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
Note: Master = PWMx, Slave = PWMy
PIC12(L)F1571/2
DS40001723D-page 210
FIGURE 22-9:
FIGURE 22-10:
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
PWMxDC
PWMxOF
PWMxTMR
10
PWMxOUT
OFx_match
PWMyTMR
PWMyPH
PWMyDC
PWMyOUT
Note: Master = PWMx, Slave = PWMy
DS40001723D-page 211
PIC12(L)F1571/2
PWMyPR
CONTINUOUS SLAVE RUN MODE WITH IMMEDIATE RESET AND SYNC START TIMING DIAGRAM
Period
Duty Cycle
Phase
Offset
PWMxCLK
PWMxPR
10
PWMxPH
PWMxDC
PWMxOF
PWMxTMR
10
PWMxOUT
OFx_match
PWMyTMR
PWMyPR
PWMyPH
PWMyDC
PWMyOUT
PIC12(L)F1571/2
DS40001723D-page 212
FIGURE 22-11:
FIGURE 22-12:
Period
Duty Cycle
Offset
PWMxCLK
PWMxPR
PWMxDC
PWMxOF
PWMxTMR
PWMxOUT
OFx_match
PHx_match
DCx_match
PRx_match
PWMyTMR
PWMyDC
PWMyOUT
Note: Master = PWMx, Slave = PWMy
DS40001723D-page 213
PIC12(L)F1571/2
PWMyPR
Period
Duty Cycle
Offset
PWMxCLK
PWMxPR
PWMxDC
PWMxOF
PWMxTMR
PWMxOUT
OF5_match
PH5_match
DC5_match
PR5_match
PWMyTMR
PWMyPR
PWMyDC
PWMyOUT
Note: Master = PWMx, Slave = PWMy
PIC12(L)F1571/2
DS40001723D-page 214
FIGURE 22-13:
PIC12(L)F1571/2
22.4
Reload Operation
22.4.2
Immediate
Triggered
The LDT bit of the PWMxLDCON register controls the
arming method. Both methods require the LDA bit to be
set. All four buffer pairs will load simultaneously at the
loading event.
22.4.1
IMMEDIATE RELOAD
TRIGGERED RELOAD
22.5
22.6
Interrupts
DS40001723D-page 215
PIC12(L)F1571/2
22.7
TABLE 22-1:
REGISTER 22-1:
Peripheral
PWM1
PWM1
PWM2
PWM2
PWM3
PWM3
R/W-0/0
R/W-0/0
R/HS/HC-0/0
R/W-0/0
EN
OE
OUT
POL
R/W-0/0
R/W-0/0
MODE<1:0>
U-0
U-0
bit 7
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3-2
bit 1-0
Unimplemented: Read as 0
DS40001723D-page 216
PIC12(L)F1571/2
REGISTER 22-2:
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
OFIE
PHIE
DCIE
PRIE
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
DS40001723D-page 217
PIC12(L)F1571/2
REGISTER 22-3:
U-0
U-0
U-0
U-0
R/W/HS-0/0
R/W/HS-0/0
OFIF
PHIF
R/W/HS-0/0 R/W/HS-0/0
DCIF
bit 7
PRIF
bit 0
Legend:
HC = Hardware Clearable bit
R = Readable bit
W = Writable bit
1 = Bit is set
0 = Bit is cleared
bit 7-4
Unimplemented: Read as 0
bit 3
bit 2
bit 1
bit 0
Note 1:
DS40001723D-page 218
PIC12(L)F1571/2
REGISTER 22-4:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
PS<2:0>
U-0
U-0
R/W-0/0
bit 7
R/W-0/0
CS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-4
bit 3-2
Unimplemented: Read as 0
bit 1-0
DS40001723D-page 219
PIC12(L)F1571/2
REGISTER 22-5:
R/W-0/0
R/W-0/0
U-0
U-0
U-0
U-0
LDA(1)
LDT
R/W-0/0
bit 7
R/W-0/0
LDS<1:0>
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-2
Unimplemented: Read as 0
bit 1-0
Note 1:
2:
This bit is cleared by the module after a reload operation. It can be cleared in software to clear an existing
arming event.
The LD_trigger corresponding to the PWM used becomes reserved.
DS40001723D-page 220
PIC12(L)F1571/2
REGISTER 22-6:
U-0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
OFO(1)
OFM<1:0>
R/W-0/0
R/W-0/0
OFS<1:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
Unimplemented: Read as 0
bit 6-5
bit 4
bit 3-2
Unimplemented: Read as 0
bit 1-0
Note 1:
DS40001723D-page 221
PIC12(L)F1571/2
REGISTER 22-7:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PH<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
REGISTER 22-8:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PH<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 222
PIC12(L)F1571/2
REGISTER 22-9:
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DC<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
DC<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 223
PIC12(L)F1571/2
REGISTER 22-11: PWMxPRH: PWMx PERIOD COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PR<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
PR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 224
PIC12(L)F1571/2
REGISTER 22-13: PWMxOFH: PWMx OFFSET COUNT HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
OF<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
OF<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 225
PIC12(L)F1571/2
REGISTER 22-15: PWMxTMRH: PWMx TIMER HIGH REGISTER
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
TMR<15:8>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
TMR<7:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-0
DS40001723D-page 226
PIC12(L)F1571/2
Note:
There are no long and short bit name variants for the following three mirror registers
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
PWM3EN_A
PWM2EN_A
PWM1EN_A
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
U-0
U-0
U-0
U-0
R/W-0/0
PWM3LDA_A
R/W-0/0
R/W-0/0
PWM2LDA_A PWM1LDA_A
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
U-0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
R/W-0/0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-3
Unimplemented: Read as 0
bit 2-0
DS40001723D-page 227
PIC12(L)F1571/2
TABLE 22-2:
Name
OSCCON
Bit 6
Bit 5
SPLLEN
Bit 4
Bit 3
Bit 2
IRCF<3:0>
Bit 1
Bit 0
SCS<1:0>
Register
on Page
55
PIE3
PWM3IE
PWM2IE
PWM1IE
PIR3
PWM3IF
PWM2IF
PWM1IF
80
PWMEN
PWM3EN_A
PWM2EN_A
PWM1EN_A
227
PWMLD
PWM3LDA_A
PWM2LDA_A
PWM1LDA_A
227
PWMOUT
227
77
PWM1PHL
PH<7:0>
222
PWM1PHH
PH<15:8>
222
PWM1DCL
DC<7:0>
223
PWM1DCH
DC<15:8>
223
PWM1PRH
PR<7:0>
224
PWM1PRL
PR<15:8>
224
PWM1OFH
OF<7:0>
225
PWM1OFL
OF<15:8>
225
PWM1TMRH
TMR<7:0>
226
PWM1TMRL
TMR<15:8>
226
PWM1CON
EN
OE
OUT
POL
PWM1INTE
OFIE
PWM1INTF
PWM1CLKCON
PWM1LDCON
LDA
PWM1OFCON
216
PHIE
DCIE
PRIE
217
OFIF
PHIF
DCIF
OFO
PS<2:0>
LDT
OFM<1:0>
MODE<1:0>
PRIF
218
CS<1:0>
219
LDS<1:0>
220
OFS<1:0>
221
PWM2PHL
PH<7:0>
222
PWM2PHH
PH<15:8>
222
PWM2DCL
DC<7:0>
223
PWM2DCH
DC<15:8>
223
PWM2PRL
PR<7:0>
224
PWM2PRH
PR<15:8>
224
PWM2OFL
OF<7:0>
225
PWM2OFH
OF<15:8>
225
PWM2TMRL
TMR<7:0>
226
PWM2TMRH
TMR<15:8>
226
PWM2CON
EN
OE
OUT
POL
PWM2INTE
OFIE
PWM2INTF
PWM2CLKCON
PWM2LDCON
LDA
PWM2OFCON
216
PHIE
DCIE
PRIE
217
OFIF
PHIF
DCIF
OFO
PS<2:0>
LDT
OFM<1:0>
MODE<1:0>
PRIF
218
CS<1:0>
219
LDS<1:0>
220
OFS<1:0>
221
PWM3PHL
PH<7:0>
222
PWM3PHH
PH<15:8>
222
PWM3DCL
DC<7:0>
223
PWM3DCH
DC<15:8>
223
PWM3PRL
PR<7:0>
224
PWM3PRH
PR<15:8>
224
PWM3OFL
OF<7:0>
225
PWM3OFH
OF<15:8>
225
PWM3TMRL
TMR<7:0>
226
PWM3TMRH
TMR<15:8>
PWM3CON
EN
OE
OUT
POL
226
MODE<1:0>
216
Legend: = unimplemented location, read as 0. Shaded cells are not used by the PWM.
DS40001723D-page 228
PIC12(L)F1571/2
TABLE 22-2:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
PWM3INTE
OFIE
PHIE
DCIE
PRIE
217
PWM3INTF
OFIF
PHIF
DCIF
PRIF
PWM3CLKCON
OFO
Name
PS<2:0>
PWM3LDCON
LDA
PWM3OFCON
LDT
OFM<1:0>
218
CS<1:0>
219
LDS<1:0>
220
OFS<1:0>
221
Legend: = unimplemented location, read as 0. Shaded cells are not used by the PWM.
TABLE 22-3:
Name
CONFIG1
Bit -/6
Bit 13/5
Bit 12/4
Bit 11/3
CLKOUTEN
13:8
7:0
CP
MCLRE
PWRTE
WDTE<1:0>
Bit 10/2
Bit 9/1
Bit 8/0
BOREN<1:0>
FOSC<1:0>
Register
on Page
42
Legend: = unimplemented location, read as 0. Shaded cells are not used by clock sources.
DS40001723D-page 229
PIC12(L)F1571/2
NOTES:
DS40001723D-page 230
PIC12(L)F1571/2
23.0
COMPLEMENTARY WAVEFORM
GENERATOR (CWG) MODULE
23.3
TABLE 23-1:
23.1
Fundamental Operation
23.2
Clock Source
SELECTABLE INPUT
SOURCES
Source Peripheral
Signal Name
Comparator C1
C1OUT_sync
PWM1
PWM1_output
PWM2
PWM2_output
PWM3
PWM3_output
23.4
Output Control
23.4.1
OUTPUT ENABLES
23.4.2
POLARITY CONTROL
DS40001723D-page 231
Rev. 10-000123D
7/10/2015
GxASDLA
00
GxCS
FOSC
10
1'
11
CWGxDBR
cwg_clock
GxASDLA = 01
HFINTOSC
GxIS
0'
C1OUT_async
Reserved
PWM1_out
PWM2_out
PWM3_out
Reserved
Reserved
Reserved
R
S
TRISx
GxOEA
GxPOLA
Input Source
CWGxDBF
R
GxOEB
EN
GxPOLB
00
R
GxARSEN
10
1'
11
shutdown
Q
GxASDLB
0'
GxASE
Auto-Shutdown
Source
C1OUT_async
GxASDSC1
CWGxA
EN
set dominate
2
GxASDLB = 01
TRISx
CWGxB
PIC12(L)F1571/2
DS40001723D-page 232
FIGURE 23-1:
PIC12(L)F1571/2
FIGURE 23-2:
cwg_clock
PWM1
CWGxA
Rising Edge
Dead Band
Rising Edge
Rising Edge Dead Band
Falling Edge Dead Band Dead Band
CWGxB
23.5
Dead-Band Control
23.6
23.7
The CWGxDBR register sets the duration of the deadband interval on the rising edge of the input source
signal. This duration is from 0 to 64 counts of dead band.
Dead band is always counted off the edge on the input
source signal. A count of 0 (zero), indicates that no
dead band is present.
If the input source signal is not present for enough time
for the count to be completed, no output will be seen on
the respective output.
DS40001723D-page 233
cwg_clock
Input Source
CWGxA
CWGxB
FIGURE 23-4:
DEAD-BAND OPERATION, CWGxDBR = 03h, CWGxDBF = 04h, SOURCE SHORTER THAN DEAD BAND
cwg_clock
Input Source
CWGxA
CWGxB
Source Shorter than Dead Band
PIC12(L)F1571/2
DS40001723D-page 234
FIGURE 23-3:
PIC12(L)F1571/2
23.8
Dead-Band Uncertainty
23.9
Auto-Shutdown Control
EQUATION 23-1:
DEAD-BAND
UNCERTAINTY
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
23.9.1
SHUTDOWN
Software generated
External Input
23.9.1.1
Example:
Fcwg_clock = 16 MHz
23.9.1.2
Therefore:
1
TDEADBAND_UNCERTAINTY = ----------------------------Fcwg_clock
1
= ------------------16 MHz
= 62.5ns
DS40001723D-page 235
PIC12(L)F1571/2
23.10 Operation During Sleep
23.11.1
2.
3.
4.
5.
6.
7.
8.
9.
Ensure that the TRISx control bits corresponding to CWGxA and CWGxB are set so that both
are configured as inputs.
Clear the GxEN bit if not already cleared.
Set desired dead-band times with the CWGxDBR
and CWGxDBF registers.
Set up the following controls in the CWGxCON2
auto-shutdown register:
Select desired shutdown source.
Select both output overrides to the desired
levels (this is necessary even if not using
auto-shutdown because start-up will be from
a shutdown state).
Set the GxASE bit and clear the GxARSEN
bit.
Select the desired input source using the
CWGxCON1 register.
Configure the following controls in the
CWGxCON0 register:
Select desired clock source.
Select the desired output polarities.
Set the output enables for the outputs to be
used.
Set the GxEN bit.
Clear the TRISx control bits corresponding to
CWGxA and CWGxB to be used to configure
those pins as outputs.
If auto-restart is to be used, set the GxARSEN
bit and the GxASE bit will be cleared automatically. Otherwise, clear the GxASE bit to start the
CWG.
DS40001723D-page 236
23.11.2
AUTO-SHUTDOWN RESTART
23.11.2.1
23.11.2.2
Auto-Restart
FIGURE 23-5:
CWG Input
Source
Shutdown Source
GxASE
CWG1A
CWG1B
Shutdown
FIGURE 23-6:
CWG Input
Source
GxASE
DS40001723D-page 237
CWG1A
CWG1B
Output Resumes
PIC12(L)F1571/2
Shutdown Source
PIC12(L)F1571/2
23.12 Register Definitions: CWG Control
REGISTER 23-1:
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
R/W-0/0
U-0
U-0
R/W-0/0
GxEN
GxOEB
GxOEA
GxPOLB
GxPOLA
GxCS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-1
Unimplemented: Read as 0
bit 0
DS40001723D-page 238
PIC12(L)F1571/2
REGISTER 23-2:
R/W-x/u
R/W-x/u
R/W-x/u
GxASDLB<1:0>
R/W-x/u
U-0
GxASDLA<1:0>
R/W-0/0
R/W-0/0
R/W-0/0
GxIS<2:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
bit 5-4
bit 3
Unimplemented: Read as 0
bit 2-0
DS40001723D-page 239
PIC12(L)F1571/2
REGISTER 23-3:
R/W-0/0
R/W-0/0
U-0
U-0
U-0
R/W-0/0
R/W-0/0
U-0
GxASE
GxARSEN
GxASDSC1
GxASDSFLT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7
bit 6
bit 5-3
Unimplemented: Read as 0
bit 2
bit 1
bit 0
Unimplemented: Read as 0
DS40001723D-page 240
PIC12(L)F1571/2
REGISTER 23-4:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBR<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
REGISTER 23-5:
U-0
U-0
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
R/W-x/u
CWGxDBF<5:0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
u = Bit is unchanged
x = Bit is unknown
1 = Bit is set
0 = Bit is cleared
bit 7-6
Unimplemented: Read as 0
bit 5-0
DS40001723D-page 241
PIC12(L)F1571/2
TABLE 23-2:
Name
ANSELA
CWG1CON0
CWG1CON1
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ANSA4
ANSA2
ANSA1
ANSA0
114
G1EN
G1OEB
G1CS0
238
G1ASDLB<1:0>
CWG1DBR
TRISA
G1IS<1:0>
G1ASDSC1 G1ASDSFLT
239
CWG1DBF<5:0>
241
CWG1DBR<5:0>
TRISA<5:4>
(1)
TRISA2
240
241
TRISA<1:0>
113
Legend: = unimplemented location, read as 0. Shaded cells are not used by the CWG.
Note 1: Unimplemented, read as 1.
DS40001723D-page 242
PIC12(L)F1571/2
24.0
IN-CIRCUIT SERIAL
PROGRAMMING (ICSP)
24.1
24.2
24.3
FIGURE 24-1:
VDD
ICSPDAT
NC
2 4 6
ICSPCLK
1 3 5
Target
VPP/MCLR
VSS
PC Board
Bottom Side
Pin Description*
1 = VPP/MCLR
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No Connect
DS40001723D-page 243
PIC12(L)F1571/2
FIGURE 24-2:
Pin 1 Indicator
Pin Description*
1 = VPP/MCLR
1
2
3
4
5
6
2 = VDD Target
3 = VSS (ground)
4 = ICSPDAT
5 = ICSPCLK
6 = No connect
FIGURE 24-3:
External
Programming
Signals
Device to be
Programmed
VDD
VDD
VDD
VPP
MCLR/VPP
VSS
VSS
Data
ICSPDAT
Clock
ICSPCLK
To Normal Connections
* Isolation devices (as required).
DS40001723D-page 244
PIC12(L)F1571/2
25.0
25.1
Read-Modify-Write Operations
Byte-Oriented
Bit-Oriented
Literal and Control
TABLE 25-1:
Each instruction is a 14-bit word containing the operation code (opcode) and all required operands. The
opcodes are broken into three broad categories.
OPCODE FIELD
DESCRIPTIONS
Field
mm
Description
Register file address (0x00 to 0x7F).
TABLE 25-2:
ABBREVIATION
DESCRIPTIONS
Field
PC
TO
C
DC
Z
PD
Description
Program Counter
Time-out bit
Carry bit
Digit Carry bit
Zero bit
Power-Down bit
DS40001723D-page 245
PIC12(L)F1571/2
FIGURE 25-1:
d = 0 for destination W
d = 1 for destination f
f = 7-bit file register address
Bit-oriented file register operations
13
10 9
7 6
OPCODE
b (BIT #)
f (FILE #)
General
13
OPCODE
0
k (literal)
k (literal)
0
k (literal)
5 4
0
k (literal)
0
k (literal)
6
n
0
k (literal)
n = appropriate FSR
k = 6-bit immediate value
FSR Increment instructions
13
OPCODE
2 1
0
n m (mode)
n = appropriate FSR
m = 2-bit mode value
OPCODE only
13
0
OPCODE
DS40001723D-page 246
PIC12(L)F1571/2
TABLE 25-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
ADDWF
ADDWFC
ANDWF
ASRF
LSLF
LSRF
CLRF
CLRW
COMF
DECF
INCF
IORWF
MOVF
MOVWF
RLF
RRF
SUBWF
SUBWFB
SWAPF
XORWF
f, d
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f
f, d
f, d
f, d
f, d
f, d
f, d
Add W and f
Add with Carry W and f
AND W with f
Arithmetic Right Shift
Logical Left Shift
Logical Right Shift
Clear f
Clear W
Complement f
Decrement f
Increment f
Inclusive OR W with f
Move f
Move W to f
Rotate Left f through Carry
Rotate Right f through Carry
Subtract W from f
Subtract with Borrow W from f
Swap nibbles in f
Exclusive OR W with f
DECFSZ
INCFSZ
f, d
f, d
Decrement f, Skip if 0
Increment f, Skip if 0
BCF
BSF
f, b
f, b
Bit Clear f
Bit Set f
BTFSC
BTFSS
f, b
f, b
ADDLW
ANDLW
IORLW
MOVLB
MOVLP
MOVLW
SUBLW
XORLW
k
k
k
k
k
k
k
k
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
00
11
00
11
11
11
00
00
00
00
00
00
00
00
00
00
00
11
00
00
0111
1101
0101
0111
0101
0110
0001
0001
1001
0011
1010
0100
1000
0000
1101
1100
0010
1011
1110
0110
dfff
dfff
dfff
dfff
dfff
dfff
lfff
0000
dfff
dfff
dfff
dfff
dfff
1fff
dfff
dfff
dfff
dfff
dfff
dfff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
00xx
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
ffff
C, DC, Z
C, DC, Z
Z
C, Z
C, Z
C, Z
Z
Z
Z
Z
Z
Z
Z
C
C
C, DC, Z
C, DC, Z
Z
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
1(2)
1(2)
00
00
1, 2
1, 2
1
1
2
2
01
01
1, 2
1, 2
11
11
11
00
11
11
11
11
1110
1001
1000
0000
0001
0000
1100
1010
01
01
1 (2)
1 (2)
LITERAL OPERATIONS
1
1
1
1
1
1
1
1
kkkk
kkkk
kkkk
001k
1kkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
kkkk
C, DC, Z
Z
Z
C, DC, Z
Z
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require one
additional instruction cycle.
3: See the table in the MOVIW and MOVWI instruction descriptions.
DS40001723D-page 247
PIC12(L)F1571/2
TABLE 25-3:
Mnemonic,
Operands
Description
Cycles
14-Bit Opcode
MSb
LSb
Status
Affected
Notes
CONTROL OPERATIONS
BRA
BRW
CALL
CALLW
GOTO
RETFIE
RETLW
RETURN
k
k
k
Relative Branch
Relative Branch with W
Call Subroutine
Call Subroutine with W
Go to address
Return from interrupt
Return with literal in W
Return from Subroutine
2
2
2
2
2
2
2
2
11
00
10
00
10
00
11
00
001k
0000
0kkk
0000
1kkk
0000
0100
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
0000
kkkk
1011
kkkk
1010
kkkk
1001
kkkk
1000
00
00
00
00
00
00
0000
0000
0000
0000
0000
0000
0110
0000
0110
0000
0110
0110
0100 TO, PD
0000
0010
0001
0011 TO, PD
0fff
INHERENT OPERATIONS
CLRWDT
NOP
OPTION
RESET
SLEEP
TRIS
ADDFSR
MOVIW
n, k
n mm
MOVWI
k[n]
n mm
1
1
1
1
1
1
C COMPILER OPTIMIZED
k[n]
1
1
11
00
1
1
11
00
11
1111 1nkk
2, 3
2
2, 3
2
Note 1: If the Program Counter (PC) is modified, or a conditional test is true, the instruction requires two cycles. The second cycle
is executed as a NOP.
2: If this instruction addresses an INDF register and the MSb of the corresponding FSR is set, this instruction will require
one additional instruction cycle.
3: See the table in the MOVIW and MOVWI instruction descriptions.
DS40001723D-page 248
PIC12(L)F1571/2
25.2
Instruction Descriptions
ADDFSR
ANDLW
Syntax:
Syntax:
[ label ] ANDLW
Operands:
-32 k 31
n [ 0, 1]
Operation:
FSR(n) + k FSR(n)
Status Affected:
None
Description:
Operands:
0 k 255
Operation:
Status Affected:
Description:
FSRn is limited to the range 0000h FFFFh. Moving beyond these bounds
will cause the FSR to wraparound.
ADDLW
ANDWF
AND W with f
Syntax:
[ label ] ADDLW
Syntax:
[ label ] ANDWF
Operands:
0 f 127
d 0,1
Operation:
Status Affected:
Description:
ADDWF
Add W and f
ASRF
Syntax:
[ label ] ADDWF
Syntax:
[ label ] ASRF
Operands:
0 f 127
d 0,1
Operands:
0 f 127
d [0,1]
Operation:
Operation:
Status Affected:
C, DC, Z
Description:
(f<7>) dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
Operands:
0 k 255
Operation:
(W) + k (W)
Status Affected:
C, DC, Z
Description:
f,d
ADDWFC
Syntax:
[ label ] ADDWFC
Operands:
0 f 127
d [0,1]
f {,d}
register f
f {,d}
Operation:
Status Affected:
C, DC, Z
Description:
Add W, the Carry flag and data memory location f. If d is 0, the result is
placed in W. If d is 1, the result is
placed in data memory location f.
f,d
DS40001723D-page 249
PIC12(L)F1571/2
BCF
Bit Clear f
Syntax:
[ label ] BCF
BTFSC
f,b
Syntax:
Operands:
0 f 127
0b7
Operands:
Operation:
0 (f<b>)
Operation:
skip if (f<b>) = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
BRA
Relative Branch
BTFSS
Syntax:
Syntax:
Operands:
0 f 127
0b<7
Operands:
Operation:
skip if (f<b>) = 1
Operation:
(PC) + 1 + k PC
Status Affected:
None
Status Affected:
None
Description:
Description:
BRW
Syntax:
[ label ] BRW
Operands:
None
Operation:
(PC) + (W) PC
Status Affected:
None
Description:
BSF
Bit Set f
Syntax:
[ label ] BSF
Operands:
0 f 127
0b7
Operation:
1 (f<b>)
Status Affected:
None
Description:
DS40001723D-page 250
f,b
PIC12(L)F1571/2
CALL
Call Subroutine
CLRWDT
Syntax:
[ label ] CALL k
Syntax:
[ label ] CLRWDT
Operands:
0 k 2047
Operands:
None
Operation:
(PC)+ 1 TOS,
k PC<10:0>,
(PCLATH<6:3>) PC<14:11>
Operation:
Status Affected:
None
00h WDT
0 WDT prescaler,
1 TO
1 PD
Description:
Status Affected:
TO, PD
Description:
CLRWDT instruction resets the Watchdog Timer. It also resets the prescaler
of the WDT.
Status bits TO and PD are set.
CALLW
COMF
Complement f
Syntax:
[ label ] CALLW
Syntax:
[ label ] COMF
Operands:
None
Operands:
Operation:
(PC) +1 TOS,
(W) PC<7:0>,
(PCLATH<6:0>) PC<14:8>
0 f 127
d [0,1]
Operation:
(f) (destination)
Status Affected:
Description:
DECF
Decrement f
Status Affected:
None
Description:
CLRF
Clear f
Syntax:
[ label ] CLRF
f,d
Syntax:
Operands:
0 f 127
Operands:
Operation:
00h (f)
1Z
Operation:
(f) - 1 (destination)
Status Affected:
Description:
Description:
CLRW
Clear W
Syntax:
[ label ] CLRW
Operands:
None
Operation:
00h (W)
1Z
Status Affected:
Status Affected:
Description:
DS40001723D-page 251
PIC12(L)F1571/2
DECFSZ
Decrement f, Skip if 0
INCFSZ
Syntax:
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) - 1 (destination);
skip if result = 0
Operation:
(f) + 1 (destination),
skip if result = 0
Status Affected:
None
Status Affected:
None
Description:
Description:
GOTO
Unconditional Branch
IORLW
Syntax:
[ label ]
Syntax:
[ label ]
GOTO k
Increment f, Skip if 0
INCFSZ f,d
IORLW k
Operands:
0 k 2047
Operands:
0 k 255
Operation:
k PC<10:0>
PCLATH<6:3> PC<14:11>
Operation:
Status Affected:
None
Description:
INCF
Status Affected:
Description:
Increment f
IORWF
Inclusive OR W with f
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f) + 1 (destination)
Operation:
Status Affected:
Status Affected:
Description:
Description:
DS40001723D-page 252
INCF f,d
IORWF
f,d
PIC12(L)F1571/2
LSLF
MOVF
Syntax:
[ label ] LSLF
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 f 127
d [0,1]
Operation:
(f<7>) C
(f<6:0>) dest<7:1>
0 dest<0>
Operation:
(f) (dest)
f {,d}
Status Affected:
C, Z
Description:
register f
Description:
Words:
Cycles:
Syntax:
[ label ] LSRF
Operands:
0 f 127
d [0,1]
Operation:
0 dest<7>
(f<7:1>) dest<6:0>,
(f<0>) C,
Status Affected:
C, Z
Description:
f {,d}
MOVF
FSR, 0
After Instruction
W = value in FSR register
Z = 1
LSRF
register f
MOVF f,d
Status Affected:
Example:
Move f
DS40001723D-page 253
PIC12(L)F1571/2
MOVIW
Move INDFn to W
MOVLP
Syntax:
Syntax:
[ label ] MOVLP k
Operands:
0 k 127
Operation:
k PCLATH
Status Affected:
None
Operands:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
Description:
Operation:
INDFn W
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
MOVLW
Move literal to W
Syntax:
[ label ]
0 k 255
Operation:
k (W)
Status Affected:
None
Description:
The 8-bit literal k is loaded into W register. The dont cares will assemble as
0s.
Words:
1
1
Mode
Syntax
mm
Cycles:
Preincrement
++FSRn
00
Example:
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
MOVLB
MOVLW k
Operands:
Predecrement
MOVLW
0x5A
After Instruction
W =
MOVWF
Move W to f
Syntax:
[ label ]
MOVWF
Operands:
0 f 127
Operation:
(W) (f)
0x5A
Status Affected:
None
Description:
Words:
Cycles:
Example:
MOVWF
OPTION_REG
Before Instruction
OPTION_REG =
W
=
After Instruction
OPTION_REG =
W
=
0xFF
0x4F
0x4F
0x4F
Syntax:
[ label ] MOVLB k
Operands:
0 k 31
Operation:
k BSR
Status Affected:
None
Description:
DS40001723D-page 254
PIC12(L)F1571/2
MOVWI
Move W to INDFn
Syntax:
Operands:
Operation:
n [0,1]
mm [00,01, 10, 11]
-32 k 31
W INDFn
Effective address is determined by
FSR + 1 (preincrement)
FSR - 1 (predecrement)
FSR + k (relative offset)
After the Move, the FSR value will be
either:
FSR + 1 (all increments)
FSR - 1 (all decrements)
Unchanged
Status Affected:
None
Mode
Syntax
Preincrement
++FSRn
00
Predecrement
--FSRn
01
Postincrement
FSRn++
10
Postdecrement
FSRn--
11
Description:
mm
NOP
No Operation
Syntax:
[ label ]
Operands:
None
Operation:
No operation
Status Affected:
None
NOP
Description:
No operation.
Words:
Cycles:
Example:
NOP
OPTION
Syntax:
[ label ] OPTION
Operands:
None
Operation:
(W) OPTION_REG
Status Affected:
None
Description:
RESET
Software Reset
Syntax:
[ label ] RESET
Operands:
None
Operation:
Status Affected:
None
Description:
DS40001723D-page 255
PIC12(L)F1571/2
RETFIE
RETURN
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
None
Operands:
None
Operation:
TOS PC,
1 GIE
Operation:
TOS PC
Status Affected:
None
Status Affected:
None
Description:
Description:
Words:
Cycles:
Example:
RETFIE
RETURN
RETFIE
After Interrupt
PC =
GIE =
TOS
1
RETLW
RLF
Syntax:
[ label ]
Syntax:
[ label ]
0 f 127
d [0,1]
RETLW k
f,d
Operands:
0 k 255
Operands:
Operation:
k (W);
TOS PC
Operation:
None
Status Affected:
Description:
Description:
Words:
Cycles:
Status Affected:
Example:
TABLE
ADDWF PC ;W = offset
RETLW k1 ;Begin table
RETLW k2 ;
DS40001723D-page 256
Words:
Cycles:
Example:
RLF
Register f
REG1,0
Before Instruction
REG1
C
After Instruction
REG1
W
C
=
=
1110 0110
0
=
=
=
1110 0110
1100 1100
1
0x07
value of k8
PIC12(L)F1571/2
RRF
SUBLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
Operation:
k - (W) W)
Operation:
Status Affected:
C, DC, Z
Status Affected:
Description:
Description:
The W register is subtracted (2s complement method) from the 8-bit literal
k. The result is placed in the W register.
RRF f,d
Register f
C=0
Wk
C=1
Wk
DC = 0
W<3:0> k<3:0>
DC = 1
W<3:0> k<3:0>
SLEEP
SUBWF
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
SLEEP
Operands:
None
Operation:
00h WDT,
0 WDT prescaler,
1 TO,
0 PD
Status Affected:
TO, PD
Description:
SUBWF f,d
Status Affected:
C, DC, Z
Description:
SUBWFB
Subtract W from f
C=0
Wf
C=1
Wf
DC = 0
W<3:0> f<3:0>
DC = 1
W<3:0> f<3:0>
Syntax:
SUBWFB
Operands:
0 f 127
d [0,1]
f {,d}
Operation:
Status Affected:
C, DC, Z
Description:
DS40001723D-page 257
PIC12(L)F1571/2
SWAPF
Swap Nibbles in f
XORLW
Syntax:
[ label ]
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operands:
0 k 255
(f<3:0>) (destination<7:4>),
(f<7:4>) (destination<3:0>)
Operation:
(W) .XOR. k W)
Operation:
Status Affected:
Status Affected:
None
Description:
Description:
TRIS
XORWF
Syntax:
[ label ] TRIS f
Syntax:
[ label ]
Operands:
0 f 127
d [0,1]
Operation:
SWAPF f,d
Operands:
5f7
Operation:
Status Affected:
None
Description:
DS40001723D-page 258
Exclusive OR W with f
XORWF
f,d
Status Affected:
Description:
PIC12(L)F1571/2
26.0
ELECTRICAL SPECIFICATIONS
26.1
2:
Maximum current rating requires even load distribution across I/O pins. Maximum current rating may be
limited by the device package power dissipation characterizations, see Table 26-6: Thermal
Characteristics to calculate device specifications.
Power dissipation is calculated as follows: PDIS = VDD x {IDD IOH} + {(VDD VOH) x IOH} + (VOl x IOL).
NOTICE: Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operation listings of this specification is not implied. Exposure above maximum rating conditions for
extended periods may affect device reliability.
DS40001723D-page 259
PIC12(L)F1571/2
26.2
The standard operating conditions for any device are defined as:
Operating Voltage:
Operating Temperature:
DS40001723D-page 260
PIC12(L)F1571/2
FIGURE 26-1:
Rev. 10-000130B
9/19/2013
VDD (V)
5.5
2.5
2.3
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 26-7 for each Oscillator modes supported frequencies.
FIGURE 26-2:
VDD (V)
3.6
2.5
1.8
0
16
32
Frequency (MHz)
Note 1: The shaded region indicates the permissible combinations of voltage and frequency.
2: Refer to Table 26-7 for each Oscillator modes supported frequencies.
DS40001723D-page 261
PIC12(L)F1571/2
26.3
DC Characteristics
TABLE 26-1:
SUPPLY VOLTAGE
PIC12LF1571/2
PIC12F1571/2
Param.
No.
D001
Sym.
VDD
Characteristic
Min.
Typ
Max.
Units
VDDMIN
1.8
2.5
VDDMAX
3.6
3.6
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 3)
2.3
2.5
5.5
5.5
V
V
FOSC 16 MHz
FOSC 32 MHz (Note 3)
1.5
1.7
1.6
1.6
0.8
Supply Voltage
D001
D002*
VDR
D002*
D002A* VPOR
D002A*
D002B* VPORR*
Conditions
D002B*
1.5
D003
VFVR
1.024
-40C TA +85C
D003A
VADFVR
-4
+4
D003B
-4
+4
D004*
SVDD
0.05
V/ms
DS40001723D-page 262
PIC12(L)F1571/2
FIGURE 26-3:
SVDD
VSS
NPOR(1)
POR Rearm
VSS
TVLOW(3)
Note 1:
2:
3:
TPOR(2)
DS40001723D-page 263
PIC12(L)F1571/2
TABLE 26-2:
PIC12LF1571/2
PIC12F1571/2
Param.
No.
Device
Characteristics
D013
D013
D014
D014
D015
D015
D016
D016
Min.
Typ
Max.
Units
35
44
60
Conditions
VDD
Note
1.8
69
3.0
FOSC = 1 MHz,
External Clock (ECM),
Medium Power mode
68
93
2.3
91
120
3.0
131
160
5.0
116
132
1.8
203
233
3.0
174
221
2.3
234
286
3.0
299
374
5.0
5.5
11
1.8
7.3
12
3.0
13
21
2.3
15
24
3.0
17
25
5.0
111
151
1.8
133
176
3.0
144
209
2.3
162
237
3.0
216
288
5.0
D017*
0.5
0.6
mA
1.8
0.7
0.9
mA
3.0
D017*
0.6
0.8
mA
2.3
0.8
0.9
mA
3.0
0.9
1.0
mA
5.0
D018
D018
Note 1:
2:
3:
0.7
0.8
mA
1.8
1.1
1.2
mA
3.0
0.9
1.1
mA
2.3
1.1
1.3
mA
3.0
1.3
1.5
mA
5.0
FOSC = 1 MHz,
External Clock (ECM),
Medium Power mode
FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
FOSC = 4 MHz,
External Clock (ECM),
Medium Power mode
FOSC = 31 kHz,
LFINTOSC,
-40C TA +85C
FOSC = 31 kHz,
LFINTOSC,
-40C TA +85C
FOSC = 500 kHz,
MFINTOSC
FOSC = 500 kHz,
MFINTOSC
FOSC = 8 MHz,
HFINTOSC
FOSC = 8 MHz,
HFINTOSC
FOSC = 16 MHz,
HFINTOSC
FOSC = 16 MHz,
HFINTOSC
DS40001723D-page 264
PIC12(L)F1571/2
TABLE 26-2:
PIC12LF1571/2
PIC12F1571/2
Param.
No.
Device
Characteristics
Conditions
Min.
Typ
Max.
Units
D018A*
2.4
mA
3.0
FOSC = 32 MHz,
HFINTOSC (Note 3)
D018A*
2.1
2.5
mA
3.0
2.2
2.6
mA
5.0
FOSC = 32 MHz,
HFINTOSC (Note 3)
D019A
1.7
1.9
mA
3.0
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 3)
D019A
1.8
mA
3.0
1.9
2.3
mA
5.0
FOSC = 32 MHz,
External Clock (ECH),
High-Power mode (Note 3)
2.2
5.9
1.8
4.3
8.3
3.0
12
20
2.3
15
25
3.0
17
26
5.0
18
25
1.8
30
38
3.0
29
40
2.3
37
51
3.0
42
53
5.0
D019B
D019B
D019C
D019C
Note 1:
2:
3:
VDD
Note
FOSC = 32 kHz,
External Clock (ECL),
Low-Power mode
FOSC = 32 kHz,
External Clock (ECL),
Low-Power mode
FOSC = 500 kHz,
External Clock (ECL),
Low-Power mode
FOSC = 500 kHz,
External Clock (ECL),
Low-Power mode
DS40001723D-page 265
PIC12(L)F1571/2
TABLE 26-3:
PIC12LF1571/2
PIC12F1571/2
Param.
No.
D022
Device Characteristics
Base IPD
D022
Base IPD
D022A
Base IPD
D023
D023
Conditions
Min.
Typ
Max.
+85C
Max.
+125C
Units
0.020
0.6
2.6
1.8
0.025
0.8
2.9
3.0
0.2
0.9
2.8
2.3
0.3
3.0
3.8
3.0
0.4
3.6
4.5
5.0
14
15
2.3
11
19
21
3.0
12
21
22
5.0
0.3
0.8
2.9
1.8
WDT Current
0.5
1.1
3.5
3.0
0.5
1.7
4.1
2.3
0.6
1.9
4.4
3.0
VDD
Note
WDT Current
0.7
2.1
4.7
5.0
D023A
13
18
20
1.8
22
28
29
3.0
D023A
16
24
25
2.3
19
30
31
3.0
20
33
35
5.0
D024
6.5
11
3.0
BOR Current
D024
7.0
10
11
3.0
BOR Current
8.0
12
13
5.0
D24A
0.2
3.0
LPBOR Current
D24A
0.4
3.0
LPBOR Current
0.5
5.0
0.03
0.7
2.7
1.8
0.04
0.8
3.0
0.2
1.3
3.8
2.3
0.3
1.4
3.9
3.0
D026
D026
0.4
1.5
5.0
D026A*
250
1.8
250
3.0
D026A*
280
2.3
280
3.0
280
5.0
Note 1:
2:
3:
FVR Current
FVR Current
DS40001723D-page 266
PIC12(L)F1571/2
TABLE 26-3:
PIC12LF1571/2
PIC12F1571/2
Param.
No.
Conditions
Min.
Typ
Max.
+85C
Max.
+125C
Units
D027
4.2
10
3.0
D027
13
20
21
2.3
14
23
25
3.0
16
24
26
5.0
20
35
36
1.8
21
36
38
3.0
28
47
48
2.3
29
51
52
3.0
31
52
53
5.0
Device Characteristics
D028A
D028A
Note 1:
2:
3:
Note
VDD
1.8
Comparator,
CxSP = 0
Comparator,
CxSP = 0
Comparator,
Normal Power, CxSP = 1
(Note 1)
Comparator,
Normal Power, CxSP = 1,
VREGPM = 1 (Note 1)
DS40001723D-page 267
PIC12(L)F1571/2
TABLE 26-4:
I/O PORTS
Sym.
VIL
Characteristic
Min.
Typ
Max.
Units
Conditions
0.8
0.15 VDD
I/O Ports:
D030
D030A
D031
D032
0.2 VDD
0.3 VDD
0.8
0.2 VDD
MCLR
VIH
I/O Ports:
D040
2.0
0.8 VDD
0.7 VDD
D040A
D041
MCLR
IIL
D060
MCLR(2)
IPUR
D080
D090
125
nA
1000
nA
50
200
nA
25
100
200
25
140
300
0.6
VDD 0.7
50
pF
I/O Ports
VOH
D070*
VOL
I/O Ports
D061
2.1
0.8 VDD
I/O Ports
D101A* CIO
DS40001723D-page 268
PIC12(L)F1571/2
TABLE 26-5:
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
Program Memory
Programming Specifications
D110
VIHH
8.0
9.0
D111
IDDP
10
mA
D112
VBE
2.7
VDDMAX
D113
VPEW
VDDMIN
VDDMAX
D114
1.0
mA
D115
5.0
mA
D121
EP
Cell Endurance
10K
E/W
(Note 2)
D122
VPRW
VDDMIN
VDDMAX
D123
TIW
2.5
ms
D124
TRETD
Characteristic Retention
40
Year
Provided no other
specifications are violated
D125
EHEFC
100K
E/W
0C TA +60C, lower
byte last 128 addresses
Data in Typ column is at 3.0V, +25C unless otherwise stated. These parameters are for design
guidance only and are not tested.
Note 1: Self-write and block erase.
2: Required only if single-supply programming is disabled.
DS40001723D-page 269
PIC12(L)F1571/2
TABLE 26-6:
THERMAL CHARACTERISTICS
TH01
TH02
Sym.
Characteristic
JA
JC
TH03
TJMAX
TH04
PD
TH05
Typ.
Units
Conditions
56.7
C/W
89.3
C/W
149.5
C/W
39.4
C/W
9.0
C/W
43.1
C/W
39.9
C/W
40.3
C/W
150
PD = PINTERNAL + PI/O
TH06
PI/O
TH07
PDER
Derated Power
Note 1: IDD is current to run the chip alone without driving any load on the output pins.
2: TA = Ambient Temperature; TJ = Junction Temperature.
DS40001723D-page 270
PIC12(L)F1571/2
26.4
AC Characteristics
Timing Parameter Symbology has been created with one of the following formats:
1. TppS2ppS
2. TppS
T
F
Frequency
Lowercase letters (pp) and their meanings:
pp
cc
CCP1
ck
CLKOUT
cs
CS
di
SDIx
do
SDO
dt
Data in
io
I/O PORT
mc
MCLR
Uppercase letters and their meanings:
S
F
Fall
H
High
I
Invalid (High-impedance)
L
Low
FIGURE 26-4:
Time
osc
rd
rw
sc
ss
t0
t1
wr
CLKIN
RD
RD or WR
SCKx
SS
T0CKI
T1CKI
WR
P
R
V
Z
Period
Rise
Valid
High-impedance
LOAD CONDITIONS
Rev. 10-000133A
8/1/2013
Load Condition
Pin
CL
VSS
DS40001723D-page 271
PIC12(L)F1571/2
FIGURE 26-5:
CLOCK TIMING
Q4
Q1
Q2
Q3
Q4
Q1
CLKIN
OS02
OS04
OS04
OS03
CLKOUT
(CLKOUT Mode)
Note 1:
TABLE 26-7:
OS01
Sym.
FOSC
Characteristic
Min.
Typ
Max.
Units
Conditions
DC
0.5
MHz
DC
MHz
DC
20
MHz
OS02
TOSC
50
ns
OS03
TCY
200
TCY
DC
ns
TCY = 4/FOSC
DS40001723D-page 272
PIC12(L)F1571/2
TABLE 26-8:
OSCILLATOR PARAMETERS
Sym.
Characteristic
Freq.
Tolerance
Min.
Typ
Max.
Units
OS08
HFOSC
2%
16.0
MHz
OS09
LFOSC
31
kHz
OS10*
TWARM
HFINTOSC
Wake-up from Sleep Start-up Time
15
LFINTOSC
Wake-up from Sleep Start-up Time
0.5
ms
Conditions
FIGURE 26-6:
+125
5%
Temperature (C)
+85
3%
+60
2%
+25
0
5%
-40
1.8
2.5
2.0
3.0
3.5
4.0
4.5
5.0
5.5
VDD (V)
TABLE 26-9:
Param
No.
Sym.
Min.
Typ
Max.
Units
F10
F11
4
16
8
32
MHz
MHz
F12
TRC
ms
CLK
-0.25%
+0.25%
F13*
Conditions
DS40001723D-page 273
PIC12(L)F1571/2
FIGURE 26-7:
Cycle
Write
Fetch
Read
Execute
Q4
Q1
Q2
Q3
FOSC
OS12
OS11
OS20
OS21
CLKOUT
OS19
OS18
OS16
OS13
OS17
I/O pin
(Input)
OS14
OS15
I/O pin
(Output)
New Value
Old Value
OS18, OS19
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
OS11
TosH2ckL
FOSC to CLKOUT(1)
70
ns
OS12
TosH2ckH
FOSC to CLKOUT(1)
72
ns
OS13
TckL2ioV
20
ns
OS14
TioV2ckH
TOSC + 200 ns
ns
OS15
TosH2ioV
50
70*
ns
OS16
TosH2ioI
50
ns
OS17
TioV2osH
20
ns
OS18*
TioR
40
15
72
32
ns
VDD = 1.8V,
3.3V VDD 5.0V
OS19*
TioF
28
15
55
30
ns
VDD = 1.8V,
3.3V VDD 5.0V
OS20*
Tinp
25
ns
OS21*
Tioc
25
ns
DS40001723D-page 274
PIC12(L)F1571/2
FIGURE 26-8:
VDD
MCLR
30
Internal
POR
PWRT
Time-out
33
32
OSC
Start-up Time
Internal Reset(1)
Watchdog Timer
Reset(1)
34
31
34
I/O Pins
Note 1: Asserted low.
DS40001723D-page 275
PIC12(L)F1571/2
TABLE 26-11: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER
AND BROWN-OUT RESET PARAMETERS
Standard Operating Conditions (unless otherwise stated)
Param.
No.
Sym.
Characteristic
Min.
Typ
Max.
Units
Conditions
10
16
27
ms
1024
TOSC
TPWRT
40
65
140
ms
34*
TIOZ
2.0
35
VBOR
2.55
2.35
1.80
2.70
2.45
1.90
2.85
2.58
2.05
V
V
V
36*
VHYST
25
60
mV
37*
16
35
VDD VBOR
38
1.8
2.1
2.5
LPBOR = 1
30
TMCL
31
32
TOST
33*
Note 1:
2:
VDD = 3.3V-5V,
1:512 prescaler used
PWRTE = 0
BORV = 0
BORV = 1 (PIC12F1571/2)
BORV = 1 (PIC12LF1571/2)
-40C TA +85C
FIGURE 26-9:
VDD
VBOR and VHYST
VBOR
37
Reset
(due to BOR)
DS40001723D-page 276
33
PIC12(L)F1571/2
FIGURE 26-10:
T0CKI
40
41
42
T1CKI
45
46
49
47
TMR0 or
TMR1
40*
Sym.
TT0H
Characteristic
Min.
No Prescaler
With Prescaler
41*
TT0L
No Prescaler
With Prescaler
Typ
Max.
Units
0.5 TCY + 20
ns
10
ns
0.5 TCY + 20
ns
10
ns
Greater of:
20 or TCY + 40
N
ns
42*
TT0P
T0CKI Period
45*
TT1H
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Synchronous, No Prescaler
0.5 TCY + 20
ns
15
ns
Asynchronous
30
ns
Greater of:
30 or TCY + 40
N
ns
TT1L
46*
T1CKI Low
Time
47*
TT1P
49*
Asynchronous
60
ns
2 TOSC
7 TOSC
Conditions
N = Prescale value
N = Prescale value
Timers in Sync
mode
DS40001723D-page 277
PIC12(L)F1571/2
TABLE 26-13: ANALOG-TO-DIGITAL CONVERTER (ADC) CHARACTERISTICS(1,2,3)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25C
Param.
Sym.
No.
Characteristic
Min.
Typ
Max.
AD01
NR
Resolution
10
AD02
EIL
Integral Error
1.7
AD03
EDL
Differential Error
AD04
AD05
EGN
AD06
AD07
VAIN
Full-Scale Range
AD08
ZAIN
Recommended Impedance of
Analog Voltage Source
Note 1:
2:
3:
4:
Units
Conditions
bit
LSb VREF = 3.0V
2.5
Gain Error
2.0
1.8
VDD
VSS
VREF
10
DS40001723D-page 278
PIC12(L)F1571/2
FIGURE 26-11:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
0
NEW_DATA
OLD_DATA
ADRES
1 TCY
ADIF
GO
Sample
DONE
Sampling Stopped
AD132
FIGURE 26-12:
BSF ADCON0, GO
AD133
1 TCY
AD131
Q4
AD130
ADC_clk
9
ADC Data
OLD_DATA
ADRES
0
NEW_DATA
1 TCY
ADIF
GO
Sample
DONE
AD132
Sampling Stopped
Note 1: If the ADC clock source is selected as FRC, a time of TCY is added before the ADC clock starts; this allows the
SLEEP instruction to be executed.
DS40001723D-page 279
PIC12(L)F1571/2
TABLE 26-14: ADC CONVERSION REQUIREMENTS
Standard Operating Conditions (unless otherwise stated)
Param.
Sym.
No.
AD130* TAD
AD131 TCNV
Characteristic
Min.
Typ
Max. Units
Conditions
1.0
6.0
FOSC-based
1.0
2.0
6.0
Conversion Time
(not including Acquisition Time)(1)
11
TAD
5.0
1/2 TAD
1/2 TAD + 1TCY
FOSC-based,
ADCS<2:0> = x11 (ADC FRC mode)
DS40001723D-page 280
PIC12(L)F1571/2
TABLE 26-15: COMPARATOR SPECIFICATIONS(1)
Operating Conditions (unless otherwise stated)
VDD = 3.0V, TA = +25C
Param.
No.
CM01
Sym.
Characteristics
VIOFF
Min.
Typ.
Max.
Units
7.5
60
mV
Comments
CxSP = 1,
VICM = VDD/2
CM02
VICM
VDD
CM03
CMRR
50
dB
CM04A
TRESP(2)
400
800
ns
CxSP = 1
200
400
ns
CxSP = 1
CM04B
CM04C
1200
ns
CxSP = 0
CM04D
550
ns
CxSP = 0
10
25
mV
CM05*
TMC2OV
CM06
*
Note 1:
2:
CxHYS = 1,
CxSP = 1
Sym.
Characteristics
Min.
Typ.
Max.
Units
VDD/32
DAC01*
CLSB
Step Size
DAC02*
CACC
Absolute Accuracy
1/2
LSb
DAC03*
CR
5K
CST
Time(2)
10
DAC04*
*
Note 1:
2:
Settling
Comments
DS40001723D-page 281
PIC12(L)F1571/2
FIGURE 26-13:
CK
US121
US121
DT
US122
US120
Note:
Symbol
TCKH2DTV
TCKRF
TDTRF
FIGURE 26-14:
Characteristic
Min.
Max.
Units
Conditions
80
ns
100
ns
45
ns
50
ns
45
ns
50
ns
CK
US125
DT
US126
Note: Refer to Figure 26-4 for load conditions.
Symbol
Characteristic
DS40001723D-page 282
Min.
Max.
Units
10
ns
15
ns
Conditions
PIC12(L)F1571/2
27.0
The graphs and tables provided in this section are for design guidance and are not tested.
In some graphs or tables, the data presented is outside specified operating range (i.e., outside specified VDD range).
This is for information only and devices are ensured to operate properly only within the specified range.
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
Typical represents the mean of the distribution at +25C. MAXIMUM, Max., MINIMUM or Min.
DS40001723D-page 283
PIC12(L)F1571/2
FIGURE 27-1:
6.0
5.5
Max.
Max: 85C + 3
Typical: 25C
5.0
4.5
Typical
IDD (A)
4.0
3.5
3.0
2.5
2.0
1.5
1.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-2:
25
Max: 85C + 3
Typical: 25C
20
Max.
IDD (A)
Typical
15
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 284
PIC12(L)F1571/2
FIGURE 27-3:
40
Max: 85C + 3
Typical: 25C
35
Max.
Typical
IDD (A)
30
25
20
15
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-4:
50
Max.
Max: 85C + 3
Typical: 25C
45
IDD (A)
40
Typical
35
30
25
20
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 285
PIC12(L)F1571/2
FIGURE 27-5:
300
Typical: 25C
250
4 MHz
IDD (A)
200
150
100
1 MHz
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-6:
300
4 MHz
Max: 85C + 3
250
IDD (A)
200
150
100
1 MHz
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001723D-page 286
PIC12(L)F1571/2
FIGURE 27-7:
350
4 MHz
Typical: 25C
300
IDD (A)
250
200
150
1 MHz
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 27-8:
400
350
4 MHz
Max: 85C + 3
300
IDD (A)
250
200
1 MHz
150
100
50
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 287
PIC12(L)F1571/2
FIGURE 27-9:
2.5
Typical: 25C
IDD (mA)
2.0
32 MHz
1.5
16 MHz
1.0
8 MHz
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-10:
2.5
Max: 85C + 3
32 MHz
IDD (mA)
2.0
1.5
16 MHz
1.0
8 MHz
0.5
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001723D-page 288
PIC12(L)F1571/2
FIGURE 27-11:
2.5
Typical: 25C
2.0
32 MHz
IDD (mA)
1.5
16 MHz
1.0
8 MHz
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 27-12:
2.5
Max: 85C + 3
32 MHz
IDD (mA)
2.0
1.5
16 MHz
1.0
8 MHz
0.5
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 289
PIC12(L)F1571/2
FIGURE 27-13:
10
Max.
9
Max: 85C + 3
Typical: 25C
Typical
IDD (A)
8
7
6
5
4
3
2
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-14:
25
Max: 85C + 3
Typical: 25C
20
Max.
IDD (A)
Typical
15
10
0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 290
PIC12(L)F1571/2
FIGURE 27-15:
170
160
Max: 85C + 3
Typical: 25C
Max.
IDD (A)
150
140
Typical
130
120
110
100
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-16:
260
Max.
Max: 85C + 3
Typical: 25C
240
Typical
220
IDD (A)
200
180
160
140
120
100
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 291
PIC12(L)F1571/2
FIGURE 27-17:
1.4
16 MHz
Typical: 25C
1.2
IDD (mA)
1.0
8 MHz
0.8
4 MHz
0.6
2 MHz
0.4
1 MHz
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-18:
1.4
16 MHz
Max: 85C + 3
1.2
1.0
IDD (mA)
8 MHz
0.8
4 MHz
2 MHz
0.6
1 MHz
0.4
0.2
0.0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001723D-page 292
PIC12(L)F1571/2
FIGURE 27-19:
1.4
16 MHz
Typical: 25C
1.2
1.0
IDD (mA)
8 MHz
0.8
4 MHz
2 MHz
0.6
1 MHz
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
FIGURE 27-20:
1.6
1.4
16 MHz
Max: 85C + 3
1.2
IDD (mA)
1.0
8 MHz
0.8
4 MHz
2 MHz
0.6
1 MHz
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 293
PIC12(L)F1571/2
FIGURE 27-21:
350
300
Max: 85C + 3
Typical: 25C
Max.
IPD (nA
(nA)
250
200
150
100
Typical
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-22:
0.8
0.7
Max: 85C + 3
Typical: 25C
IPD (A
(A)
0.6
Max
0.5
0.4
0.3
Typical
0.2
0.1
0.0
20
2.0
2
2.5
5
3
3.0
0
3
3.5
5
4
4.0
0
4
4.5
5
5
5.0
0
5
5.5
5
6
6.0
0
VDD (V)
DS40001723D-page 294
PIC12(L)F1571/2
FIGURE 27-23:
1.0
0.9
Max: 85C + 3
Typical: 25C
0.8
Max.
IPD (A)
0.7
0.6
Typical
0.5
04
0.4
0.3
0.2
0.1
0.0
16
1.6
1
1.8
8
2
2.0
0
2
2.2
2
2
2.4
4
2
2.6
6
2
2.8
8
3
3.0
0
3
3.2
2
3
3.4
4
3
3.6
6
3
3.8
8
VDD (V)
FIGURE 27-24:
1.6
1.4
Max: 85C + 3
Typical: 25C
1.2
Max.
IPD (A
(A)
1.0
0.8
Typical
0.6
0.4
0.2
0.0
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 295
PIC12(L)F1571/2
FIGURE 27-25:
28
Max: 85C + 3
Typical: 25C
26
24
Max.
IPD (uA)
22
20
18
T i l
Typical
16
14
12
10
16
1.6
1
1.8
8
2
2.0
0
2
2.2
2
2
2.4
4
2
2.6
6
2
2.8
8
3
3.0
0
3
3.2
2
3
3.4
4
3
3.6
6
3
3.8
8
VDD (V)
FIGURE 27-26:
24
22
Max.
20
IPD (uA
(uA)
Typical
18
16
14
Max: 85C + 3
Typical: 25
C
25C
12
10
20
2.0
2
5
2.5
3
0
3.0
3
5
3.5
4
0
4.0
4
5
4.5
5
0
5.0
5
5
5.5
6
0
6.0
VDD (V)
DS40001723D-page 296
PIC12(L)F1571/2
FIGURE 27-27:
9
8.5
Max: 85C + 3
Typical: 25C
Max.
IPD ((uA)
7.5
7
Typical
6.5
6
5.5
5
4.5
24
2.4
2
2.5
5
2
2.6
6
2
2.7
7
2
2.8
8
2
2.9
9
3
3.0
0
3
3.1
1
3
3.2
2
3
3.3
3
3
3.4
4
3
3.5
5
3
3.6
6
3
3.7
7
5
4
5.4
5
6
5.6
VDD (V)
FIGURE 27-28:
12
11
Max: 85C + 3
Typical: 25C
10
Max.
IPD (uA)
9
8
Typical
7
6
5
4
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
4
0
4.0
4
2
4.2
4
4
4.4
4
6
4.6
4
8
4.8
5
0
5.0
5
2
5.2
VDD (V)
DS40001723D-page 297
PIC12(L)F1571/2
FIGURE 27-29:
1.8
16
1.6
Max: 85C + 3
Typical: 25C
1.4
Max.
IPD (uA
(uA)
1.2
1
0.8
0.6
0.4
Typical
0.2
0
2.4
2.5
2.6
2.7
2.8
2.9
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.7
VDD (V)
FIGURE 27-30:
1.8
Max: 85C + 3
Typical: 25C
1.6
Max.
1.4
IDD (A
(A)
1.2
1.0
0.8
0.6
Typical
0.4
0.2
0.0
28
2.8
3
3.0
0
3
3.2
2
3
3.4
4
3
3.6
6
3
3.8
8
4
4.0
0
4
4.2
2
4
4.4
4
4
4.6
6
4
4.8
8
5
5.0
0
5
5.2
2
5
5.4
4
5
5.6
6
VDD (V)
DS40001723D-page 298
PIC12(L)F1571/2
FIGURE 27-31:
500
450
Max: 85C + 3
Typical: 25C
400
Max.
350
IPD (A)
300
250
200
150
100
Typical
50
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
FIGURE 27-32:
1.4
Max: 85C + 3
Typical: 25C
1.2
Max.
IDD (A)
1.0
0.8
0.6
0.4
Typical
0.2
0.0
15
1.5
2
0
2.0
2
5
2.5
3
0
3.0
3
5
3.5
4
0
4.0
4
5
4.5
5
0
5.0
5
5
5.5
6
0
6.0
VDD (V)
DS40001723D-page 299
PIC12(L)F1571/2
FIGURE 27-33:
22
Max: 85C + 3
Typical: 25C
20
Max.
18
Typical
IPD (
(A)
16
14
12
10
8
6
4
2
0
2.0
2
5
2.5
3
0
3.0
3
5
3.5
4
0
4.0
4
5
4.5
5
0
5.0
5
5
5.5
6
0
6.0
VDD (V)
FIGURE 27-34:
32
Max: -40C + 3
Typical: 25C
30
28
Max.
IPD (A
(A)
26
24
22
Typical
20
18
16
14
12
16
1.6
1
1.8
8
2
2.0
0
2
2.2
2
2
2.4
4
2
2.6
6
2
2.8
8
3
3.0
0
3
3.2
2
3
3.4
4
3
3.6
6
3
3.8
8
VDD (V)
DS40001723D-page 300
PIC12(L)F1571/2
FIGURE 27-35:
45
Max: -40C
40C + 3
Typical: 25C
40
Max.
35
IPD (A
(A)
Typical
30
25
20
15
10
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 301
PIC12(L)F1571/2
FIGURE 27-36:
1100
Max: 85C + 3
Typical: 25C
1000
900
Max.
IPD (A
(A)
800
700
Typical
600
500
400
300
200
16
1.6
1
8
1.8
2
0
2.0
2
2
2.2
2
4
2.4
2
6
2.6
2
8
2.8
3
0
3.0
3
2
3.2
3
4
3.4
3
6
3.6
3
8
3.8
VDD (V)
FIGURE 27-37:
1,200
Max: 85C + 3
Typical: 25C
1,100
Max.
1,000
Typical
IPD (A
(A)
900
800
700
600
500
400
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VDD (V)
DS40001723D-page 302
PIC12(L)F1571/2
FIGURE 27-38:
60
Max: Typical + 3
Typical: statistical mean @ 25C
50
Max.
Time (us)
40
Typical
30
20
Note:
The FVR Stabilization Period applies when:
1) coming out of RESET or exiting Sleep mode for PIC12/16LFxxxx devices.
2) when exiting sleep mode with VREGPM = 1 for PIC12/16Fxxxx devices
In all other cases, the FVR is stable when released from RESET.
10
0
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
3.8
VDD (V)
DS40001723D-page 303
PIC12(L)F1571/2
NOTES:
DS40001723D-page 304
PIC12(L)F1571/2
28.0
DEVELOPMENT SUPPORT
28.1
Multiple projects
Multiple tools
Multiple configurations
Simultaneous debugging sessions
DS40001723D-page 305
PIC12(L)F1571/2
28.2
MPLAB XC Compilers
28.3
MPASM Assembler
28.4
28.5
DS40001723D-page 306
PIC12(L)F1571/2
28.6
28.7
28.8
28.9
The MPLAB PICkit 3 allows debugging and programming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
interface of the MPLAB IDE. The MPLAB PICkit 3 is
connected to the design engineers PC using a fullspeed USB interface and can be connected to the target via a Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The
connector uses two device I/O pins and the Reset line
to implement in-circuit debugging and In-Circuit Serial
Programming (ICSP).
DS40001723D-page 307
PIC12(L)F1571/2
28.11 Demonstration/Development
Boards, Evaluation Kits, and
Starter Kits
A wide variety of demonstration, development and
evaluation boards for various PIC MCUs and dsPIC
DSCs allows quick application development on fully
functional systems. Most boards include prototyping
areas for adding custom circuitry and provide application firmware and source code for examination and
modification.
The boards support a variety of features, including LEDs,
temperature sensors, switches, speakers, RS-232
interfaces, LCD displays, potentiometers and additional
EEPROM memory.
DS40001723D-page 308
PIC12(L)F1571/2
29.0
PACKAGING INFORMATION
29.1
XXXXXXXX
XXXXXNNN
YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
12F1571
E/Pe3 017
1310
Example
12F1571
E/SN1310
017
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week 01)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
DS40001723D-page 309
PIC12(L)F1571/2
Package Marking Information (Continued)
8-Lead MSOP (3x3 mm)
Example
L1571I
310017
XXXX
YYWW
NNN
PIN 1
DS40001723D-page 310
Example
MFQ0
1312
017
PIN 1
PIC12(L)F1571/2
TABLE 29-1:
Part Number
Marking
TABLE 29-2:
Part Number
Marking
PIC12F1571-E/MF
MFY0/YYWW/NNN
PIC12F1571-E/MF
MFY0/YYWW/NNN
PIC12F1572-E/MF
MGA0/YYWW/NNN
PIC12F1572-E/MF
MGA0/YYWW/NNN
PIC12F1571-I/MF
MFZ0
PIC12F1571-I/MF
MFZ0
PIC12F1572-I/MF
MGB0
PIC12F1572-I/MF
MGB0
PIC12LF1571-E/MF
MGC0
PIC12LF1571-E/MF
MGC0
PIC12LF1572-E/MF
MGE0
PIC12LF1572-E/MF
MGE0
PIC12LF1571-I/MF
MGD0
PIC12LF1571-I/MF
MGD0
PIC12LF1572-I/MF
MGF0
PIC12LF1572-I/MF
MGF0
DS40001723D-page 311
PIC12(L)F1571/2
29.2
Package Details
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
E1
NOTE 1
1
TOP VIEW
A2
PLANE
L
A1
e
eB
8X b1
8X b
.010
SIDE VIEW
END VIEW
DS40001723D-page 312
PIC12(L)F1571/2
8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DATUM A
DATUM A
e
2
e
2
Units
Dimension Limits
Number of Pins
N
e
Pitch
Top to Seating Plane
A
Molded Package Thickness
A2
Base to Seating Plane
A1
Shoulder to Shoulder Width
E
Molded Package Width
E1
Overall Length
D
Tip to Seating Plane
L
c
Lead Thickness
Upper Lead Width
b1
b
Lower Lead Width
Overall Row Spacing
eB
MIN
.115
.015
.290
.240
.348
.115
.008
.040
.014
-
INCHES
NOM
8
.100 BSC
.130
.310
.250
.365
.130
.010
.060
.018
-
MAX
.210
.195
.325
.280
.400
.150
.015
.070
.022
.430
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Significant Characteristic
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-018D Sheet 2 of 2
DS40001723D-page 313
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 314
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 315
PIC12(L)F1571/2
!"#$%
&
!
"# $% &"'""
($)
%
*++&&&!
!+$
DS40001723D-page 316
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 317
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 318
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 319
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 320
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 321
PIC12(L)F1571/2
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS40001723D-page 322
PIC12(L)F1571/2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
D
(DATUM A)
(DATUM B)
E
NOTE 1
2X
0.10 C
1
2X
TOP VIEW
0.10 C
0.05 C
C
SEATING
PLANE
A1
A
8X
(A3)
0.05 C
SIDE VIEW
0.10
C A B
D2
1
L
0.10
C A B
E2
NOTE 1
8X b
0.10
e
2
C A B
BOTTOM VIEW
Microchip Technology Drawing C04-254A Sheet 1 of 2
DS40001723D-page 323
PIC12(L)F1571/2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
Number of Terminals
N
e
Pitch
Overall Height
A
Standoff
A1
A3
Terminal Thickness
Overall Width
E
E2
Exposed Pad Width
Overall Length
D
D2
Exposed Pad Length
Terminal Width
b
Terminal Length
L
K
Terminal-to-Exposed-Pad
MIN
0.45
0.00
1.40
2.20
0.25
0.35
0.20
MILLIMETERS
NOM
8
0.65 BSC
0.50
0.02
0.065 REF
3.00 BSC
1.50
3.00 BSC
2.30
0.30
0.45
-
MAX
0.55
0.05
1.60
2.40
0.35
0.55
-
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Package is saw singulated
3. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-254A Sheet 2 of 2
DS40001723D-page 324
PIC12(L)F1571/2
8-Lead Ultra Thin Plastic Dual Flat, No Lead Package (RF) - 3x3x0.50 mm Body [UDFN]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C
X2
E
Y2
X1
G1
G2
SILK SCREEN
Y1
Units
Dimension Limits
E
Contact Pitch
Optional Center Pad Width
X2
Optional Center Pad Length
Y2
Contact Pad Spacing
C
Contact Pad Width (X8)
X1
Contact Pad Length (X8)
Y1
Contact Pad to Contact Pad (X6)
G1
Contact Pad to Center Pad (X8)
G2
MIN
MILLIMETERS
NOM
0.65 BSC
MAX
1.60
2.40
2.90
0.35
0.85
0.20
0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-2254A
DS40001723D-page 325
PIC12(L)F1571/2
NOTES:
DS40001723D-page 326
PIC12(L)F1571/2
APPENDIX A:
DATA SHEET
REVISION HISTORY
Revision A (10/2013)
Original release of this document.
Revision B (2/2014)
Updated PIC12(L)F1571/2 Family Types table
Program Memory Flash heading (words to K words).
Revision C (8/2014)
Updated PWM chapter. Changed to Final data sheet.
Updated IDD and IPD parameters in the Electrical
Specification chapter. Added Characterization Graphs.
Added Section
Conventions.
1.1:
Register
and
Bit
Naming
Revision D (8/2015)
Updated Clocking Structure, Memory, Low-Power
Features, Family Types table and Pin Diagram Table
on cover pages.
Added Sections 3.2: High-Endurance Flash and
5.4: Clock Switching Before Sleep. Added Table 29-2
and 8-pin UDFN packaging.
Updated Examples 3-2 and 15-1.
Updated Figures 8-1, 21-1, 22-8 through 22-13 and
23-1.
Updated Registers 7-5, 8-1, 22-6 and 23-3.
Updated Sections 8.2.2, 15.2.6, 16.0, 21.0, 21.4.2,
22.3.3, 23.9.1.2, 23.11.1, 26.1 and 29.1.
Updated Tables 1, 3-3, 3-4, 3-10, 5-1, 16-1, 17-3, 22-2,
23-2, 26-6, 26-8 and 29-1.
DS40001723D-page 327
PIC12(L)F1571/2
NOTES:
DS40001723D-page 328
PIC12(L)F1571/2
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers
should
contact
their
distributor,
representative or Field Application Engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
DS40001723D-page 329
PIC12(L)F1571/2
NOTES:
DS40001723D-page 330
PIC12(L)F1571/2
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
[X](1)
PART NO.
Device
/XX
XXX
Package
Pattern
Examples:
a)
b)
Device:
PIC12LF1571, PIC12F1571
PIC12LF1572, PIC12F1572
Blank
T
Temperature
Range:
I
E
= -40C to +85C
= -40C to +125C
Package:(2)
MF
MS
P
SN
RF
Pattern:
c)
=
=
=
=
=
(Industrial)
(Extended)
PIC12LF1571T - I/SO
Tape and Reel,
Industrial temperature,
SOIC package
PIC12F1572 - I/P
Industrial temperature,
PDIP package
PIC12F1571-E/MF
Extended Temperature,
DFN package
DS40001723D-page 331
PIC12(L)F1571/2
NOTES:
DS40001723D-page 332
Note the following details of the code protection feature on Microchip devices:
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as unbreakable.
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Trademarks
== ISO/TS 16949 ==
2013-2015 Microchip Technology Inc.
DS40001723D-page 333
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07/14/15
DS40001723D-page 334