--And gate

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity and_2 is
port ( a,b: in std_logic;
y: out std_logic);
end and_2;
architecture Behavioral of and_2 is
begin
y <= a and b;
end Behavioral;
--Fau unit
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY fau IS
PORT ( a, b, cin: IN STD_LOGIC;
s, cout: OUT STD_LOGIC);
END fau;
--------------------------------------ARCHITECTURE fau OF fau IS
BEGIN
s <= a XOR b XOR cin;
cout <= (a AND b) OR (a AND cin) OR (b AND cin);
END fau;
----------------------------------------Reg unit
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------ENTITY reg IS

PORT ( d, clk, rst: IN STD_LOGIC;

q: OUT STD_LOGIC);
END reg;
--------------------------------------ARCHITECTURE reg OF reg IS
BEGIN
PROCESS (clk, rst)
BEGIN
IF (rst='1') THEN q<='0';
ELSIF (clk'EVENT AND clk='1') THEN q<=d;
END IF;
END PROCESS;
END reg;

--Pipe unit
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_components.all;
--------------------------------------ENTITY pipe IS
PORT ( a, b, clk, rst: IN STD_LOGIC;
q: OUT STD_LOGIC);
END pipe;
--------------------------------------ARCHITECTURE structural OF pipe IS
SIGNAL s, cin, cout: STD_LOGIC;
BEGIN
U1: COMPONENT fau PORT MAP (a, b, cin, s, cout);
U2: COMPONENT reg PORT MAP (cout, clk, rst, cin);
U3: COMPONENT reg PORT MAP (s, clk, rst, q);
END structural;
--My_components
LIBRARY ieee;
USE ieee.std_logic_1164.all;
--------------------------------------PACKAGE my_components IS
-------------------------COMPONENT and_2 IS
PORT (a, b: IN STD_LOGIC; y: OUT STD_LOGIC);
END COMPONENT;
-------------------------COMPONENT fau IS

PORT (a, b, cin: IN STD_LOGIC; s, cout: OUT STD_LOGIC);

END COMPONENT;
-------------------------COMPONENT reg IS
PORT (d, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);
END COMPONENT;
-------------------------COMPONENT pipe IS
PORT (a, b, clk, rst: IN STD_LOGIC; q: OUT STD_LOGIC);
END COMPONENT;
-------------------------END my_components;
----------------------------------------Multiplier unit
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.my_components.all;
--------------------------------------ENTITY multiplier IS
PORT ( a, clk, rst: IN STD_LOGIC;
b:IN STD_LOGIC_VECTOR (3 DOWNTO 0);
prod: OUT STD_LOGIC);
END multiplier;
--------------------------------------ARCHITECTURE structural OF multiplier IS
SIGNAL and_out, reg_out: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
U1: COMPONENT and_2 PORT MAP (a, b(3), and_out(3));
U2: COMPONENT and_2 PORT MAP (a, b(2), and_out(2));
U3: COMPONENT and_2 PORT MAP (a, b(1), and_out(1));
U4: COMPONENT and_2 PORT MAP (a, b(0), and_out(0));
U5: COMPONENT reg PORT MAP (and_out(3), clk, rst,reg_out(3));
U6: COMPONENT pipe PORT MAP (and_out(2), reg_out(3),
clk, rst, reg_out(2));
U7: COMPONENT pipe PORT MAP (and_out(1), reg_out(2),
clk, rst, reg_out(1));
U8: COMPONENT pipe PORT MAP (and_out(0), reg_out(1),
clk, rst, reg_out(0));
prod <= reg_out(0);
END structural;
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