sThe Demultiplexer

What is demultiplexer?
The data distributor, known more commonly as a Demultiplexer or Demux
for short, is the exact opposite of the Multiplexer we saw in the previous tutorial.
The demultiplexer takes one single input data line and then switches it to any one
of a number of individual output lines one at a time. The demultiplexer converts a
serial data signal at the input to a parallel data at its output lines as shown below.
1-to-4 Channel De-multiplexer

Output Select
b

Data Output
Selected

The Boolean expression for this 1-to-4 Demultiplexer above with

outputs A to D and data select lines a, b is given as:
F = abA + abB + abC + abD
The function of the Demultiplexer is to switch one common data input line to
any one of the 4 output data lines A to D in our example above. As with the
multiplexer the individual solid state switches are selected by the binary input
address code on the output select pins a and b as shown.
4 Channel Demultiplexer using Logic Gates

The symbol used in logic diagrams to identify a demultiplexer is as follows.

The Demultiplexer Symbol

Again, as with the previous multiplexer example, we can also use

the Demultiplexer to digitally control the gain of an operational amplifier as shown.
Digitally Adjustable Amplifier Gain

The circuit above illustrates how to provide digitally controlled

adjustable/variable op-amp gain using a demultiplexer. The voltage gain of the
2

inverting operational amplifier is dependent upon the ratio between the input
resistor, Rin and its feedback resistor, R as determined in the Op-amp tutorials.
The digitally controlled analogue switches of the demultiplexer select an
input resistor to vary the value of Rin. The combination of these resistors will
determine the overall gain of the amplifier, (Av). Then the voltage gain of the
inverting operational amplifier can be adjusted digitally simply by selecting the
appropriate input resistor combination.
Standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output
demultiplexer, the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS
CD4514 1-to-16 output demultiplexer.
Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16line demultiplexer/decoder. Here the individual output positions are selected using
a 4-bit binary coded input. Like multiplexers, demultiplexers can also be cascaded
together to form higher order demultiplexers.
Unlike multiplexers which convert data from a single data line to multiple lines and
demultiplexers which convert multiple lines to a single data line, there are devices
available which convert data to and from multiple lines and in the next tutorial
about combinational logic devices, we will look at Encoders which convert multiple
input lines into multiple output lines, converting the data from one form to
another.
Uses of Demultiplexer
Demultiplexer is used to connect a single source to multiple destinations. One use
of
the Demultiplexer is at the output of the ALU circuit. The output of the ALU has to
be stored in
one of the multiple registers or storage units. The Data input of the Demultiplexer i
s connected
to the output of the ALU. Each output of the Demultiplexer is connected to each of
the multiple
registers. By selecting the appropriate output data from the ALU
is routed to the appropriate
3

register for storage.

The second use of the Demultiplexer is the reconstruction of Parallel Data from the
incoming serial data stream. Serial data arrives at the Data input of the Demultipl
exer at fixed
time intervals. A counter attached to the Select inputs of the Demultiplexer routes
the incoming
serial bits to successive outputs where each bit is stored. When all the bits have be
en stored,
data can be read out in parallel. Figure 19.2

Programmable Logic Devices

Programmable Logic Devices are used in many applications to replace the Logic gat
es
and MSI chips. PLDs save circuit space and reduce and save the cost of component
s in a
Digital Circuit. PLDS consists of Arrays of
AND gates and OR gates that can be programmed
to perform specific functions.
Programmable Arrays of AND Gates and OR Gates
The array is essentially a grid of conductors that forms rows and columns wi
th a fuse
connecting each column conductor with each row conductor. The fuses can be blo
wn to
disconnect a particular column from a particular row. The OR gate array consists o
f the grid
and OR gates. Similarly the AND gate array consists of the grid and AND Gates. Fig
ure 19.3
Each column conductor in the grid represents a single variable or its complement.
A
grid of several column conductors represents several variables and their compleme
nts. Each
OR and AND gate in the array is connected to each of the variables through horizo
ntal
conductors. When all the fuses are intact, all variables are present at the inputs of
all the OR
and AND gates. The OR and AND gates can be configured to have specified literals

connected to their inputs by blowing away appropriate fuses which are blown throu
gh
programming. A programmed OR array has sum terms at the output of its OR gate
s. Similarly
a programmed AND array has product terms at its output. Figure 19.

An alternate implementation of the grid is with no fuses, the grid column and row
conductors are not connected to each other. A specific column conductor can be co
nnected to
a row conductor by shorting the column and row conductors. Both the methods in
which a fuse
is blown to disconnect a column from a row and the shorting method in which a co
lumn is
connected to
a row can only be done once. Thus when an array has been configured to
perform a function it can not be reprogrammed.
Programmable Logic Devices have an array of AND gates and an array of OR gates
either or both of which can be programmed. There are different types of PLDs, they
are
classified according to their architecture which allows either both the arrays to
be programmed
or only one of the two arrays.
1. Programmable Read-Only Memory (PROM)
The PROM consists of a fixed non-programmable AND array configured as
a decoder
and a programmable OR array. Figure 19.5. The PROM is used as
a storage device which
stores information at addressable locations. It has limited applications and is not u
sed as a
logic device. PROM architecture and details are discussed in latter lectures.
2. Programmable Logic Array (PLA)
The PLA consists of a programmable AND array and a programmable OR array.
10

Figure 19.6. It has been designed to overcome the limitations of

a PROM. PLA is also known
as a Field-Programmable Logic Array as
it can be programmed by the user and not by the
manufacturer.

11

12

3. Programmable Array Logic (PAL)

The PAL has been designed to overcome the longer delays and the complex circuitr
y
associated with the PLA due to two programmable arrays. The PAL has programma
ble AND
array and a fixed OR array. Figure 19.7
4. Generic Array Logic (GAL)
The GAL has a reprogrammable AND array and a fixed OR array with programmabl
e
output logic. Figure 19.8. The main difference between GAL and PAL are the reprog
rammable
AND array which can be programmed again and again, unlike PAL AND array whic
h can be
programmed once. GAL uses E2CMOS technology which is Electrically Erasable C
MOS
instead of Bipolar technology and fusible links. The other difference is the program
mable
outputs.

13

The Multiplexer (MUX)

Multiplexing is the generic term used to describe the operation of sending
one or more analogue or digital signals over a common transmission line at
different times or speeds and as such, the device we use to do just that is called
a Multiplexer.
The multiplexer, shortened to MUX or MPX, is a combinational logic
circuit designed to switch one of several input lines through to a single common
output line by the application of a control signal. Multiplexers operate like very fast
acting multiple position rotary switches connecting or controlling multiple input
lines called channels one at a time to the output.
Multiplexers, or MUXs, can be either digital circuits made from high speed logic
gates used to switch digital or binary data or they can be analogue types using
transistors, MOSFETs or relays to switch one of the voltage or current inputs
through to a single output.
The most basic type of multiplexer device is that of a one-way rotary switch
as shown.
Basic Multiplexing Switch

The rotary switch, also called a wafer switch as each layer of the switch is
known as a wafer, is a mechanical device whose input is selected by rotating a
shaft. In other words, the rotary switch is a manual switch that you can use to
select individual data or signal lines simply by turning its inputs ON or OFF. So
how can we select each data input automatically using a digital device.

14

In digital electronics, multiplexers are also known as data selectors because

they can select each input line, are constructed from individual Analogue
Switches encased in a single IC package as opposed to the mechanical type
selectors such as normal conventional switches and relays.
They are used as one method of reducing the number of logic gates required in a
circuit design or when a single data line or data bus is required to carry two or
more different digital signals. For example, a single 8-channel multiplexer.
Generally, the selection of each input line in a multiplexer is controlled by an
additional set of inputs called control lines and according to the binary condition of
these control inputs, either HIGH or LOW the appropriate data input is
connected directly to the output. Normally, a multiplexer has an even number of
2N data input lines and a number of control inputs that correspond with the
number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to
switch an n-bit input pattern to multiple output lines that represent the binary
coded (BCD) output equivalent of the active input.
We can build a simple 2-line to 1-line (2-to-1) multiplexer from basic
logic NAND gates as shown.
2-input Multiplexer Design

The input A of this simple 2-1 line multiplexer circuit constructed from
standard NAND gates acts to control which input ( I0 or I1 ) gets passed to the
output at Q.

15

From the truth table we can see that when data select input, A is LOW (logic
0), input I1 passes its data to the output while input I0 is blocked. When data
select A is HIGH (logic 1), input I0 is passed to Q while input I0 is blocked.
So by the application of either a logic 0 or a logic 1 at A we can select the
appropriate input with the circuit acting a bit like a single pole double throw
(SPDT) switch. Then in this simple example, the 2-input multiplexer connects one
of two 1-bit sources to a common output, producing a 2-to-1-line multiplexer and
we can confirm this in the following Boolean expression.
Q = A.I0.I1 + A.I0.I1 + A.I0.I1 + A.I0.I1
and for our 2-input multiplexer circuit above, this can be simplified too:
Q = A.I1 + A.I0
We can increase the number of data inputs to be selected further simply by
following the same procedure and larger multiplexer circuits can be implemented
using smaller 2-to-1 multiplexers as their basic building blocks. So for a 4-input
multiplexer we would therefore require two data select lines as 4-inputs
represents 22 data control lines give a circuit with four inputs, I0, I1, I2, I3 and two
data select lines A and B as shown.
4-to-1 Channel Multiplexer

16

The Boolean expression for this 4-to-1 Multiplexer above with

inputs A to D and data select lines a, b is given as:
Q = abA + abB + abC + abD
In this example at any one instant in time only ONE of the four analogue switches
is closed, connecting only one of the input lines A to D to the single output at Q.
As to which switch is closed depends upon the addressing input code on lines a
and b, so for this example to select input Bto the output at Q, the binary input
address would need to be a = logic 1 and b = logic 0.
Then we can show the selection of the data through the multiplexer as a
function of the data select bits as shown.
Multiplexer Input Line Selection

17

Adding more control address lines will allow the multiplexer to control more
inputs but each control line configuration will connect only ONE input to the
output.
Then the implementation of the Boolean expression above using individual
logic gates would require the use of seven individual gates consisting
of AND, OR and NOT gates as shown.
4 Channel Multiplexer using Logic Gates

The symbol used in logic diagrams to identify a multiplexer is as follows.

Multiplexer Symbol

Multiplexers are not limited to just switching a number of different input

lines or channels to one common single output. There are also types that can
switch their inputs to multiple outputs and have arrangements or 4-to-2, 8-to-3 or
even 16-to-4 etc configurations and an example of a simple Dual channel 4 input
multiplexer (4-to-2) is given below:
18

4-to-2 Channel Multiplexer

Here in this example the 4 input channels are switched to 2 individual

output lines but larger arrangements are also possible. This simple 4-to-2
configuration could be used for example, to switch audio signals for stereo preamplifiers or mixers.
Adjustable Amplifier Gain
As well as sending parallel data in a serial format down a single
transmission line or connection, another possible use of multi-channel
multiplexers is in digital audio applications as mixers or where the gain of an
analogue amplifier can be controlled digitally, for example.
Digitally Adjustable Amplifier Gain

Here, the voltage gain of the inverting operational amplifier is dependent

upon the ratio between the input resistor, Rin and its feedback resistor, Rf as
determined in the Op-amp tutorials.
19

A single 4-channel (Quad) SPST switch configured as a 4-to-1 channel multiplexer

is connected in series with the resistors to select any feedback resistor to vary the
value of Rf. The combination of these resistors will determine the overall gain of the
amplifier, (Av). Then the gain of the amplifier can be adjusted digitally by simply
selecting the appropriate resistor combination.
Digital multiplexers are sometimes also referred to as Data Selectors as
they select the data to be sent to the output line and are commonly used in
communications or high speed network switching circuits such as LANs and
Ethernet applications.
Some multiplexer ICs have a single inverting buffer (NOT Gate) connected to the
output to give a positive logic output (logic 1, HIGH) on one terminal and a
complimentary negative logic output (logic 0, LOW) on another different terminal.
It is possible to make simple multiplexer circuits from
standard ANDand OR gates as we have seen above, but commonly
multiplexers/data selectors are available as standard i.c. packages such as the
common TTL 74LS151 8-input to 1 line multiplexer or the TTL 74LS153 Dual 4input to 1 line multiplexer. Multiplexer circuits with much higher number of inputs
can be obtained by cascading together two or more smaller devices.
Then we can see that Multiplexers are switching circuits that just switch or
route signals through themselves, and being a combinational circuit they are
memoryless as there is no signal feedback path. The multiplexer is a very useful
electronic circuit that has uses in many different applications such as signal
routing, data communications and data bus control applications.
When used with a demultiplexer, parallel data can be transmitted in serial form via
a single data link such as a fibre-optic cable or telephone line and converted back
into parallel data once again. The advantage is that only one serial data line is
required instead of multiple parallel data lines. Therefore, multiplexers are
sometimes referred to as data selectors.
Multiplexers can also be used to switch either analogue, digital or video signals,
with the switching current in analogue power circuits limited to below 10mA to
20mA per channel in order to reduce heat dissipation.
A digital comparator or magnitude comparator is a hardware electronic device that
takes two numbers as input in binary form and determines whether one number is
greater than, less than or equal to the other number. Comparators are used
in central processing unit s (CPUs) and microcontrollers (MCUs). A XNOR gate is a
basic comparator, because its output is "1" only if its two input bits are equal.

20

Multiplexing Basics
Multiplexing basically involves taking multiple signals and combining them into
one signal for transmission over a single medium, such as a telephone line. The
input signals can be either analog or digital. The purpose of multiplexing is to
enable signals to be transmitted more efficiently over a given communication
channel, thereby decreasing transmission costs.
A device called a multiplexer (often shortened to "mux") combines the input signals
into one signal. When the multiplexed signal needs to be separated into its
component signals (for example, when your email is to be delivered to its
destination), a device called ademultiplexer (or "demux") is used.
Multiplexing was originally developed in the 1800s for telegraphy. Today,
multiplexing is widely used in many telecommunications applications, including
telephony, Internet communications, digital broadcasting and wireless telephony.

Time Division Multiplexing

In time division multiplexing (TDM), each input signal (or data stream) is assigned
a fixed-length time slot on a communication channel. Each sender transmits a
block of data during its assigned time slot.
For example, lets say that input streams from three sending devices are being
multiplexed into one signal for transmission over a single physical channel. Device
1 transmits a block of data during time slot 1, device 2 transmits a block of data
during time slot 2, and device 3 transmits a block of data during time slot 3. After
device 3 transmits, the cycle begins again with each device transmitting in turn in
its assigned time slot.
A drawback to standard TDM is that each sending device has a reserved time slot
in each cycle, regardless of whether it is ready to transmit. This can result in empty
slots and underutilization of the multiplexed communication channel.
21

Statistical TDM (STDM) represents an improvement over standard TDM. In STDM,

if a sender is not ready to transmit in a cycle, the next sender that is ready can
transmit. This reduces the number of wasted slots and increases the utilization of
the communication channel. STDM data blocks are known as packets and must
contain header information to identify the receiving destination.
Applications that use TDM include long-distance telephone service over a T-1 wire
line and the Global System for Mobile Communications (GSM) standard for cellular
phones. STDM is used in packet-switching networks for LAN and Internet
communications.

Frequency Division Multiplexing

In frequency division multiplexing (FDM), each signal is assigned its own frequency
range (or channel) within a larger frequency band. Frequency ranges for channels
cannot overlap. Frequency bands are often separated by an unused block of the
frequency spectrum to reduce interference.
FDM is used mainly for analog transmissions. It can be used over both wired and
wireless mediums.
An example of an application that uses FDM is FM radio. FM is a band that
occupies the frequency range from 88 MHz to 108 MHz within the larger radio
frequency spectrum. Each radio station transmits at the frequency assigned to its
channel (for example, 95.7 MHz, 98.3 MHz, and so on).
Another application that uses FDM is cable TV. The TV transmission cable carries
all available channels at their assigned frequencies. When you choose a cable
channel with your remote control, the set-top box processes the signal at the
frequency assigned to that channel.

Code Division Multiplexing

22

In code division multiplexing (CDM), signals from multiple senders are transmitted
in an assigned frequency band. CDM uses a principle known as spread spectrum,
in which transmitted signals are spread out over all frequency channels in the
assigned band.
In simplest terms, each signal in a CDM system is multiplexed by means of a
spreading code assigned to the sender. This spreading code modulation increases
the bandwidth required for the signal. The receiver is aware of the spreading code
and uses it to demultiplex the signal.
Although it increases the bandwidth needed for transmission, CDM has the
advantage of being more secure than other types of multiplexing. In CDM
transmissions, an individual users signal is mixed in with the signals of other
users in the frequency band. Without the spreading code required for
demultiplexing an individual signal, CDM transmissions appear merely to be noise
to a receiving device.

23

Digital comparators actually use Exclusive-NOR gates within their design for
comparing their respective pairs of bits. When we are comparing two binary or
BCD values or variables against each other, we are comparing the magnitude of
these values, a logic 0 against a logic 1 which is where the term Magnitude
Comparator comes from.
As well as comparing individual bits, we can design larger bit comparators by
cascading together nof these and produce a n-bit comparator just as we did for
the n-bit adder in the previous tutorial. Multi-bit comparators can be constructed
to compare whole binary or BCD words to produce an output if one word is larger,
equal to or less than the other.
A very good example of this is the 4-bit Magnitude Comparator. Here, two 4-bit
words (nibbles) are compared to each other to produce the relevant output with
one word connected to inputs Aand the other to be compared against connected to
input B as shown below.
4-bit Magnitude Comparator

24

Some commercially available digital comparators such as the TTL 74LS85 or

CMOS 4063 4-bit magnitude comparator have additional input terminals that
allow more individual comparators to be cascaded together to compare words
larger than 4-bits with magnitude comparators of n-bits being produced. These
cascading inputs are connected directly to the corresponding outputs of the
previous comparator as shown to compare 8, 16 or even 32-bit words.

25

LOGIC DIAGRAM

26

27

28

Addersubtractor is a circuit that is capable of adding or subtracting numbers (in

particular, binary). Below is a circuit that does adding or subtractingdepending on
a control signal. It is also possible to construct a circuit that performs both
addition and subtraction at the same time. CS1026 1 BINARY ADDER
SUBTRACTOR The most basic arithmetic operation is the addition of two binary
digits. This simple addition consists of four possible elementary operations: 0 + 0 =
0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10. The first three operations produce a sum of
one digit, but when both augend and addend bits are equal to 1, the binary sum
consists of two digits. The higher significant bit of this result is called a carry.
CS1026 2 CS1026 3 The two's complement of an N-bit number is defined as the
result of subtracting the number from 2^N So two's complement of 3 is 16 - 3 = 13
So 5 + -3 ( 5 + 16 3) Mod 16 (5 -3) Mod 16 2 CS1026 4 The two's complement of
an N-bit number is defined as the complement with respect to 2^N, in other words
the result of subtracting the number from 2^N. This is also equivalent to taking
the ones' complement and then adding one, since the sum of a number and its
ones' complement is all 1 bits. CS1026 5 BINARY ADDERSUBTRACTOR CS1026
6 When the augend and addend numbers contain more significant digits, the carry
obtained from the addition of two bits is added to the next higher order pair of
significant bits. A combinational circuit that performs the addition of two bits is
called a half adder. One that performs the addition of three bits (two significant
bits and a previous carry) is a full adder. The names of the circuits stem from the
fact that two half adders can be employed to implement a full adder Augend. The
first of several addends, or "the one to which the others are added," is sometimes
called the augend CS1026 7 CS1026 8 Implementation of half adder CS1026 9
Full Adder CS1026 10 Full Adder CS1026 11 Implementation of full adder in sumof-products form CS1026 12 Implementation of full adder with two half adders and
an OR gate CS1026 13 Addition of n-bit numbers requires a chain of n full adders
or a chain of one-half adder and n - 1 full adders. In the former case, the input
carry to the least significant position is fixed at 0. Interconnection of four fulladder (FA) circuits to provide a four-bit binary ripple carry adder. CS1026 14
CS1026 15 The augend bits of A and the addend bits of B are designated by
subscript numbers from right to left, with subscript 0 denoting the least significant
bit. The carries are connected in a chain through the full adders. The input carry
29

to the adder is C0, and it ripples through the full adders to the output carry C4.
The S outputs generate the required sum bits. An n-bit adder requires n full
adders, with each output carry connected to the input carry of the next higher
order full adder. CS1026 16 Carry Propagation The addition of two binary numbers
in parallel implies that all the bits of the augend and addend are available for
computation at the same time. As in any combinational circuit, the signal must
propagate through the gates before the correct output sum is available in the
output terminals. The total propagation time is equal to the propagation delay of a
typical gate, times the number of gate levels in the circuit. The longest propagation
delay time in an adder is the time it takes the carry to propagate through the full
adders. CS1026 17 Inverter Delay CS1026 18 Full adder with P and G shown The
signals at Pi and Gi settle to their steady-state values after they propagate through
their respective gates. These two signals are common to all half adders and depend
on only the input augend and addend bits. The signal from the input carry Ci to
the output carry Ci + 1 propagates through an AND gate and an OR gate, which
constitute two gate levels. If there are four full adders in the adder, the output
carry C4 would have 2 * 4 = 8 gate levels from C0 to C4. For an n-bit adder, there
are 2n gate levels for the carry to propagate from input to output. CS1026 19 Gi is
called a carry generate, and it produces a carry of 1 when both Ai and Bi are 1,
regardless of the input carry Ci. Pi is called a carry propagate, because it
determines whether a carry into stage i will propagate into stage i + 1 i.e., whether
an assertion of Ci will propagate to an assertion of Ci + 1 CS1026 20 Carry
lookahead logic CS1026 21 Since the Boolean function for each output carry is
expressed in sum-of-products form, each function can be implemented with one
level of AND gates followed by an OR gate. The three Boolean functions for C1, C2,
and C3 are implemented in the carry lookahead generator. Note that this circuit
can add in less time because C3 does not have to wait for C2 and C1 to propagate;
in fact, C3 is propagated at the same time as C1 and C2. This gain in speed of
operation is achieved at the expense of additional complexity (hardware). CS1026
22 Logic diagram of carry lookahead generator CS1026 23 Four-bit adder with
carry lookahead CS1026 24 74283 4-bit binary Full Adder Connection Diagram
CS1026 25 74283 4-bit binary Full Adder Logic Diagram CS1026 26 Binary
Subtractor Remember that the subtraction A - B can be done by taking the 2s
complement of B and adding it to A. The 2s complement can be obtained by taking
the 1s complement and adding 1 to the least significant pair of bits. The 1s
complement can be implemented with inverters, and a 1 can be added to the sum
through the input carry. CS1026 27 Four-bit addersubtractor (with overflow
detection) CS1026 28 The circuit for subtracting A - B consists of an adder with
inverters placed between each data input B and the corresponding input of the full
adder. The input carry C0 must be equal to 1 when subtraction is performed. The
30

operation thus performed becomes A, plus the 1s complement of B, plus 1. This is

equal to A plus the 2s complement of B. CS1026 29 For unsigned numbers, that
gives A - B if A >= B or the 2s complement of (B A) if A < B. For signed numbers,
the result is A - B, provided that there is no Overflow. Binary numbers in the
signed-complement system are added and subtracted by the same basic addition
and subtraction rules as are unsigned numbers. Therefore, computers need only
one common hardware circuit to handle both types of arithmetic. CS1026 30 The
user or programmer must interpret the results of such addition or subtraction
differently, depending on whether it is assumed that the numbers are signed or
unsigned. An overflow condition can be detected by observing the carry into the
sign bit position and the carry out of the sign bit position. If these two carries are
not equal, an overflow has occurred.

Using the AdderSubtractor

Operation

Note

Unsigned
addition

calculation

Ignore the V-bit

C

Operation
Signed
addition

A3

A2

A1

A0

B3

B2

B1

B0

S3

S2

S1

S0

Note

The addends A & B and

the sum S are all 2s
complements.

calculation
A3

A2

A1

A0

B3

B2

B1

B0

31

Operation

Subtraction
without
overflow
(V=0)

S3

Ignore C & V

S2

Note

Operation

S0

calculation

The minuend A, the

subtrahend B, and the
difference S are all 2s
complements.
o

S1

Ignore C

A3

A2

A1

A0

B3

B2

B1

B0

S3

S2

S1

S0

Note

calculation

Subtraction
The minuend A, the subtrahend
with
B, and the difference S are all
overflow
2s complements.
(V=1)

A3

A2

A1

A0

B3

B2

B1

B0

S3

S2

S1

S0

2s Complement Table

Binary

2s complement

Binary

2s complement

01111

+15

10000

-16

01110

+14

10001

-15
32

01101

+13

10010

-14

01100

+12

10011

-13

01011

+11

10100

-12

01010

+10

10101

-11

01001

+9

10110

-10

01000

+8

10111

-9

00111

+7

11000

-8

00110

+6

11001

-7

00101

+5

11010

-6

00100

+4

11011

-5

00011

+3

11100

-4

00010

+2

11101

-3

00001

+1

11110

-2

00000

+0

11111

-1

Half Adder

The truth table is

33

Simplifying boolean equations or making some Karnaugh map will produce the
same circuit shown below, but start by looking at the results. The column is our
familiar XOR gate, while the Cout column is the AND gate. This device is called a
half-adder for reasons that will make sense in the next section.

or in ladder logic

Full Adder

34

The half-adder is extremely useful until you want to add more that one binary digit
quantities. The slow way to develop a two binary digit adders would be to make a
truth table and reduce it. Then when you decide to make a three binary digit
adder, do it again. Then when you decide to make a four digit adder, do it again.
Then when ... The circuits would be fast, but development time would be slow.
Looking at a two binary digit sum shows what we need to extend addition to
multiple binary digits.
11
11
11
--110
Look at how many inputs the middle column uses. Our adder needs three inputs;
a, b, and the carry from the previous sum, and we can use our two-input adder to
build a three input adder.
is the easy part. Normal arithmetic tells us that if = a + b + Cin and 1 = a + b,
then = 1 + Cin.

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What do we do with C1 and C2? Let's look at three input sums and quickly
calculate:
Cin + a + b = ?
0+0+0=0

0+0+1= 1

0+1+0= 1

1+0+0=1

1 + 0 + 1 = 10

1 + 1 + 0 = 10

0 + 1 + 1 = 10
1 + 1 + 1 = 11

If you have any concern about the low order bit, please confirm that the circuit and
ladder calculate it correctly.
In order to calculate the high order bit, notice that it is 1 in both cases when a + b
produces a C1. Also, the high order bit is 1 when a + b produces a 1 and Cin is a 1.
So We will have a carry when C1 OR (1 AND Cin). Our complete three input adder
is:

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For some designs, being able to eliminate one or more types of gates can be
important, and you can replace the final OR gate with an XOR gate without
changing the results.
We can now connect two adders to add 2 bit quantities.
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A0 is the low order bit of A, A1 is the high order bit of A, B0 is the low order bit of B,
B1 is the high order bit of B, 0is the low order bit of the sum, 1 is the high order
bit of the sum, and Cout is the Carry.

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A two binary digit adder would never be made this way. Instead the lowest order
bits would also go through a full adder.

There are several reasons for this, one being that we can then allow a circuit to
determine whether the lowest order carry should be included in the sum. This
allows for the chaining of even larger sums. Consider two different ways to look at
a four bit sum.
111

1<-+ 11<+-

0110

| 01 | 10

1011

| 10 | 11

----10001

- | ---- | --1 +-100 +-101

If we allow the program to add a two bit number and remember the carry for later,
then use that carry in the next sum the program can add any number of bits the
user wants even though we have only provided a two-bit adder. Small PLCs can
also be chained together for larger numbers.
These full adders can also can be expanded to any number of bits space allows. As
an example, here's how to do an 8 bit adder.

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This is the same result as using the two 2-bit adders to make a 4-bit adder and
then using two 4-bit adders to make an 8-bit adder or re-duplicating ladder logic
and updating the numbers.

Each "2+" is a 2-bit adder and made of two full adders. Each "4+" is a 4-bit adder
and made of two 2-bit adders. And the result of two 4-bit adders is the same 8-bit
adder we used full adders to build.
For any large combinational circuit there are generally two approaches to design:
you can take simpler circuits and replicate them; or you can design the complex
circuit as a complete device.
Using simpler circuits to build complex circuits allows a you to spend less time
designing but then requires more time for signals to propagate through the
transistors. The 8-bit adder design above has to wait for all the Cxout signals to
move from A0 + B0 up to the inputs of 7.
If a designer builds an 8-bit adder as a complete device simplified to a sum of
products, then each signal just travels through one NOT gate, one AND gate and
one OR gate. A seventeen input device has a truth table with 131,072 entries, and
reducing 131,072 entries to a sum of products will take some time.

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When designing for systems that have a maximum allowed response time to
provide the final result, you can begin by using simpler circuits and then attempt
to replace portions of the circuit that are too slow. That way you spend most of
your time on the portions of a circuit that matter.

Half subtractor
The half-subtractor is a combinational circuit which is used to perform subtraction
of two bits. It has two inputs, X (minuend) and Y (subtrahend) and two outputs D
(difference) and B (borrow).

Full subtractor
As in the case of the addition using logic gates, a full subtractor is made
by combining two half-subtractors and an additional OR-gate. A full subtractor has
the borrow in capability (denoted as BORIN in the diagram below) and so
allows cascading which results in the possibility of multi-bit subtraction. The
circuit diagram for a full subtractor is given below.

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