Electrnica Digital III

VHDL y Tarjeta Spartan 3 y 3AN

MC Nicols Quiroz Hernndez

FPGA Design Flow

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F
P
G
A
P
I
N
E
S
SPARTAN3
XC3S200
FT256
-4
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Pines

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Slices de un CLB

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Slice de un
Spartan3

Key Components and Features

200,000-gate Xilinx Spartan-3 XC3S200 FPGA in a 256-ball thin Ball Grid Array
package (XC3S200FT256)
4,320 logic cell equivalents
Twelve 18K-bit block RAMs (216K bits)
Twelve 18x18 hardware multipliers
Four Digital Clock Managers (DCMs)
Up to 173 user-defined I/O signals
2Mbit Xilinx XCF02S Platform Flash, in-system programmable configuration
PROM
1Mbit non-volatile data or application code storage available after FPGA
configuration
Jumper options allow FPGA application to read PROM data or FPGA
configuration from other sources
1M-byte of Fast Asynchronous SRAM
Two 256Kx16 ISSI IS61LV25616AL-10T 10 ns SRAMs
Configurable memory architecture
- Single 256Kx32 SRAM array, ideal for MicroBlaze code images
- Two independent 256Kx16 SRAM arrays
Individual chip select per device
Individual byte enables
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Key Components and Features

3-bit, 8-color VGA display port
9-pin RS-232 Serial Port
DB9 9-pin female connector (DCE connector)
RS-232 transceiver/level translator
Uses straight-through serial cable to connect to computer or workstation
serial port
Second RS-232 transmit and receive channel available on board test
points
PS/2-style mouse/keyboard port
Four-character, seven-segment LED display
Eight slide switches
Eight individual LED outputs
Four momentary-contact push button switches
50 MHz crystal oscillator clock source
Socket for an auxiliary crystal oscillator clock source
FPGA configuration mode selected via jumper settings
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Key Components and Features

Push button switch to force FPGA reconfiguration
LED indicates when FPGA is successfully configured
Three 40-pin expansion connection ports to extend and enhance the
Spartan-3 Starter Kit Board
See www.xilinx.com/s3boards for compatible expansion cards
Compatible with Digilent, Inc. peripheral boards
FPGA serial configuration interface signals available on the A2 and
B1 connectors
- PROG_B, DONE, INIT_B, CCLK, DONE
JTAG port for low-cost download cable
Digilent JTAG download/debugging cable connects to PC parallel port
JTAG download/debug port compatible with the Xilinx Parallel Cable IV and
MultiPRO Desktop Tool
AC power adapter input for included international unregulated +5V power
supply
Power-on indicator LED
On-board 3.3V , 2.5V , and 1.2V regulators
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Xilinx Spartan-3
Starter Kit Board
Block Diagram

Xilinx Spartan-3 Starter Kit Board

(Top Side)

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Xilinx Spartan-3 Starter Kit Board

(Bottom Side)

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Display Characters and

Resulting LED Segment
Control Values

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Switches, Push buttons and LEDs

Los componentes fsicos (leds, switches, displays,

pushbuttons) de la tarjeta estn conectados de manera
nica a los pines en el FPGA.
swicht

sw7

sw6

sw5

sw4

sw3

sw2

sw1

sw0

FPGA Pin

K13

K14

J13

J14

H13

H14

G12

F12

Push Button

BTN3 BTN2 BTN1 BTN0

FPGA Pin

L14

L13

M14

M13

LED

led7

led6

led5

led4

led3

led2

led1

led0

FPGA Pin

P11

P12

N12

P13

N14

L12

P14

K12

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Desplegadores de siete segmentos

Los desplegadores son de nodo comn (se activan con ceros lgicos).
Los 7 segmentos de cada desplegador estn conectados entre si (se activan con un
cero el desplegador).

Anodo Control

AN3

AN2

AN1

AN0

FPGA Pin

E13

F14

G14

D14

Habilita con 0

LED

DP

FPGA Pin

P16

N16

F13

R16

P15

N15

G13

E14

Enciende con 0

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Persistencia
La persistencia de la visin, el cerebro percibe que
los 4 caracteres aparecen simultneamente
encendidos.

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DCBA

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Implementar la siguiente tabla:

Detector de nmeros primos
entity Num_Primos is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
f : out STD_LOGIC);
end num;
architecture Behavioral of Num_Primos is
begin
f<= '1' when (a(3)='0' and a(2)='0' and a(1)='0' and
a(0)='1') else
'1' when (a(3)='0' and a(2)='0' and a(1)='1' and
a(0)='0') else
'1' when (a(3)='0' and a(2)='0' and a(1)='1' and
a(0)='1') else

'0';
end Behavioral;
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Comparador 4 bits

A=B entonces Z= 11
A<B entonces Z= 01
A>B entonces Z= 10

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Entidad
entity Compa4x4 is
Port ( a : in STD_LOGIC_VECTOR (3 downto 0);
b : in STD_LOGIC_VECTOR (3 downto 0);
z : out STD_LOGIC_VECTOR (1 downto 0));
end Compa4x4;

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Arquitectura
comparador 4 bits
architecture Behavioral of Compa4x4 is
begin
process(a, b)
begin
if a=b then
z<= "11";
elsif a<b then
z<= "01";
else
z<= "10";
end if;
end process;
end Behavioral;

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10

Decodificador
Binario a 7 segmentos
Disear un decodificador de binario a 7 segmentos en VHDL.
Implementar en el FPGA (Spartan3).
Mostrar las letras a, b, c, d, f para las combinaciones de 1010 a 1111

a
f

Datos
Binarios

b
c

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Display 7Seg
a
f

b
c

e
d

Dec

21

0
1
2
3
4
5

Hex Bin
pg
C0 1 1
F9
11
A4 1 0
B0 1 0
99
10
92
10

fedcba
000000
111001
100100
110000
011001
010010

6
7
8
9

82
B8
80
98

0
1
0
0

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1
1
1
1

0
0
0
0

0
1
0
1

0
1
0
1

0
0
0
0

1
0
0
0

0
0
0
0
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11

Ejemplo
Describir en VHDL un circuito que multiplexe dos lneas (a y b)
de un bit, a una sola lnea (salida) tambin de un bit; la seal
selec sirve para indicar que a la salida se tiene la lnea a
(selec = '0') o b (selec = '1').

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Entidad
Define las entradas y salidas del circuito, es decir, la caja
negra que lo define.

-- Los comentarios empiezan por dos guiones

ENTITY mux IS
PORT ( a: IN bit;
b: IN bit;
selec: IN bit;
salida: OUT bit);
END mux;

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12

La arquitectura es donde se describe el

comportamiento del circuito.
ARCHITECTURE comportamental OF mux IS
BEGIN
PROCESS(a, b, selec)
BEGIN
IF (selec='0') THEN
salida<=a;
ELSE
salida<=b;
END IF;
END PROCESS;
END comportamental;

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RTL
ARCHITECTURE transferencia OF mux IS
SIGNAL nosel, ax, bx: bit;
BEGIN
nosel <= NOT selec;
ax <= a AND nosel;
Descripcin concurrente o tambin
bx <= b AND selec;
llamada de transferencia entre
registros:
salida <= ax OR bx;
END transferencia;

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13

ARCHITECTURE transferencia OF mux IS

BEGIN
salida <= a WHEN selec='0' ELSE b;
END transferencia;

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componentes
ARCHITECTURE estructura OF mux IS
COMPONENT and2
PORT(e1,e2: IN bit; y: OUT bit);
END COMPONENT;
COMPONENT or2
PORT(e1,e2: IN bit; y: OUT bit);
END COMPONENT;
Seal
COMPONENT inv
componente
PORT(e: IN bit; y: OUT bit);
Entidad de top
END COMPONENT;
SIGNAL ax,bx,nosel: bit;
BEGIN
u0: inv PORT MAP(e=>selec, y=>nosel);
u1: and2 PORT MAP(e1=>a, e2=>nosel, y=>ax);
u2: and2 PORT MAP(e1=>b, e2=>sel, y=>bx);
u3: or2 PORT MAP(e1=>ax, e2=>bx, y=>salida);
END estructura;
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14

Dependiendo de la base en que se especifique el nmero se

puede poner un prefijo B (binario), O (octal), o X
(hexadecimal).
Ejemplo:
B"11101001",
O"126",
X"FE"

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Contador Jonhson bidireccional con bit de paro

The following sequence appears on
outputs Q3-Q0 when shifting left:
0000
0001
0011
0111
1111
1110
1100
1000
0000 (repeats)

The following sequence appears on

outputs Q3-Q0 when shifting right:
0000
1000
1100
1110
1111
0111
0011
0001
0000 (repeats)

I/O PINS:
CLK : input free-running clock
LEFT : input signal to shift left (active-low switch)
RIGHT : input signal to shift right (active-low switch)
STOP : input signal to stop counting (active-low switch)
Q3-Q0 : counter outputs (active-low LEDs; Q0 is right-most)
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RTL

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Entidad contador Jonhson

entity jcounter is
port (
CE : in STD_LOGIC; -- Clock Enable (STOP)
LEFT : in STD_LOGIC; -- Direction Control
CLK : in STD_LOGIC; -- Clock Input
Q : inout STD_LOGIC_VECTOR (3 downto 0) := "0000"
);
end jcounter;

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16

Arquitectura
architecture jcounter_arch of jcounter is
begin
process (CLK)
begin
if (CLK'event and CLK='1') then -- CLK rising edge
if (CE='1') then
if (LEFT='1') then
Q(3 downto 1) <= Q(2 downto 0); -- Shift lower bits (Left Shift)
Q(0) <= not Q(3);
-- Circulate inverted MSB to LSB
else
Q(2 downto 0) <= Q(3 downto 1); -- Shift upper bits (Right Shift)
Q(3) <= not Q(0);
-- Circulate inverted LSB to MSB
end if;
end if;
end if;
end process;
end jcounter_arch;
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Funciones de conversin

<slv_sig> = CONV_STD_LOGIC_VECTOR(<int_sig>, <integer_size>);

un entero a std_Logic_Vector
<int_sig> = CONV_INTEGER(<slv_sig>);
std_Logic_Vector a entero
to_float()
convertir un numero real a flotante.

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17

Contador de 0 a 9
entity conta0a9 is
Port (
ce : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
Q : inout STD_LOGIC_VECTOR (3 downto 0));
end conta0a9;

Nicols Quiroz

Display 7Seg
a
f

b
c

e
d

Dec

35

0
1
2
3
4
5

Hex Bin
pg
C0 1 1
F9
11
A4 1 0
B0 1 0
99
10
92
10

fedcba
000000
111001
100100
110000
011001
010010

6
7
8
9

82
B8
80
98

0
1
0
0

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1
1
1
1

0
0
0
0

0
1
0
1

0
1
0
1

0
0
0
0

1
0
0
0

0
0
0
0
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18

Maquinas de Estado Finito

(FSM)
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FSM
inputs

Mealy FSM
next
state
circuits

FF

output
circuits

output

clk

inputs

Moore FSM
next
state
circuits

FF

output
circuits

output

clk

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19

Read/Write controller
START=0
RW=1

IDLE

RW=0

WRITING

READING

LAST=1

LAST=1

WAITING

Entradas:

Salidas:

START, RW, LAST, CLK

RDSIG= 1, si esta en READING

WRSIG= 1, si esta en WRITING
DONE= 1, si esta en WAITING
En cualquier otro caso son igual cero.
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Entidad

entity Control is
Port ( CLK :
START :
RW :
LAST :
RDSIG :
WRSIG :
DONE :
end Control;

in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
in STD_LOGIC;
out STD_LOGIC;
out STD_LOGIC;
out STD_LOGIC);

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Estados
Utilice un tipo enumerativo para los diferentes estados
type STATE_TYPE is (ST1_IDLE, ST2_READING, ST3_WRITING, ST4_WAITING);
signal CURRENT_STATE, NEXT_STATE : STATE_TYPE;

Esto permite a la herramienta de sntesis una apropiada

codificacin

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COMB: process (CURRENT_STATE, START, RW, LAST)

begin
NEXT_STATE <= ST1_IDLE; --ESTADO DEFAULT
DONE <= '0'; --SALIDAS
RDSIG <= '0';
WRSIG <= '0';
case (CURRENT_STATE) is
when ST1_IDLE =>
if START = '0' then
NEXT_STATE <= ST1_IDLE;
elsif RW = '1' then
NEXT_STATE <= ST2_READING;
else
NEXT_STATE <= ST3_WRITING;
end if;
when ST2_READING =>
RDSIG <= '1'; --SALIDA
if LAST = '0' then
NEXT_STATE <= ST2_READING;
else
NEXT_STATE <= ST4_WAITING;
end if;
when ST3_WRITING =>
WRSIG <= '1'; --SALIDA
if LAST = '0' then
NEXT_STATE <= ST3_WRITING;
else
NEXT_STATE <= ST4_WAITING;
end if;
when ST4_WAITING =>
--when others =>
DONE <= '1'; --SALIDA
NEXT_STATE <= ST1_IDLE;
end case;
end process;
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COMBINACIONAL

ST1_IDLE

ST2_READING

ST3_WRITING

ST4_WAITING
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21

Secuencial
SEC: process (clk)
begin
if (clk'event and clk = '1') then
CURRENT_STATE <= NEXT_STATE;
end if;
end process;

SEC: process (CLK, RST)

begin
if (CLK'event and CLK = '1') then
if (RST = '1') then
CURRENT_STATE <= ST1_IDLE;
else
CURRENT_STATE <= NEXT_STATE;
end if;
end if;
end process;

CON SEAL RESET

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Entradas y salidas
Entradas: switchs
CLK : T9
START : F12
RW : G12
LAST : H14
RST : M13
Salidas: LEDs
RDSIG : K12
WRSIG : P14
DONE : L12

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22

Diseo 1
Letrero con desplazamiento
Realizar un desplegador de mensajes que muestre

HOLA bUAP FCE 11

Movindose de derecha a izquierda (almacenar el
mensaje en una ROM).

Ideas
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Letrero con desplazamiento

Contadores

rst

4
4
4
4

Q0
Q1
Q2
Q3

ROM
16x8
d0
d1
d2
d3

mux

dir

sel

clk

dato

rst
MEF
Div frec

50 MHz

clk

sel
clk1

rst

clk2

clk

AN

clk1?

11 12 1
2
10
9
3
8
4
7 6 5

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clk2?
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23

ROM

dir

dato

entidad?
ROM
16x8

dir

dato

entity ROM_C is
Port ( DIRECCION : in STD_LOGIC_VECTOR (3 downto 0);
DATO : out STD_LOGIC_VECTOR (7 downto 0));
end ROM_C;

10

11

12

13
14

15

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architecture MENSAJE of ROM_C is

type ROM is array(natural range <>) of std_logic_vector(7 downto 0);
constant MENS: ROM(0 to 15):=
(X"89", --H
0
X"C0", --O
1
X"C7", --L
2
X"88", --A
3
X"FF", -4
X"83", --b
5
X"C1", --U
6
X"88", --A
7
X"8C", --P
8
Arquitectura?
X"FF", -9
X"8E", --F
10
X"C6", --C
11
X"86", --E
12
X"FF", -13
XF9", --1
14
XF9" --1
15
);
begin
process (DIRECCION)
begin
DATO <= MENS(conv_integer(unsigned(DIRECCION)));
end process;
end MENSAJE;

ROM

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MEF
Cuntos estados?

MEF

S0

sel

AN
sel

0111
00

AN
sel

1011
01

AN
sel

1101
10

AN
sel

1110
11

rst
AN

S1

clk

S2

S3

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Contadores

rst

Q0
Q1
Q2
Q3

49

Contadores
4 contadores de 4 bits
Contadores?

clk

Q0

"0000"

Q1

"0001"

Q2

"0010"

Q3

"0011"

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25

Multiplexor 4 a 1
4
4
4
4

d0
d1
d2
d3

mux

sel
2

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Cartas ASM

26

Diseo 2
Letrero por palabras
Realizar un desplegador de mensajes que muestre

HOLA bUAP FCE 2010

por palabras.

H O L A
b U A P

Ideas

F C E

2 0 1 0
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S0

Carte ASM

AN

Cuntos estados?

11

01

S1
AN

H O L A
0

11

1011

00

m=?

01

10

F C E

S2
AN

2 0 1 0

00

m=?

10

S0 S1 S2 S3

b U A P

0111

11

1101

00

m=?

10

01

S3
AN

11
10

1110

00

m=?

01

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27

Diseo 2
case (estado) is
when s0 =>
an <= "0111";
if m= "00" then
sal <= "cod H";
elsif m = "01" then
sal <= "cod b";
elsif m = "10" then
sal <= "cod F";
else
sal <= "cod 2";
when s1 =>
<statement>;
when s2=>
<statement>;
when s3 =>
<statement>;
when others =>
<statement>;
end case;
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Spartan 3AN

28

S
p
a
r
t
a
n
3
A
N
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Push-Button
Los Pulsadores no tienen conectado una resistencia, estn
conectados de forma directa, por lo tanto deben
conectarse las resistencias de pulldown.

NET "BOTON1" LOC = "T16" | IOSTANDARD = LVCMOS33 | PULLDOWN ;

Y son terminales de I/O de 3.3 V

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29

C
o
n
f
i
g
u
r
a
c
i

n
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Spartan 3AN

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LEDs

NET
NET
NET
NET
NET
NET
NET
NET

"LED<7>"
"LED<6>"
"LED<5>"
"LED<4>"
"LED<3>"
"LED<2>"
"LED<1>"
"LED<0>"

LOC
LOC
LOC
LOC
LOC
LOC
LOC
LOC

=
=
=
=
=
=
=
=

"W21" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;

"Y22" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"V20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"V19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"U19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"U20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"T19" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
"R20" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8 ;
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Interruptores deslizables

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Push-Button Switches Require an Internal

Pull-up Resistor in the FPGA Input Pin

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Rotary Shaft Encoder Circuitry

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Outputs from Rotary Shaft Encoder Might

Include Mechanical Chatter

UCF Location Constraints

NET "ROT_A" LOC = "T13" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "ROT_B" LOC = "R14" | IOSTANDARD = LVCMOS33 | PULLUP ;
NET "ROT_CENTER" LOC = "R13" | IOSTANDARD = LVCMOS33 | PULLDOWN ;
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Character LCD Interface

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Character LCD Interface

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34