Experience

Re: To find number of cells which are unplaced after

placement?
The dbGet command can used interactively to explore the design. Below are some useful
single line dbGet scripts:
1. To get a list of unplaced instances in the design:
dbGet [dbGet -p top.insts.pStatus unplaced].name
2. To list all the placed instances in the design:
dbGet [dbGet -p top.insts.pStatus placed].name
3. To list all the fixed instances in the design:
dbGet [dbGet -p top.insts.pStatus fixed].name
4. To see what metal layers your block's IO pins are on:
dbGet top.terms.pins.allShapes.layer.name
5. To get a list of NONDEFAULT rules in the design:
dbGet head.rules.name
6. To get NDR applied on a specified net:
dbGet [dbGet -p top.nets.name netName].rule.name
7. To get the placement status of an instance:
dbGet [dbGetInstByName instName].pStatus
8. To get the points of a rectangular routing blockage:
dbGet top.fplan.rBlkgs.shapes.rect
9. To get the points of a rectilinear routing blockage:
dbGet top.fplan.rBlkgs.shapes.poly
10. To get a list of all cell types used in the design:
dbGet -u top.insts.cell.name
(The "-u" filters out duplicate objects.)
11. To get the size of block placement halos:
dbGet [dbGet -p2 top.insts.cell.subClass block*].pHaloTop
dbGet [dbGet -p2 top.insts.cell.subClass block*].pHaloBot
dbGet [dbGet -p2 top.insts.cell.subClass block*].pHaloLeft
dbGet [dbGet -p2 top.insts.cell.subClass block*].pHaloRight
12. To get the size and top/bottom layers of block routing halos:
dbGet [dbGet -p2 top.insts.cell.subClass block*].rHaloSideSize
dbGet [dbGet -p2 top.insts.cell.subClass block*].rHaloBotLayer.name

dbGet [dbGet -p2 top.insts.cell.subClass block*].rHaloTopLayer.name

13. To make sure all your tiehi/lo connections have tie cells (and are not connected to a rail
instead):
dbGet top.insts.instTerms.isTieHi 1
dbGet top.insts.instTerms.isTieLo 1
(Should return "0x0" if all connections have tie cells.
If "1"s are returned, use the following to find the terms that still need a tie cell:)
dbGet [dbGet -p top.insts.instTerms.isTieHi 1].name
dbGet [dbGet -p top.insts.instTerms.isTieLo 1].name
14. To get all insTerm names which are tied to tieLo cells:
dbGet [dbGet -p [dbGet -p2 top.insts.cell.subClass coreTieLo].instTerms.net.allTerms.isInput
1].name
15. To change the routing status of a net (for example, from FIXED to ROUTED):
dbSet [dbGet -p top.nets.name netName].wires.status routed
16. To get the status of your design:
dbGet top.statusIoPlaced
dbGet top.statusPlaced
dbGet top.statusClockSynthesized
dbGet top.statusRouted
dbGet top.statusRCExtracted
dbGet top.statusPowerAnalyzed
17. To find out which layers are used in a net:
dbGet [dbGet -p top.nets.name netName].wires.layer.name
18. To find all the instances of a certain cell type:
dbGet [dbGet -p2 top.insts.cell.name cellName].name
19. To get the size of a cell in the library, but not necessarily in the current design:
dbGet [dbGetCellByName cellName].size
20. To get nets that are marked in the db as clock net:
dbGet [dbGet -p top.nets.isClock 1].name
21. To set all instances with a particular pattern in its name to fixed status:
dbSet [dbGet p top.insts.name *clk*].pStatus fixed
22. To get database units:
dbGet head.dbUnits
23. To get manufacturing grid:
dbGet head.mfgGrid
24. To get physical only cells like filler cell, end cap cell etc:
dbGet [dbGet -p top.insts.isPhysOnly 1].name

25. To filter all the PG pins with direction bidi of a specific instance:
dbGet [dbGet -p [dbGet -p top.insts.name instName].pgCellTerms.inOutDir bidi].name
26. To get class and subClass of a cell:
dbGet [dbGetCellByName cellName].baseClass
dbGet [dbGetCellByName cellName].subClass
27. To find out the instname/cellname of the driver driving a specific net.
set netName <netName>
set inst [dbGet [dbGet -p [dbGet -p top.nets.name $netName].allTerms.isOutput 1].inst]
Puts "Net: $netName, driving inst name: [dbGet $inst.name], driving cell name: [dbGet
$inst.cell.name]"
28. To list all layers for the pin of a cell:
dbGet [dbGet -p selected.cell.terms.name pinName].pins.allShapes.layer.extName
29. Report points of polyon that forms the die area:
dbShape -output polygon [dbGet top.fPlan.boxes]
30. To query the max_cap for a list of cells
set cellPtrList [dbGet -p head.allCells.name BUF*]
foreach cellPtr $cellPtrList {puts "[dbGet $cellPtr.name] [dbFTermMaxCap [dbGet -p
$cellPtr.terms.name <termName>] 1]"}
31. To find all instances with a specify property name "myProp" (string property type) and
value "xyzzy"
set inst_ptrs [dbGet -p top.insts.props {.name == "myProp" && .value == "xyzzy"]
Puts "Instances with property myProp and value xyzzy: [dbGet $inst_ptrs.name]"

Special cells required for Multi-Voltage Design

Posted by Godwin Maben on April 15th, 2007
As discussed in the previous session, Special cells are required for implementing a MultiVoltage design. Today lets discuss about these cells in brief.
(1) Level Shifter
(2) Isolation Cell
(3) Enable Level Shifter
(4) Retention Flops
(5) AON cells
(6) Power Gating Switches/MTCMOS switch
(1) Level Shifter: Purpose of this cell is to shift the voltage from low to high as well as high
to low. Generally buffer type and Latch type level shifters are available. In general H2L LSs
are very simple, L2H LSs are little complex and are in general larger in size(double height)
and have 2 power pins. There are some placement restrictions for L2H level shifter to handle
noise levels in the design. Level shifters are typically used to convert signal levels and protect

against sneak leakage paths. With great care, level shifters can be avoided in some cases, but
this will become less practicable on a wider scale.
(2) Isolation Cell: These are special cells required at the interface between blocks which are
shut-down and always on. They clamp the output node to a known voltage. These cells needs
to be placed in an always on region only and the enable signal of the isolation cell needs to
be always_on. In a nut-shell, an isolation cell is necessary to isolate floating inputs.
There are 2 types of isolation cells (a) Retain 0 (b) Retain 1
(3) Enable Level Shifter: This cell is a combination of a Level Shifter and a Isolation cell.
(4) Retention Flops: These cells are special flops with multiple power supply. They
are typically used as a shadow register to retain its value even if the block in which its
residing is shut-down. All the paths leading to this register need to be always_on and hence
special care must be taken to synthesize/place/route them. In a nut-shell, When design
blocks are switched off for sleep mode, data in all flip-flops contained within the block will
be lost. If the designer desires to retain state, retention flip-flops must be used.
The retention flop has the same structure as a standard master-slave flop. However, the
retention flop has a balloon latch that is connected to true-Vdd. With the proper series of
control signals before sleep, the data in the flop can be written into the balloon latch.
Similarly, when the block comes out of sleep, the data can be written back into the flip-flop.
(5) AON cells: Generally these are buffers, that remain always powered irrespective of where
they are placed. They can be either special cells or regular buffers. If special cells are used,
they have thier own secondary power supply and hence can be placed any where in the
design. Using regular buffers as AON cells restricts the placement of these cells in a specific
region.

Picture above gives an idea about how/why/when they are required. In a nut-shell, If data
needs to be routed through or from sleep blocks to active blocks and If the routing distance is
excessively long or the driving load is excessively large, then buffers might be needed to
drive the nets. In these cases, the always-on buffers can be used.

(6) Power Gating Switches/MTCMOS Switch: MTCMOS stands for multi-threshold

CMOS, where low-Vt gates are used for speed, and high-Vt gates are used for low leakage.
By using high-Vt transistors as header switches, blocks of cells can be switched off to sleepmode, such that leakage power is greatly reduced. MTCMOS switches can be implemented in

various different ways. First, they can be implemented as PMOS (header) or NMOS (footer)
switches. Secondly, their granularity can be implemented on a cell-level (fine-grain) or on a
block-level (coarse-grain). That is, the switches can be either built into every standard cell, or
they can be used to switch off a large design block of standard cells.
Depending on the design characteristics, if these cells are readily available, we can start
looking at how to use these cells in successfully implementing a Multi-Voltage Design.